JPS61144772A - Fixed head type magnetic tape reproducing device - Google Patents

Abstract

PURPOSE:To correct a step out without adjusting the azimuth of a magnetic head by delaying a playback signal of each track according to the quantity of the step-out between playback signals of respective tracks. CONSTITUTION:Synchronizing signal detecting circuits 20 and 22 input output signals of variable delay circuits 14-1 and 14-C of the 1st track and the Cth track (center track) to detect synchronizing signals of the 1st and the Cth tracks, thereby outputting detection signals P1 and Pc at the detection timing. A phase comparator 24 makes a phase comparison between the signals P1 and Pc to output a width pulse signal corresponding to the phase difference to an LPF26, thereby outputting a signal which has the polarity and level corresponding to the direction and quantity of the step-out. A control signal generating circuit 28 calculates the delay time of each delay circuit 14 required to correct the step-out on the basis of the input step-out information on the LPF26 and outputs control signals V1, V2...Vc...Vx required to obtain the delay time, thereby correcting the step-out of each track.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is directed to a fixed head type magnetic tape reproducing device such as a multi-track PCM tape recorder, in which synchronization between each one-rack reproduction signal due to azimuth deviation of the magnetic head is achieved. The present invention relates to a device for correcting misalignment.

[Conventional technology]

The azimuth of the magnetic head in a magnetic tape playback V device refers to the difference in the inclination of the magnetic head on the playback side relative to the direction of the head on the recording side to the magnetic tape. Both grips of the side magnetic head are set at right angles to each other, so that the azimuth error is 0 (2 points).However, in reality, the recording side spatula] is set separately from the head on the head 1 side. Since there is < i′e, an azimuth error j9 will occur between the two.

In multi-track PCM tape recorders, the second
As shown in the figure, each track has a width of 151 in the direction (width direction) perpendicular to the running direction of the magnetic tape 10. Therefore, the magnetic head 12 is
If C azimuth deviation occurs as shown in FIG. 1, simultaneous deviation may occur between track reproduction signals, resulting in errors in the reproduced data.

Conventionally, in order to cope with such a 4j azimuth shift, the angle of the magnetic head has been strictly adjusted. However, such a device has the disadvantage that adjustment is required for each device. Also, even if adjusted,
It was not possible to deal with variations in the recording head at all.

There was also another type that adjusted the azimuth for automatic fishing by slightly moving the magnetic head, but this had the disadvantage that the mechanism for moving the magnetic head was complicated.

[Problem that the invention seeks to solve]

The present invention solves the drawbacks in the prior art, and
The object of the present invention is to provide a fixed head type magnetic reproducing apparatus that can correct the 19 degree deviation between tracks without adjusting the azimuth of the magnetic head.

(Means for Solving the Problems) The present invention has 6 Cs in which a synchronization shift between tracks is detected and a delay is applied to each 1-rack reproduction signal in accordance with this cycle shift.

[For production]

According to the solving means of the present invention, even if a synchronization difference occurs between each of the 1 to 1 rack reproduction signals, a delay is added to each of the 1 to 1 rack reproduction signals according to the discrepancy. , the same !σj deviation can be corrected without adjusting the azimuth of the magnetic head.

(Example 1 An embodiment of this invention is shown in FIG.

In FIG. 1, a multi-track magnetic head (reproducing head) 12 reads data of each rack recorded on a magnetic tape. Each track reproduction signal output from the magnetic head 12 is variable! ! extension circuit 1
4 (14-1, 14-2゜...14-C, l
4-X). j The synchronization detection circuit 16 detects a synchronization difference between tracks and applies a control signal vr of -1°2, . . . , C2 . , X). The delay time of each variable delay circuit 14 is controlled by a corresponding control signal Vi. As a result, each variable delay circuit 14 outputs 14 raw information signals whose LL and synchronization errors have been corrected.

An example of the configuration of the synchronization detection circuit 16 is shown in FIG. J in Figure 3
3, the synchronization signal detection circuits 20 and 22 input the output signals of the variable delay circuits 14 to 1.14-C of the 11th rack J3 and the C1 rack (center track), respectively, and perform synchronization. Detect each signal. Fixed head type PCM
As shown in Figure 4, the tape recorder's data format consists of several sets of data (ripples), which are distributed to each rack and recorded, and the same pattern of synchronization is placed at the beginning of each set. No. 13 is inserted into each track, and a CRC check signal is inserted into each track at the end of each set. The synchronization signal detection circuit 20.22 detects the synchronization signal S of the first track shown in FIG.
1. Detect the synchronizing signal SC of the C-th track, and use the detected timing as shown in FIG. l detection signal P, Pc
output each.

The phase comparator 24 compares the (I2 phase) of the detected signals P and P2 and outputs a width pulse signal corresponding to the phase K as shown in FIG. 【Yo,
[The signal is smoothed by the 1-pass filter 26, and the low-pass filter 26 outputs a signal with a polarity J-3 and a level corresponding to the 1j direction J5 and magnitude of the synchronization shift, as shown in FIG.

Based on the synchronization information inputted from the low-pass filter 26, the control signal generation circuit 28 outputs the ! of each delay circuit 1/I necessary to correct the synchronization difference. ￥Extended time τ, τ2
．． ..., τC1..., τX is set to 0, and the redundant times τ, τ2. ..., τC1...

Control signals V, V2 . necessary to reduce τX by 1q. ....

Vc, . . . , Vx are output.

Here, the (q phase difference of the detected Domei signals S and SC and the delay time τ1゜τ2 necessary to reduce the error by 1 mm)
The relationship between τC1..., τX will be explained below. Here, C1 is carried out for a platform with 8 tracks. FIG. 6 shows each l to rack reproduction signal in a state where a +y1 deviation has occurred. The diagonal line (the part shown is the synchronization signal for each track).

Now, suppose that when the synchronizing signals S and S4 of the first track and the fourth track, which is approximately the same as that of the first track, are detected, there is a one-volt phase difference of time T between them. Since the magnitude of the synchronization difference is uniform between each adjacent i~ rack, the time difference T between the adjacent tracks is obtained by dividing the time difference T by the number of synchronization difference points that exist between the detected tracks. seek. In the example of FIG. 6, C is detected for the 1st track and the 41st rack, and since there are three out-of-synchronization points between them, the time difference t between the adjacent tracks. becomes .

The delay time of each track is fixed to one of the following:
The time difference t is added to the fixed delay time.

The delay time of other tracks can be determined by increasing or decreasing the value. The track on which the delay time is fixed is, for example, the center track, and the delay time τC is set to be in the middle of the delay time change width of the variable fi extension circuit used, which gives the best efficiency <4T.

For example, in the example of Fig. 6, f of the fourth tone
If f, 5F1 is fixed at τC, and the rack delay time for each 1 is set as shown in the table below, the synchronization difference will be 4;'ζ
can be corrected.

By the way, the variable delay circuit 14 can be configured as a voltage control type using a CMOS inverter, for example. As shown in FIG. 7, the CMOS inverter is
Channel MO3-FF: T2O and n-channel MO3-FET
32 are connected between gates and drains, respectively, a power supply voltage V −■ is applied to the sources, a signal is input to the common gate 1 through the input or + ss terminal 34, and the common train is connected to the output terminal 36. It is designed to output an inverted signal of an input signal.

In this CMOS inverter 40, a delay time occurs between the input and the output. This delay time varies continuously depending on the power supply voltage VDD-Vss as shown in FIG. This is the power supply voltage VD
D-■ The inductance of the element changes due to ss.
This is for the purpose of

Therefore, by utilizing this property, the control signal generation circuit 28 generates a control voltage Vi (i=1.
2. ..., C1..., x), and this control 12
11. By controlling the voltage applied to the CMOS inverter 40 to the voltage Vi, the U extension time can be precisely controlled. Each CMOS inverter 40 takes approximately 3 to 5 μs.
By cascading them in multiple stages as shown in FIG. 9, the delay time can be reduced to 1q.

For example, if 10,000 stages are connected, it will become 30/50Tr.
The delay time of LS is C.

Examples of the configuration of the variable delay circuit 14 using a CMOS inverter are shown in FIGS. 10 to 14, and the variable delay circuit 14 in FIG.
S, -F[voltage a applied between T2O and power supply voltage vDD
, I inserted the MOS-F r T42 used for II. The 1-rack playback signal is input from the input terminal 34, and the delayed signal is output from the output terminal 36. The control voltage -v1 is input from the control ill ITI input terminal C1.

In the example of FIG. The more control 2I+electricity 1■vr becomes a larger value, the more ClCM
Reduce the OS inverter/IO mark ++11 electric L1,
Reduce the delay time. Also, lower 1 - rack < 4
．． The control voltage V1 is set to a small value to reduce the voltage applied to the CMOS inverter 40 and shorten the delay time. This corrects the synchronization deviation of each track.

The variable i delay circuit 14 in FIG.
These are installed on both sides of the OS inverter 40. The power supply voltage V for ρ CHISENEL MO8-FET30
During DD, p'y-ψ channel MO8-F [-'/I 2
Insert the n7-channel MOS-F IET32 between the power supply voltage vss and the n-channel MOS-1” f
” T 'I 4 is inserted. In this case, control ?a
The lightning voltage and the control rcv: the control voltage Vi′
using human power t from the control input terminals C1 and C2, respectively.
, 'r, p chitone/l, MO8-FET42 and njiV channel lvl OS-FET44 respectively.

The control voltage V1' is a voltage (V
-Vi=vi' -V)1)
D S S , and in the case of vDD 'SS, vi' = -Vi, which is the variable ' in Figure 12! The i extension circuit 14 is a control MO8-F
'lF T42.44 is installed inside the CMOS inverter 40 in C of b.

The variable d extension circuit 14 in FIG.
The control MO3FEI-44 is used as an intermediary between MOS-FET 30 and 32, which includes 0, and MOS-
MO for control between F E' T 30 and power supply voltage VDD
8-FET/I2 was inserted.

The variable extension circuit 14 in FIG.
,'r! 12. /I The applied voltage is controlled in common to each stage by /I.

[Embodiment 2] Another embodiment of this invention is shown in FIG. This means that the first embodiment (FIG. 1) is a closed loop iI! While the opening time was previously controlled, the delay time was controlled using an oven lube.

Are the parts in common with Figure 1 the same? 'J number 6J. In this device, the synchronization detection circuit 16 inputs each of the magnetic heads 12 from 1 to 1+4:;
The same deviation is detected, and each riT9* extension circuit 11 is changed to Jl and 12[l to correct the same l'1Ilf deviation.

[Variation example] There is a difference in the above embodiment (variable I delay circuit 1 /I i;
! Although the variable delay circuit 1/I of other types can be used, the synchronization detection circuit 1G outputs the control signal Vl according to each type. Make it.

〔Effect of the invention〕

[As explained below, according to the present invention, the synchronization between tracks 1) is detected, the playback signal of each track is detected, and each 1-rack playback signal is delayed to correct the same 1y1 shift. n iF. Since this is done, there is no need to adjust the azimuth of the conventional magnetic spatula 1 to +i, and there is no need for a real mechanism for automatic head 7 azimuth adjustment. In addition, it is necessary to deal with problems such as park sag of the recording head.

/I Detailed Description of Page 1 FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing the state of azimuth deviation of the magnetic head.

Figure 3 shows a concrete example of the synchronization detection circuit 1G in J3 in Figure 1.
There is a block diagram showing rlI.

Figure 4 t, L1, knock to nor f-1 P CM ”r-
A diagram showing the recording format of the camera loader.

The movement 1'1 of the same town detection circuit 16 in FIG. 5 GEL and FIG. 3 is the indicated time chip pt-.

FIG. 6 (Well, it is a time chart 17, which does not show the synchronization loss state of each 1-rack reproduction signal.

FIG. 7 is a circuit diagram C showing a CMOS inverter.

Figure 8 is a characteristic diagram showing the delay time characteristic 11 of the power supply to the C to 10S input circuits in Figure 7. There is a circuit diagram for the connection.

FIGS. 10 to 14 are circuit diagrams Ct'j+ showing examples of the configuration of 1.p/Z of the variable delay circuit 14 of FIG.

FIG. 15 is a schematic diagram showing an embodiment of this optical filter.

10... Magnetic opening, 12... Magnetic head, 1
4 (14-1 to 14-X)-i1 change'f1 extension circuit, 4
0...C~10S inverter.

(Ha7)' 16th figure 2 view Thursday ~ Ya 1 to 1 dance! )l
)! −−β β β Tomoe ≦ 5v voo-vss Figure 8

Claims (1)

[Scope of Claims] A circuit for detecting a synchronization difference between tracks in a magnetic tape playback signal; a variable delay circuit for delaying the magnetic tape playback signal for each track; 1. A fixed head magnetic tape reproducing apparatus comprising: a circuit for controlling a delay time of a delay circuit and outputting a synchronized magnetic tape reproducing signal from the variable delay circuit.