JPS61143808A - Bit modify circuit of sequence control device - Google Patents

Abstract

PURPOSE:To require no large capacity memory and lower a cost by extracting a bit column to a bit modify by a multiplexer and inverting the bit in question by a conformity and 9 non-conforming between a data and a writing data. CONSTITUTION:A memory 11 is connected to a latch circuit 13 and an output gate circuit 14 through a data bus 12 and an output side of the latch circuit 13 is connected to an exclusive OR circuit 15 and a multiplexer 17. To this multiplexer 17, a bit address signal is inputted and 1 bit of a data that the latch circuit 13 stores is selected. A conformity and a non-conformity of the selected bit data selected by an exclusive OR circuit 19 and one bit writing data are detected and outputted through a decoder 20. The data read from the memory 11 is temporarily stored and selected 13 and the conformity and the non-conformity with the writing data are detected. At the time of the non- conformity, an inverted output of the bit data in question is taken out from the decoder 20 and only the selected bit in the exclusive OR circuit 15 is taken out to the memory 11 side.

Description

DETAILED DESCRIPTION OF THE INVENTION The industrial application field of the present invention relates to a sequence control device, and particularly to a bit modification circuit for memory data.

In conventional sequence control, logical operations are performed on a 1-bit basis, and memory writing and reading are required on a 1-bit basis. There is also a need for a sequence control device having a data processing function to be able to write and read data in byte units.

Conventionally, a device of this type is shown in Figure 2 (see Japanese Patent Laid-Open No. 59-43405). 1) The memory elements 18 to 1n of the XN configuration are integrated into one memory by selecting the same address on the byte address bus 2, and giving the bit address decode signal from the decoder 3 as a chip select signal through the AND gate circuit 4. An address of one of the elements is selected. In addition, the memory element 18
Writing and reading of ~1n is controlled by terminal W/H. The data input/output line of the memory element 1a-In is connected to the input of the OR gate 5, and the read 1-bit data is taken out to the terminal bit. Further, to write 1-bit data, 1-bit data is applied to the terminal bit, and the selected memory element 18 to In1C is written through the active state of the gate circuit 6 having a 3-state output. In this case, the gate circuit 6 is activated by the bit/byte switching command applied to the terminal b/BVc. Terminal B is a byte data terminal, and this terminal is used to connect memory elements 1a to 1n.
Byte data is written and read by interrupting each 1 bit. 7ti terminal resistance of each data line,
8 is an output protection resistor of the OR gate 5.

Problems to be Solved by the Invention Conventional sequence control devices require a plurality of memory elements for bit modification, which poses problems such as an increase in the space of the CPU section of the sequence control device and an increase in cost.

Means and Operation for Solving Problems The present invention provides a latch circuit that temporarily stores one word of read data from a memory, a multiplexer that selects one bit of the latch circuit using a bit selection signal, and a multiplexer that selects one bit of the latch circuit using a bit selection signal. a decoder that obtains a decoded output of the bit selection signal from the mismatch output of this exclusive OR; It is equipped with an exclusive OR circuit that inverts the bit data that matches the decoded output of the IIJ decoder, and an output gate circuit that outputs the word data output of this exclusive OR circuit to the memory side. Data is extracted by a multiplexer, and bit modification is determined by exclusive ORing of the extracted bit data and written bit data.

Example Figure 1 is a circuit diagram showing one embodiment of the present invention.

The memory 11 is coupled to a latch circuit 13 and an output gate circuit 14 via a data bus 12, and one word (or one byte) of read data from the memory 11 is sent to the latch circuit 13.
One word (or one byte) of output data from the output gate circuit 14 is written into the memory 11. The output side of the latch circuit 13 is an exclusive OR circuit 15
is connected by its input line 16 to the multiplexer 17.
by its input line 18.

The multiplexer 17 receives a bit address signal as a bit selection signal, and this signal causes the latch circuit 13 to
1 word (or 1 byte) of data stored in ? select. The exclusive OR 19Fi multiplexer 17 inputs the selected bit data and 1-bit write data and detects whether they match or do not match. The decoder 20 receives the detection output of the exclusive OR 19 as an enable input, changes to an enabled state due to the mismatch output, and uses the bit address data as a decode input to obtain its decode output. The inverter circuit 21 is the decoder 2
The inverted outputs of the respective decode terminals are obtained, and these outputs are used as the other input of the exclusive OR circuit 15. The exclusive OR circuit 15 combines the data stored in the latch circuit 13 and the decoder 20.
The inputs are connected so that the bit digits match those of each decoded output. Each bit output of the exclusive OR circuit 15 is connected to the output gate circuit 14 through a connection line 22, and the gate circuit 1
With this configuration, one word (or one byte) of data read from the memory 11 is temporarily stored in the latch circuit L3, and one bit of it is selected by the multiplexer 17. selected based on the signal, and the selected bit data matches the write data by exclusive OR 19;
When a mismatch is detected, the inverted output of the bit data is taken out from the decoder 20, only the bit selected by the exclusive OR circuit 15 is inverted, and the output is sent to the memory 11 side via the output gate circuit 14. It is extracted as modified data.

Effects of the Invention According to the present invention, the relevant bit digit is extracted using a multiplexer for bit modification, and the bit of the relevant digit is inverted depending on whether the data of the extracted bit digit and the written data match or do not match. This has the effect of eliminating the need for a memory element with a relatively large capacity, resulting in a relatively low cost and small space configuration.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a bit modification circuit diagram of a conventional sequence control device. 11...Memory, 13...Latch circuit, 14...
Output gate circuit, 15... exclusive OR circuit, 17.
...Multiplexer, 19...Exclusive OR, 20.
... Decoder, 21... Inverter circuit. =43

Claims (1)

[Claims] A latch circuit that temporarily stores one word of read data from memory, a multiplexer that selects one bit of this latch circuit by a bit selection signal, and a match or mismatch between the selected bit data of this multiplexer and the write bit data. a decoder that obtains a decoded output of the bit selection signal based on the mismatch output of the exclusive OR, and inverts bit data that matches the decoded output of the decoder among the data stored in the latch circuit. 1. A bit modifying circuit for a sequence control device, comprising: an exclusive OR circuit that outputs word data from the exclusive OR circuit; and an output gate circuit that outputs word data output from the exclusive OR circuit to the memory side.