JPS61140260A - Carrier wave recovery circuit - Google Patents

Carrier wave recovery circuit

Info

Publication number
JPS61140260A
JPS61140260A JP59262489A JP26248984A JPS61140260A JP S61140260 A JPS61140260 A JP S61140260A JP 59262489 A JP59262489 A JP 59262489A JP 26248984 A JP26248984 A JP 26248984A JP S61140260 A JPS61140260 A JP S61140260A
Authority
JP
Japan
Prior art keywords
signal
output
complex
quadrant multiplier
carrier wave
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59262489A
Other languages
Japanese (ja)
Inventor
Motoyasu Tanaka
基康 田中
Shinji Ono
小野 愼二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP59262489A priority Critical patent/JPS61140260A/en
Publication of JPS61140260A publication Critical patent/JPS61140260A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/18Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/22Demodulator circuits; Receiver circuits
    • H04L27/227Demodulator circuits; Receiver circuits using coherent demodulation
    • H04L27/2275Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses the received modulated signals
    • H04L27/2277Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses the received modulated signals using remodulation

Abstract

PURPOSE:To obtain very stable recovered carrier wave by using an oscillation signal of a frequency fixed reference oscillator as a reference signal, applying correlation processing with an input signal by a complex correlation device, applying complex number multiplication by a complex 4 quadrant multiplier so as to recover a carrier wave. CONSTITUTION:An output of a phase modulator 6 is a signal obtained by remodulating a reference signal sin(omega0t+alpha) by a demodulation signal from a discriminator 5 and goes to sin[omega0t+theta(t)+alpha]. A complex number correlation device 10 applies correlation between the said remodulation signal and a modulated input signal sin[omega1t+theta(t)]. A part of the modulated input signal inputted to a signal input terminal 1 is inputted to a hybrid 21 of the complex number correlation device after being subject to time adjustment by a delay circuit 8, a real part output R is fed to a 4 quadrant multiplier 23 of a complex number 4 quadrant multiplier 9 and an imaginary part output I is fed to a 4 quadrant multiplier 23'. Then the output signal of the 4 quadrant multiplier 23 and the output signal of the 4 quadrant multiplier 23' are synthesized by a hybrid 26' and the result is fed to a phase detector 3 as a recovered carrier wave C.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明はP S K (Phaae 5hift Ke
eing)位相復調回路に必要な搬送波再生回路の改良
に関する。
[Detailed Description of the Invention] (Industrial Application Field) The present invention is based on PSK (Phaae 5hift Ke
eing) relates to improvements in carrier regeneration circuits required for phase demodulation circuits.

(従来の技術と問題点) 従来、同期検波によるPSK位相復調回路の搬送波再生
回路の多くは電圧制御発振器(VCO)を用いているが
、安定度が悪い為に位相誤差を生じやすく、又、位相ロ
ックループ(phaseLook Loop )を構成
している為、同期外れが生じると引き込みまで時間を要
するので、と、ドロスが大きいという欠点がある。
(Prior art and problems) Conventionally, most of the carrier wave regeneration circuits of PSK phase demodulation circuits using synchronous detection use voltage controlled oscillators (VCOs), but they tend to cause phase errors due to poor stability. Since it constitutes a phase-locked loop (phaseLook Loop), if synchronization occurs, it takes time to pull in, so there is a drawback that there is a large amount of dross.

(問題点を解決するための手段) 本発明は比較的簡単な回路で入力信号に同期した安定な
再生搬送波が得られる搬送波再生回路の提供を目的とし
ている。
(Means for Solving the Problems) An object of the present invention is to provide a carrier wave regeneration circuit that can obtain a stable regenerated carrier wave synchronized with an input signal using a relatively simple circuit.

本発明は上記の目的を達成するために次の構成を有する
The present invention has the following configuration to achieve the above object.

即ち、同期検波方式PSK位相復調回路において、基準
信号を発生する基準発振器と、前記基準信号を受けて被
変調入力信号の復調信号で前記基準信号を再び変調する
位相変調器と、該位相変調器の出力信号と被変調入力信
号との複素相関をとる複素相関器と、該複素相関器の実
部出力と虚部出力の低周波数成分をそれぞれ取り出す低
域ろ波器と、該各低域ろ波器の出力と前記基準信号とを
複素乗算する複素4象限乗算器とからなる搬送波再生回
路である。
That is, in a synchronous detection type PSK phase demodulation circuit, a reference oscillator that generates a reference signal, a phase modulator that receives the reference signal and modulates the reference signal again with a demodulated signal of a modulated input signal, and the phase modulator a complex correlator that takes a complex correlation between the output signal of the output signal and the modulated input signal, a low-pass filter that extracts low frequency components of the real part output and the imaginary part output of the complex correlator, and each of the low-pass filters. This carrier wave regeneration circuit includes a complex four-quadrant multiplier that performs complex multiplication of the output of the wave generator and the reference signal.

(作 用) 以下本発明の搬送波再生回路の作用を説明する。説明の
簡単のためKPSK2相復調回路によシ説明する。
(Function) The function of the carrier wave regeneration circuit of the present invention will be explained below. For ease of explanation, a KPSK two-phase demodulation circuit will be explained.

第1図にその基本回路を示す。Figure 1 shows its basic circuit.

第1図において、1は信号入力端子、2は復調信号出力
端子、3は位相検波器、4は低域ろ波器、5は判定器、
6は位相変調器、7は基準発振器、8は遅延回路で入力
信号と再変調信号の相関をとる為の時間調整を行なう。
In FIG. 1, 1 is a signal input terminal, 2 is a demodulated signal output terminal, 3 is a phase detector, 4 is a low-pass filter, 5 is a determiner,
6 is a phase modulator, 7 is a reference oscillator, and 8 is a delay circuit, which performs time adjustment for correlating the input signal and the re-modulated signal.

9は複素4象限乗算器、10は複素相関器、11はゲー
ト回路で相関をとる信号の最良点をゲートする働きを行
なう。
Numeral 9 is a complex four-quadrant multiplier, 10 is a complex correlator, and 11 is a gate circuit which functions to gate the best point of the signal to be correlated.

又、複素4象限乗算器9はハイブリ、ド26および同2
6′、π/2移相器22′、4象限乗算器23および同
23′から構成される。複素相関器10はハイブリッド
21および同21’、’/2移相器22、相関器(ミキ
サー)24および同24′から構成されている。25お
よび25′は低域ろ波器で複素相関器lOの出力の高周
波成分を除く働きを行なう。
Moreover, the complex four-quadrant multiplier 9 includes hybrid, de 26, and d2
6', a π/2 phase shifter 22', a four-quadrant multiplier 23, and a four-quadrant multiplier 23'. The complex correlator 10 is composed of a hybrid 21 and a hybrid 21', a '/2 phase shifter 22, a correlator (mixer) 24, and a hybrid 24'. 25 and 25' are low-pass filters that serve to remove high frequency components from the output of the complex correlator IO.

今、基準発振器7の信号を5in(−を七〇、被変調入
力信号をsin (町1+I(1))とする。町。
Now, assume that the signal of the reference oscillator 7 is 5in (- is 70, and the modulated input signal is sin (cho 1 + I (1)).

町は信号の角周波数、 α、σ(1)は信号の位相であ
る。
where is the angular frequency of the signal, and α and σ(1) are the phase of the signal.

又、位相変調器6の出力は、基準発振器7の出力信号で
ある基準信号5in(*。t+α)が判定器5からの復
調信号で再変調された信号で5in(−0t + # 
(tl+α)となる。
Further, the output of the phase modulator 6 is a signal obtained by re-modulating the reference signal 5in (*.t+α), which is the output signal of the reference oscillator 7, with the demodulation signal from the determiner 5.
(tl+α).

複素相関器10ではこの再変調信号と被変調入力信号5
in(町1−)−# (1目の相関をとる。この点を詳
細に説明する。
In the complex correlator 10, this re-modulated signal and the modulated input signal 5
in(Town 1-)-# (Take the correlation of the first item. This point will be explained in detail.

信号入力端子1に入力された被変調入力信号の一部は遅
延回路8で時間調整を受けた後複素相関器10のハイブ
リッド21に入力されここで二手に分配されて相関器(
ミキサー)24および同24′へそれぞれ加えられる。
A part of the modulated input signal input to the signal input terminal 1 is time-adjusted by the delay circuit 8, and then input to the hybrid 21 of the complex correlator 10, where it is distributed into two parts and sent to the correlator (
mixers) 24 and 24', respectively.

一方位相変調器6の出力はゲート回路11を経由して複
素相関器10のハイプリ、ド21′に加えられる。
On the other hand, the output of the phase modulator 6 is applied via the gate circuit 11 to the high voltage 21' of the complex correlator 10.

ここで二手に分配されて一方は前記相関器24へ直接加
えられ、他方はjI/2移相器22を経て前記相関器2
4′へ加えられる。
Here, it is divided into two parts, one being directly applied to the correlator 24, and the other being applied to the correlator 2 through the jI/2 phase shifter 22.
Added to 4'.

相関器24および同24′はそれぞれ加えられた信号の
乗算を行なう。そして、それぞれの出力を複素表現すれ
ば相関器24の出力は実部であシ、相関器24′の出力
は虚部となる。これを式で表わすと次のようになる。
Correlators 24 and 24' each perform multiplication of the added signals. If the respective outputs are expressed in complex terms, the output of the correlator 24 will be the real part, and the output of the correlator 24' will be the imaginary part. This can be expressed as a formula as follows.

まず、相関器24の実部出力Rについては、R= si
n (町t+θ(tJ) sin (set+’(tl
+ a )+2θ(tl+α)・・(1) となる。
First, regarding the real part output R of the correlator 24, R=si
n (town t+θ(tJ) sin (set+'(tl
+a)+2θ(tl+α)...(1).

次に1相関器24′の虚部出力Iについては、■=si
n(*、t+ ’ (t) ) cos (a+o t
+θ(1)+−)+2#(t)+α)・・(2) となる。
Next, regarding the imaginary part output I of the 1 correlator 24', ■=si
n(*,t+'(t)) cos(a+o t
+θ(1)+-)+2#(t)+α)...(2).

次いで、実部出力Rは低域ろ波器25f、経由して複素
4象限乗算器9の4象限乗算器23へ加えられ、虚部出
力■は低域ろ波器25′を経由して4象限乗算器23′
へ加えられる。
Next, the real part output R is applied to the 4-quadrant multiplier 23 of the complex 4-quadrant multiplier 9 via the low-pass filter 25f, and the imaginary part output Quadrant multiplier 23'
added to.

ここで、実部信号Rも虚部信号工も低域ろ波器25およ
び同25′を経由しているため前記式(1)および式(
2)の第2項即ち周波数の高い方の信号は遮断されて、
4象限乗算器23および同23′に加えられるのは前記
式(1)および式(2)の第1項の信号だけということ
になる。
Here, since both the real part signal R and the imaginary part signal pass through the low-pass filters 25 and 25', the equation (1) and the equation (
The second term of 2), that is, the higher frequency signal is blocked,
Only the signals of the first terms of equations (1) and (2) are applied to the four-quadrant multipliers 23 and 23'.

一方基準発振器7の出力である基準信号は前記複素4象
限乗算器9のハイブリッド26に加えられ、ここで二手
に分配されその一方は4象限乗算器23へ加えられ、他
の一方は茸/2移相器22′を経由して4象限乗算器2
3′へ加えられている。4象限乗算器23および同23
′ではそれぞれ、加えられている各2つの信号の乗算を
行ないその積R′および工′を出力する。これを式で表
わすと次のようになる。
On the other hand, the reference signal which is the output of the reference oscillator 7 is applied to the hybrid 26 of the complex 4-quadrant multiplier 9, where it is divided into two parts, one of which is applied to the 4-quadrant multiplier 23, and the other one of which is applied to the 4-quadrant multiplier 23. 4-quadrant multiplier 2 via phase shifter 22'
3' is added. Four-quadrant multiplier 23 and four-quadrant multiplier 23
', respectively, performs multiplication of the two added signals and outputs the product R' and the product R'. This can be expressed as a formula as follows.

まず、実部出力凡の系統については4象限乗算器23で
乗算が行なわれその出力R′は= −!−(5ins1
t+sin ((2se−at ) t −#(t)−
2g )) ・・・(3)となる。
First, for the real part output system, multiplication is performed in the four-quadrant multiplier 23, and the output R' is = -! -(5ins1
t+sin ((2se-at) t-#(t)-
2g)) ...(3).

次に、虚部比カニの系統については4象限乗算器23′
で乗算が行なわれその出カニ′は=1(sin #、 
t −5in((2#@−at )t−#(t)−2g
 ) ) ・(4)となる。
Next, for the imaginary part ratio crab system, the four-quadrant multiplier 23'
Multiplication is performed and the output is = 1 (sin #,
t-5in((2#@-at)t-#(t)-2g
) ) ・(4) becomes.

セして、式(3)で表わされる4象限乗算器23の出力
信号と式(4)で表わされる4象限乗算器23′の出力
信号はハイブリッド26′で合成されて再生搬送波Cと
して位相検波器3へ加えられる。
Then, the output signal of the four-quadrant multiplier 23 expressed by equation (3) and the output signal of the four-quadrant multiplier 23' expressed by equation (4) are combined by the hybrid 26' and phase-detected as a recovered carrier wave C. Add to vessel 3.

ハイプリ、ド26′では両信号が加算されるので再生搬
送波Cは C=R’+I’ =ain町t ・・・・・・・・・・・・・・・(5)
となって複素4象限乗算器9の出力、すなわち位相検波
器3に入力される再生搬送波信号は入力信号に同期した
信号となり正しく搬送波が再生されることがわかる。
Since both signals are added in Hypuri and Do26', the reproduced carrier wave C is C=R'+I' = ain town t ・・・・・・・・・・・・・・・(5)
Therefore, it can be seen that the output of the complex four-quadrant multiplier 9, that is, the reproduced carrier wave signal input to the phase detector 3 becomes a signal synchronized with the input signal, and the carrier wave is correctly reproduced.

以上、2相PSK復調について説明したがN相(N=2
”n:正の整数)についても位相検波器が増加すること
と変調回路6が変わるのみで、同様に搬送波再生が出来
ることは明らかである。
The above explained two-phase PSK demodulation, but N-phase (N=2
It is clear that carrier wave regeneration can be similarly performed for "n: a positive integer" by simply increasing the number of phase detectors and changing the modulation circuit 6.

(発明の効果) 以上説明したように、本発明の搬送波再生回路は、周波
数固定の基準発振器の発振信号を基準信号として入力信
号との間で複素相関器による相関処理を行ない次いで複
素4象限乗算器によシ複素乗算を施して搬送波を再生し
ているので、電圧制御発振器を用いた従来の搬送波再生
回路のように電圧制御発振器の温度や経年変化等に起因
する不安定要素を補償するというような必要がなくまた
比較的簡単な回路で非常に安定な再生搬送波が得られる
という利点がある。
(Effects of the Invention) As explained above, the carrier wave recovery circuit of the present invention performs correlation processing using a complex correlator between the oscillation signal of the reference oscillator with a fixed frequency as the reference signal and the input signal, and then performs complex four-quadrant multiplication. Since the carrier wave is regenerated by performing complex multiplication on the device, it is said that unlike conventional carrier wave regeneration circuits using voltage controlled oscillators, it compensates for unstable factors caused by temperature and aging of the voltage controlled oscillator. This method has the advantage that there is no need for this, and a very stable regenerated carrier wave can be obtained with a relatively simple circuit.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、PSK2相復調回路における本発明の搬送波
再生回路の構成を示すブロック図である。 l・・・信号入力端子、  2・・・復調信号出力端子
、3・・・位相検波器、 4・・・低域ろ波器、  5
・・・判定器、  6・・・位相変調器、  7・・・
基準発振器、8・・・遅延回路、  9・・・複素4象
限乗算器、10・・・複素相関器、  11・・・ゲー
ト回路、21.21’・・・ハイブリッド(分配又は合
成器)、22.22’・・・’/2移相器、 23.2
3’・・・4象限乗算器、  24.24’・・・相関
器(ミキサー)、25.25’・・・低域ろ波器、  
26.26’・・・ハイプリ、ド 代理人 弁理士 八 幡 義 博 第 l 図 zt、 z(、z5.w;’ ・・ハイフリ、ソト22
、 d・・・・”/z移S券 23.23・・・4象[来算豚 24、24’・・・・相肩昼 25.2f’・・・・イf!!域ろシ友曙でト。
FIG. 1 is a block diagram showing the configuration of a carrier recovery circuit according to the present invention in a PSK two-phase demodulation circuit. l... Signal input terminal, 2... Demodulated signal output terminal, 3... Phase detector, 4... Low pass filter, 5
...Determiner, 6...Phase modulator, 7...
Reference oscillator, 8...Delay circuit, 9...Complex four-quadrant multiplier, 10...Complex correlator, 11...Gate circuit, 21.21'...Hybrid (distributor or combiner), 22.22'...'/2 phase shifter, 23.2
3'... Four-quadrant multiplier, 24.24'... Correlator (mixer), 25.25'... Low-pass filter,
26.26'...Hai-Furi, Do Agent Patent Attorney Yoshihiro Yahata No. l Figure zt, z(,z5.w;'...Hai-Furi, Soto 22
, d..."/z transfer S ticket 23.23...4 elephants Tomoaki de To.

Claims (1)

【特許請求の範囲】[Claims] 同期検波方式PSK位相復調回路において、基準信号を
発生する基準発振器と、前記基準信号を受けて被変調入
力信号の復調信号で前記基準信号を再び変調する位相変
調器と、該位相変調器の出力信号と被変調入力信号との
複素相関をとる複素相関器と、該複素相関器の実部出力
と虚部出力の低周波数成分をそれぞれ取り出す低域ろ波
器と、該各低域ろ波器の出力と前記基準信号とを複素乗
算する複素4象限乗算器とからなることを特徴とする搬
送波再生回路。
A synchronous detection PSK phase demodulation circuit includes a reference oscillator that generates a reference signal, a phase modulator that receives the reference signal and modulates the reference signal again with a demodulated signal of a modulated input signal, and an output of the phase modulator. A complex correlator that takes a complex correlation between a signal and a modulated input signal, a low-pass filter that extracts low frequency components of a real part output and an imaginary part output of the complex correlator, and each of the low-pass filters. A carrier wave regeneration circuit comprising a complex four-quadrant multiplier that performs complex multiplication by the output of the reference signal and the reference signal.
JP59262489A 1984-12-12 1984-12-12 Carrier wave recovery circuit Pending JPS61140260A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59262489A JPS61140260A (en) 1984-12-12 1984-12-12 Carrier wave recovery circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59262489A JPS61140260A (en) 1984-12-12 1984-12-12 Carrier wave recovery circuit

Publications (1)

Publication Number Publication Date
JPS61140260A true JPS61140260A (en) 1986-06-27

Family

ID=17376500

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59262489A Pending JPS61140260A (en) 1984-12-12 1984-12-12 Carrier wave recovery circuit

Country Status (1)

Country Link
JP (1) JPS61140260A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03153145A (en) * 1989-11-10 1991-07-01 Nec Corp Carrier recovery system
JP2008240889A (en) * 2007-03-27 2008-10-09 Nok Corp Load ring and sealing device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03153145A (en) * 1989-11-10 1991-07-01 Nec Corp Carrier recovery system
JP2008240889A (en) * 2007-03-27 2008-10-09 Nok Corp Load ring and sealing device

Similar Documents

Publication Publication Date Title
JPH02288641A (en) Digital low harmonic down converter
JPS6193746A (en) Spread spectrum communication demodulator
JPH0677932A (en) Spread spectrum receiver
US4942592A (en) Synchronous receiver for minimum shift keying transmission
JPS61140260A (en) Carrier wave recovery circuit
RU2374776C2 (en) Correlation receiver of noise-like signals with minimum frequency manipulation
US3710261A (en) Data-aided carrier tracking loops
JPS5918900B2 (en) demodulator
CN108897014A (en) A kind of no fuzziness receives the anti-multipath method of BOC navigation signal
US3588720A (en) Linear phase demodulator
JPH02281832A (en) Tau-dither circuit
JPH0770995B2 (en) Phase locked loop
JPS60224345A (en) Data transmission system
JPH05344093A (en) Demodulator for spread spectrum communication
JPH08292246A (en) Delay lock loop used in gps signal receiver
JPH0761023B2 (en) Interference compensation circuit
JPS60183858A (en) Clock synchronizing circuit of msk demodulator
KR950016112A (en) Digital Frequency Error Detection / Compensation Method and Circuit in Digital Modulator
SU1046943A1 (en) Correlative receiver of complex phase-modulated signals
JPH0479499B2 (en)
RU2187901C1 (en) Method for inverse-quadrature recovery of phase-keyed signal carrier
RU2037878C1 (en) Correlation device for processing signals with doppler frequency shift
JP2553643B2 (en) Carrier synchronizer
JPH06105898B2 (en) Interference compensation circuit
Thornhill et al. Fine Synchronization of Coherent Frequency Hopping Signals