JPS61140225A - Error correcting device - Google Patents

Abstract

PURPOSE:To reproduce a signal with some degree even when a reproduction is normally impossible and when an error rate is large in the transmission and recording system of such signals that the lower rank of bit such as picture, voice etc. the harder to give influences to characteristic by weighting the length of error correcting code according to the bit position of input data. CONSTITUTION:Input data from a terminal A normally pass through a parallel/ serial converting circuit 34 and become serial signals. When the specified number of bits is reached, error correcting codes are added and a control code is added from a terminal C and transmitted. In the case where error rate increases, the input data are separated from the highest rank bit (MSB) to the lowest rank bit (LSB) by a bit separating circuit 31. When the number of bits of each bit becomes constant, the length of error correcting codes is changed according to a bit position and added by an error correcting code adding circuit 32, and transmitted after adding a control bit from the terminal C in a multiplexing circuit 33. This switching is made by a switching circuit 37.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an error correction device used when recording and transmitting digital signals such as audio and two images.

2. Description of the Related Art With the development of digital technology in recent years, it has become possible to record and transmit images and audio signals as digital signals. Normally, in digital signal recording systems and transmission systems, part of the transmitted data is lost due to noise, etc., so by creating an error correction code and increasing redundancy to a certain degree, lost data can be recovered. Reproduction or error data detection is performed.

A conventional error correction device will be described below with reference to the drawings. FIG. 3 shows the configuration of the encoder-side transmitting section of the conventional error correction apparatus for transmitting digital signals.

In FIG. 3, 1 indicates a plurality of people/a person with a D converter/
A D converter, 2 is a multiplexer for multiplexing the output of the mu/D converter 1; 13 is a parallel/serial converter; 4 is an error converter for generating an error correction code for the serial output of the parallel/serial converter 3; code generation circuit, 6 an additional circuit for adding an error correction signal to the serial output of the parallel/serial converter 3, 6 a control code addition circuit, 7 an interleague circuit, 8 a scramble circuit, 9
is a modulation circuit.

First, the operation of a conventional encoder and especially the error correction portion will be explained. An analog input input from a terminal of the system is converted into a digital signal by a human/D converter 1, and multiplexed by a multiplexer 2. Further, the parallel/serial converter 3 converts it into serial data. The error correction circuit 4 generates an error correction code of a certain length for a certain number of serial data, and the error code adding circuit 5 adds it to the serial data from the parallel/serial converter 3.

A control code for controlling the decoder is added to the control code adding circuit 6. When a certain number of pieces of data (for one frame) have been collected, they are rearranged (interleaved) in an interleague circuit 7, and continuous errors (burst, errors) are converted into random errors. The output of the interleaving circuit T is sent to a scrambling circuit 8 to make the spectral distribution uniform,
Then, the transmitted content is polarized and modulated by the modulation circuit 9, and then transmitted or recorded.

The current method of adding error codes is the method shown in FIG.

Figure 4 shows the interleague structure for one frame.
An example of a matrix is shown, for example, an interleague matrix in mode B of audio in satellite broadcasting.

The error correction code is a 7-bit error correction code for a total of 66 bits of data with a range of 1 pit, 12 bits, 16 bits of audio, 13, 16 bits of audio, 14, 16 bits of audio, 16.7 bits of independent data. 17 is added. In addition, the control and code 11 are at the beginning of the data.
is located.

Problems to be Solved by the Invention However, although the above-mentioned conventional error correction apparatus is effective in a system having an error rate below the scaffold, when the error rate becomes large, correction becomes impossible and reproduction is not possible at all.

The present invention solves the above problem by providing an error correction device that can obtain a certain level of digital reproduction output by changing the way the error correction code is assigned even when the error rate increases considerably. It is.

Means for Solving the Problems In order to solve the above problems, the error correction device of the present invention differs from the conventional error correction method in that it separates the input data from the upper bits to the lower bits and calculates the difference for each bit. The configuration is such that the error correction method is switched between an error correction method in which the error correction code length is changed depending on the bit position.

According to the above-described structure, the present invention improves the correction ability of the upper pits by adding long error correction codes to the upper bits of input data and short error correction codes to the lower bits when the error rate increases. increase. In this way, it is possible to transmit signal systems such as images and audio where errors in higher bits have a particularly large effect.

Even in the case of recording, playback is possible to some extent.

Furthermore, if the total number of error correction codes is the same, the frame configurations can be made the same.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of an error correction device according to an embodiment of the present invention. In Fig. 1, 31 is a bit separation circuit that separates the input digital signal from the upper bit to the lower bit for each pit, and 32 is an error correction code of a length corresponding to the bit position of each pit. Error correction signal addition circuit 32 has error correction signal addition circuits 320 to 340; 33 is a multiplexing circuit that multiplexes the signal to which the error correction code has been added; 34 is a parallel/serial converter that converts the input signal directly from parallel to serial; a serial conversion circuit, 35 an error correction signal addition circuit that adds an error correction code to the output of the parallel/serial conversion circuit 34, 36 a control code addition circuit that adds a control code to the signal to which the error correction code has been added; is a switching circuit that switches the output of the multiplexing circuit 33 and the control code addition circuit 36, and when the error rate is low, it outputs the output signal of the error correction signal addition circuit section to which the error correction code has been added, and when the error rate is high. In this case, the error correction signal addition unit 32 is configured to switch to output the output signal of the multiplexing circuit 33 in which the allocation of error correction codes is changed according to the pit position of the input signal.

The operation of this embodiment will be described below with reference to FIG. First, input data from a terminal usually passes through a parallel/serial conversion circuit 34 to become a serial signal, and then, when the number of bits reaches a certain value, an error correction code is added. Then, a control code from terminal G is added and transmitted.

If the error rate increases, the bit separation circuit 31 separates the input data from the most significant bit (MSB) to the least significant bit (LSB). Then, when the number of pits of each bit becomes constant, the error correction code adding circuit 32 adds the error correction code while changing the length of the error correction code depending on the pit position. Then, the multiplexing circuit 33 adds the control bits from terminal C and transmits them. This switching is performed by a switching circuit 37.

Here, if the total number of bits is the same, it can be realized with the same frame configuration, and the subsequent circuitry can be exactly the same as the conventional one. How to set the error correction code will be explained using FIG. 2. FIG. 2(m) is an example in which the error rate is below a certain level, in which error correction codes of the same length are added to 4 words of data.

Figure 2 (Bl is for a case where the error rate is large, the input is rearranged bit by bit from a word, and an error correction code of a different length is added to each bit. In this example, the first group is the MSB,
The next group is (MSB-1), and the last one is L.
This is a group of SBs, and the length of the error correction code V varies depending on the bit position. If the frames are to be made the same, the total sum of error correction codes may be made the same.

Although all of the above explanations have focused on encoders for transmission, recording, etc., error correction in a decoder can also be realized using the same concept as the method described in this explanation.

Effects of the Invention The present invention weights the length of error correction codes according to the bit position of input data, thereby making it possible to transmit signals that are less likely to affect the characteristics of lower bits, such as images and audio. Even if the error rate is high in the recording system, it is possible to reproduce to some extent even if the same configuration normally would not allow reproduction.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an error correction device according to an embodiment of the present invention, FIG. 2 is a frame configuration diagram showing the error correction method according to FIG. 1, and FIG. 3 is a configuration of a conventional error correction encoder section. FIG. 4 is a block diagram showing a frame configuration of a conventional error correction device. 31... Bit separation circuit, 32... Error correction signal addition unit, 33... Multiplexing circuit, 34
...Parallel/serial conversion circuit, 36...
. . . error correction signal addition circuit, 36 . . . control signal addition circuit, 37 . . . switching circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 (8) (B) (A4j51 data 2 data 4 ---1--11
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−−1−−−−m? Figure 4

Claims (1)

[Claims] bit separation means for separating an input digital signal bit by bit from upper bits to lower bits; first error correction signal addition means for adding an error correction code having a length corresponding to the bit position to each bit; multiplexing means for multiplexing signals to which correction codes have been added; parallel/serial conversion means for converting the input digital signal directly from parallel to serial; and second error correction for adding error correction codes to the converted output. A signal adding means, a control code adding means for adding a control code to a signal added with an error correction code, and a switching means for switching outputs of the control code adding means and the multiplexing means, and when the error rate is low. outputs the output signal of the second error correction signal addition means, and when the error rate becomes high, the first error correction signal addition means changes the allocation of error correction codes according to the bit position of the input signal. error correction device for switching to the output signal of the converting means;