JPS61140207A - Unnecessary signal canceling circuit - Google Patents

Abstract

PURPOSE:To make designing of an integrated circuit easy by providing a circuit that cancels influences of parasitic capacity between nearby pins in an integrated circuit, and thereby widening the degree of freedom of arrangement of pins. CONSTITUTION:A signal canceling circuit 14 is provided in an integrated circuit, and this signal canceling circuit 14 is connected between the output terminal of a circuit 11 and input terminal of a circuit 12, and cancels unnecessary signals that rush in a pin P2. By impressing a signal in the relation of opposite phase to the unnecessary signals to the pin P2 side, the signals that leak from a pin P1 to the pin P2 can be made minimum or almost zero, and reduce influences of leakage. Thus, the degree of freedom of designing of pin arrangement of the integrated circuit is widened, and in its turn contributes to obtain a highly functional IC.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an unnecessary signal canceling circuit that is capable of canceling signals that cause deterioration in circuit characteristics due to capacitance between frame pins of a semiconductor integrated circuit. .

[Technical background of the invention and its problems]

Recently, semiconductor integrated circuits (hereinafter referred to as ICs) have become highly integrated, have high frequencies, and have many built-in functions.

They tend to be packaged in multiple bins. In such an IC device, the IC7 frame bin has parasitic capacitance between lead frames adjacent to each other, adjacent to each other, or even at a larger distance, so that signal induction occurs through this parasitic capacitance, damaging the original circuit characteristics. There are things that happen. In order to prevent this phenomenon, it is necessary to devise a pin arrangement, but the flow of signals around the IC.

Depending on the type and the connection position with other equipment circuits, it may not be possible to prevent the above-mentioned unnecessary induction phenomenon.

Depending on the pin arrangement, unwanted signals may leak or circuit oscillation may occur, making it impossible to maintain desired characteristics. In particular, in order to prevent damage induced by parasitic capacitance, there are significant restrictions on pin arrangement conditions, which requires a great deal of effort in IC design. For example, the feedback R between the input and output of a high gain amplifier is
Oscillation due to K or I inside the color television receiver
In C, when using an external video signal input, there is a phenomenon in which the internal video signal leaks.

[Purpose of the invention]

This invention was made in order to deal with the above-mentioned problems, and is an unnecessary signal canceller that can substantially eliminate induction by providing a signal that cancels out signals induced through parasitic capacitance between predetermined pins. The purpose is to provide circuits.

[Summary of the invention]

In order to achieve the above object, for example, as shown in FIG. Connected integrated circuit 11.
Furthermore, a signal canceling circuit 14 is integrated and connected between 12 and 12.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a basic circuit of the present invention, and 11 is an output bin P.
, 12 is a circuit having an input pin P, I3 is a circuit having an output pin P, and processes a signal from the input pin P.
, lc is assumed to be a signal processing circuit. Here, it is assumed that the output circuit 1 and the circuit 12 are integrated.

In this case, between the bins P1 and 23, an equal parasitic capacitance Cp occurs between the lead frames. Ideally, the signal output from the output circuit 11 should be input to the signal processing circuit 13 via the bin P, undergo predetermined signal processing, and be input to the circuit 12 via the bin P. It is true. However, due to the presence of parasitic capacitance Cp, signals that have not undergone the prescribed processing are directly induced from bin P to P and input to circuit 12fC, deteriorating or deteriorating the original overall characteristics. This will cause confusion.

For example, the output circuit 11 is an output circuit for video intermediate frequency film enhancement;
If the circuit 12 is a chroma signal processing circuit and the signal processing circuit 13 is a tick-off circuit, originally, the bin Pt
K is that only the chroma signal should be dropped, but from bin P, a part of the composite video signal jumps into bin P.

Therefore, in this Komei, one signal canceling circuit J4 is installed inside the integrated circuit.
It is intended to provide This signal canceling circuit 14 is a circuit 1
It is connected between the output terminal of circuit 1 and the input terminal of circuit 120, and is a circuit that cancels out the unnecessary signal that jumps into the bin PtK. The goal is to achieve the following. As a result, the signal leaking from bin P to bin P can be minimized or almost zero, and the influence of leakage can be substantially reduced. Therefore, the degree of freedom in designing the pin arrangement of an integrated circuit is expanded, and this can contribute to obtaining a highly functional IC.

FIG. 2 shows the circuit of FIG. 1 in more detail at the element level. The transistor Ql and the resistor R1 constitute an emitter follower circuit, and the circuit 11! & is the final output stage. The output signal is placed in bin P1. Let us now assume that the signal applied to P/P is an internal composite video signal V. bottle P
.

The signal V, is sent to the tick-off circuit 1 via the switch SW.
3 can be entered. The switch SW is used to selectively input the internal composite video signal V or the external composite video signal Vo from a video tape recorder or the like to the tick-off circuit 13. The output of the tick-off circuit 13, that is, the chroma signal, is introduced into the bin P, and the chroma signal V applied to the bin P is input into the base of the transistor Q2 constituting the circuit 12. A bias potential V is applied to the base of the transistor Q2 via a resistor R5, and an input bias/beadance is set. Further, an emitter resistor R2 is connected to the emitter of this transistor Q2, so that signal transmission to the next stage can be obtained.

On the other hand, the composite video signal inputted to the base of the output transistor Q) is also inputted to the base of the transistor q3 constituting the signal cancellation circuit 14. This transistor Q
The emitter of No. 3 is connected to the ground potential terminal via the emitter resistor R3, and the collector is connected to the power supply line via the resistor R4 and to the base of the transistor Q4. A signal having a phase opposite to that of the incoming signal is applied to the emitter of the transistor Q4.The collector of the transistor Q4 is connected to the power supply line, and the emitter is connected to the ground potential terminal via the emitter resistor R6, and the capacitor It is connected to the base of the previous transistor Q2 via CI.

Now, assuming that the switch SW is conducting between the terminals ``+so'' and ``+so'', only the chroma signal v3 should be input to the transistor Q2.However, due to the parasitic An unnecessary signal is input to the pin P via the capacitor Cp.However, this unnecessary signal is canceled by a canceling signal input in the opposite phase via the canceling circuit 14.In this case, the unnecessary signal is input to the pin P through the parasitic capacitor Cp. The gain 1 phase of the canceling circuit 14 is set so that the input unnecessary signal and the canceling signal almost match with each other in an antiphase relationship.

Next, when one switch SW conducts between the terminals S and -S in order to select the external composite video signal vt, the above advantages are particularly effective.

That is, when processing signals from an external source such as a video tape recorder, the synchronization relationship with the television signal from the antenna is completely different. Such a received composite video signal reaches the output circuit 11, which is connected to pin Pl+P1.
If input to yP via the parasitic capacitance Cp between them, if this is left as is, large image quality defects will result.

However, in this circuit, the signal leaked through the parasitic capacitance Cp is canceled by the signal cancellation circuit 14, so that a high quality image signal can be obtained.

Now, the parallel impedance between the impedance looking into the signal processing circuit 13 from pin P and the resistor R5 is 2. shall be. The signal Vcp leaking to the transistor Q2 through the parasitic capacitance Cp is transmitted to the transistor Q! through the capacitance CI. The signal vc supplied to the pace of is: If K is selected, ve, + v, key 0 (4). Therefore, the signal leaking through Cp can be substantially canceled out. The cancellation of the leakage signal does not necessarily have to be zero, and it may be sufficient as long as the basic performance is not impaired below a certain level depending on the circuit.

If the general KCp is considerably small and the corresponding C1 is small, then in vcp ωCpz, ·vl (6). Here, if C1 is chosen so that ``'' is obtained, equation (4) is similarly established.

If so, a signal canceling circuit 71A as shown in FIG. 3 may be used. Note that elements corresponding to the circuit in FIG. 2 are designated by the same reference numerals, and description thereof will be omitted.

In an actual rc, the parasitic capacitance Cp between bins PI+P1
In addition to this, there is also the capacitance between the pins of the IC socket.

The wiring pattern capacitance of the board may be added.

In this case, it is only necessary to consider the total capacity of these and decide the amount to be offset.

In FIG. 4, the signal processing circuit 13 is a resistor RIO.

This is an example of delaying a video signal by calling (p, , fl: cz K). Even in such a case, unnecessary signals can be canceled by providing the signal canceling circuit 71B.

In the above embodiment t, some kind of signal processing circuit 13 is connected between the pins P, P, and the signal processing circuit 1
3 does not exist, circuits 11 and 12 are completely unrelated circuits, and the output bin P of circuit 11 is a low impedance output as in the above example, the signal leaking from the bin P side. does not affect the circuit 11 at all. If there is a signal leaking unilaterally to the circuit 12 on the side of bin P, the signal canceling circuit 1
By providing 4C, unnecessary signals can be canceled out, and bin P...
In Figure 5, the circuits 1j and 12 are completely independent signal processing circuits, and the circuits 1j and 12 are completely independent signal processing circuits. and each signal cancellation circuit J (
This is an example in which C is provided.

The signal leaking from bin P to P is transmitted through transistor Q8.
Transistor Q9. It is canceled by a cancellation signal input to the base of the transistor Qll on the side of the bin P via the capacitor C1.

Resistors R11, R12, and R13 are for setting the level of the cancellation signal. Also, the signal leaking from pin yP to P is
Bin p+* via resistor Qll, QIO, capacitor C4
is canceled by a cancellation signal input to the pace of transistor Q8. Resistors R15, R16, and RIO are for setting the level of the cancellation signal.

〔Effect of the invention〕

As described above, according to the present invention, by providing a circuit in the integrated circuit that cancels out the influence of parasitic capacitance between adjacent bins, the degree of freedom in bin arrangement is expanded, and the design of the integrated circuit can be facilitated. It is possible to provide an unnecessary signal cancellation circuit that can greatly contribute to high integration and highly stable functionality.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a specific circuit diagram of the circuit shown in FIG. 1, and FIG. 3 is a circuit diagram showing an embodiment of the invention. FIGS. 4 and 5 are circuit diagrams showing other embodiments of the present invention. 11.12...Circuit, 13...Signal processing circuit, 14
．． 14 people, 14B...signal cancellation circuit, P. P...Bin. Applicant's agent Patent attorney Takehiko Suzue 1st r! ! J Figure 2

Claims (1)

[Scope of Claims] An integrated circuit in which first and second pins connected to first and second circuits, respectively, configured on the same semiconductor chip are led out to the outside, In order to cancel the signal leaked between the first and second pins due to the parasitic capacitance that equivalently occurs between the pins, the leakage signal is canceled between the pin connection portions of the first and second circuits. An unnecessary signal canceling circuit comprising a signal canceling circuit built into the above integrated circuit.