JPS61139049A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS61139049A
JPS61139049A JP26136784A JP26136784A JPS61139049A JP S61139049 A JPS61139049 A JP S61139049A JP 26136784 A JP26136784 A JP 26136784A JP 26136784 A JP26136784 A JP 26136784A JP S61139049 A JPS61139049 A JP S61139049A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
temperature compensating
compensating plate
peripheral
peripheral edge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26136784A
Other languages
Japanese (ja)
Inventor
Tsutomu Nakagawa
勉 中川
Osamu Kurakake
倉掛　修
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP26136784A priority Critical patent/JPS61139049A/en
Publication of JPS61139049A publication Critical patent/JPS61139049A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201—Structure
    • H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83193—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To remove the outer peripheral part of a substrate simultaneously, in soldering the semiconductor substrate to a temperature compensating plate, by not soldering the peripheral part, which is to be removed in a later process in order to stabilize the surface, and only removing the peripheral base part close to the soldered part. CONSTITUTION:Soldering materials 3a and 3b comprising aluminum Al are separately attached to one main surface of a semiconductor substrate 1 and one main surface of a temperature compensating plate 2 except for the peripheral parts. Then, both soldering materials 3a and 3b are contacted and heated in a high vacuum state by a vacuum alloy method. Thus a soldered material 3 is obtained, and the semiconductor substrate 1 and the temperature compensating plate 2 are fixed. At this time, the peripheral part, to which the soldering materials 3a and 3b are not attached, is not fixed. Then, an electrode 4 is formed on the other main surface of the semiconductor substrate 1. Thereafter, sand is jetted from a nozzle 5 in the direction of arrows and broken lines. Thus the peripheral base part of the semiconductor substrate 2, which is not soldered 3 to the temperature compensating plate 2, is slowly removed from the surface.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体装置の製造方法、特に、温度補償板を
ろう付けした半導体基体の周縁部の加工方法の改良に関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and in particular to an improvement in a method for processing a peripheral portion of a semiconductor substrate to which a temperature compensating plate is brazed.

〔従来の技術〕[Conventional technology]

ａ！２図は例えば特公昭４５−１９９４５号公報に示さ
れた半導体装置の一形態を示す断面図で、半導体基体（
１）は温度補償板（２）にろう材（３）によって固着さ
れ、半導体基体（１）の上面には電極（５）が形成され
ている。a! FIG. 2 is a sectional view showing one form of a semiconductor device disclosed in, for example, Japanese Patent Publication No. 45-19945, in which a semiconductor substrate (
1) is fixed to a temperature compensating plate (2) with a brazing material (3), and an electrode (5) is formed on the upper surface of the semiconductor substrate (1).

第３図はこのような半導体装置の表面安定化のための従
来の周縁部加工方法の過程の状態を示す断面図で、まず
、第３図Ａに示すように、この半導体装置を回転させな
がら、その周縁部にノズル（５）から高圧の乾燥空気で
サンド粉体を破線矢印の如く斜めに吹きつけることによ
って傾斜付けを行ない、その後に、フッ酸−硝酸混液で
傾斜付は部のサンド粉体によるダメージ層を除去し、更
に１フェス、ゴムなどで傾斜付は部を覆う。FIG. 3 is a cross-sectional view showing the process of the conventional peripheral edge processing method for stabilizing the surface of such a semiconductor device. First, as shown in FIG. 3A, while rotating the semiconductor device, The slanting is performed by blowing sand powder diagonally from the nozzle (5) as shown by the dashed arrow on the periphery of the periphery using high-pressure dry air. Remove the layer of damage caused by the body, and then cover the sloped area with rubber, etc.

ところが、このような方法では半導体基体（１）の周縁
部がろう材（３）Ｋよって温度補償板（２）に固着して
いるので、上記傾斜付は部の外側の基体周縁部（ｌａ）
が残存する。However, in such a method, since the peripheral edge of the semiconductor substrate (1) is fixed to the temperature compensating plate (2) by the brazing material (3) K, the above-mentioned slanting is applied to the outer peripheral edge of the substrate (la).
remains.

〔発明が解決しようとする問題点３ 以上のような従来の方法で残存した基体周縁部（１ａ）
はサンド粉体吹付は後の７ツ酸−硝酸混液による化学処
理、及びその後の高純水による洗浄において、液循環が
不十分で、処理、洗浄不足になシ易く、表面安定化がは
かり難いという問題点があった。[Problem 3 to be solved by the invention: The peripheral edge of the base (1a) remaining by the conventional method as described above
The problem with sand powder spraying is that during the subsequent chemical treatment with a mixture of 7-nitric acid and nitric acid, and subsequent cleaning with high-purity water, liquid circulation is insufficient, making it easy for the treatment and cleaning to be insufficient, making it difficult to stabilize the surface. There was a point.

この点を避けるために１更に、第３図Ｂに示すように、
第３図Ａのサンドプラスト工程の後Ｋ。In order to avoid this point, 1. Furthermore, as shown in FIG. 3B,
K after the sandplast process in Figure 3A.

更に浅い角度で傾斜付けを行ない、２段ベベル構造にす
る方法もあるが、この場合は上記残存する基体周縁部（
１ａ）をも同時に削シ取る必要があり、作業性が悪く、
なお、二次残存部（１ｂ）が残るという問題点があった
。There is also a method of slanting at an even shallower angle to create a two-stage bevel structure, but in this case, the remaining peripheral edge of the base (
It is necessary to remove 1a) at the same time, which makes work difficult.
Note that there was a problem that a secondary residual portion (1b) remained.

また、第４図に示すようにサンドプラストでほぼ垂直に
削った後、真横方向からサンドプラストを行い、半導体
基体（１）の周縁端面をΣ形状とするダブルポジティブ
形状の半導体装置とする方法も考えられるが、これも第
１段階の垂直方向くサンドプラストで掘込んだ後、その
外側に残存する基体周縁部を完全に除去する必要があり
、上述と同様作業性が悪いという問題点があった。Alternatively, as shown in Figure 4, there is a method in which the semiconductor substrate (1) is sandblasted almost vertically and then sandblasted from the lateral direction to form a double-positive semiconductor device in which the peripheral end face of the semiconductor substrate (1) has a Σ-shape. However, this method also has the problem of poor workability as mentioned above, as it is necessary to completely remove the peripheral edge of the base that remains on the outside after the first stage of vertical sandblast excavation. Ta.

この発明はかかる問題点を解消するためＫなされたもの
で、温度補償板にろう付けした半導体基体の周縁部を効
率よく加工できる半導体装置の製造方法を提供すること
を目的としている。The present invention has been made to solve these problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can efficiently process the peripheral edge of a semiconductor substrate brazed to a temperature compensating plate.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係る半導体装置の製造方法では、半導体基体
を温度補償板にろう付けするに当って、後工程で、表面
安定化のために除去すべき周縁部はろう付けせず忙おく
。In the method for manufacturing a semiconductor device according to the present invention, when brazing the semiconductor substrate to the temperature compensating plate, the peripheral portion to be removed for surface stabilization in a post-process is not brazed.

〔作用〕[Effect]

この発明では、半導体基体の表面安定化のために除去す
べき周縁部が温度補償板にろう付けされていないので、
ろう付は部に近い周縁基底部赤本を除去するのみで、そ
れより外側の基体周縁部が同時に除去される。In this invention, since the peripheral portion to be removed for surface stabilization of the semiconductor substrate is not brazed to the temperature compensating plate,
For brazing, only the peripheral base part near the base part is removed, and the peripheral part of the base body outside it is removed at the same time.

〔実施例〕〔Example〕

第１図Ａ　−Ｄはこの発明の一実施例の主要段階におけ
る状態を示す断面図で、まず、第１図Ａに示すように半
導体基体（１）及び温度補償板（２）にそれぞれ別個に
一方の主百に周縁部を除いてアルミニウム（Ａｔ）から
なるろう材（３ａ）及び（３ｂ）を蒸着などによって、
付着させる。次に、第１図Ｂに示すように１両者のろう
材（３ａ）及び（３ｂ）を互いに接触させ、真空合金方
法で高真空の下で５７０℃程度の温度で加熱処理してろ
う材（３）とし、これによって、半導体基体（１）と温
度補償板（２）とを固着させる。このとき、ろう材（３
ａ　）　＋　（３ｂ）の付着していない周縁部は固着さ
れない。次に、第１図Ｃに示すように半導体基体（１）
の他力の主面上に電１ｍ（４３を形成する３・その後に
、第１図ＤＫ示すように、ノズル（５）からサンド粉体
を破線矢印のように噴出させ、半導体基体（１）の温度
補償板（２）にろう材（３）で固着されていない周縁部
の基底部分を七の表面から徐々に除去し、底面に達する
と当該周縁部の上記基底部分より外側の基体周縁部（１
ａ）は自動的に離脱・飛散してしまう。従って、従来の
方法に比して作業工程の大幅な簡素化が可能である。FIGS. 1A to 1D are cross-sectional views showing the main stages of an embodiment of the present invention. First, as shown in FIG. Brazing filler metals (3a) and (3b) made of aluminum (At) are deposited on one of the main parts, except for the peripheral part, by vapor deposition or the like.
Make it adhere. Next, as shown in FIG. 1B, the two brazing fillers (3a) and (3b) are brought into contact with each other, and heat-treated at a temperature of about 570° C. under high vacuum using a vacuum alloying method. 3), thereby fixing the semiconductor substrate (1) and the temperature compensating plate (2). At this time, the brazing material (3
The unattached periphery of a) + (3b) is not attached. Next, as shown in FIG. 1C, the semiconductor substrate (1) is
3. After that, as shown in FIG. 1DK, sand powder is ejected from the nozzle (5) in the direction of the dashed arrow, and the semiconductor substrate (1) is The base part of the peripheral part that is not fixed to the temperature compensating plate (2) with the brazing material (3) is gradually removed from the surface of the base plate, and when the bottom part is reached, the peripheral part of the base body outside the base part of the peripheral part is removed. (1
A) will automatically detach and scatter. Therefore, the working process can be significantly simplified compared to conventional methods.

なお、この実施例では半導体基体周縁部の基底部分の切
離しにサンドプラストを用いたが研削を用いてもよく、
更に１上記実施例では半導体基体及び温度補償板よりも
小さい直径の蒸着Ａｔをろう材として用いたが、上記蒸
着Ａｔの代りにＡｔはく、またはアルミニウム・シリコ
ン（ＡＡ−８ｉ）はくをろう材として用いてもよい。In this example, sandplast was used to separate the base portion of the peripheral edge of the semiconductor substrate, but grinding may also be used.
Furthermore, in the above embodiment, vapor-deposited At having a diameter smaller than that of the semiconductor substrate and the temperature compensation plate was used as a brazing material, but instead of the vapor-deposited At, an At foil or an aluminum silicon (AA-8i) foil may be used as a brazing material. It may also be used as a material.

また、半導体基体には周縁部までＡｔを蒸着し、温度補
償板へのＡｔ蒸着の直径金小さくした場合にも上記実施
例と同様の効果が得られた。Furthermore, the same effect as in the above embodiment was obtained even when At was deposited on the semiconductor substrate up to the peripheral edge and the diameter of the At deposited on the temperature compensating plate was made smaller.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、この発明の方法では半導体基体を
温度補償板にろう付けするに当って、後工程で表面安定
化のために除去すべき周縁部は温度補償板にろう付すせ
ずにおくので、当該周縁部の基底部分のみを切離すのみ
で、それより外側の周縁部は自動的に除去される。従っ
て、工程数の減少及び作業の効率化が可能となる。As explained above, in the method of the present invention, when brazing a semiconductor substrate to a temperature compensating plate, the peripheral portion that should be removed for surface stabilization in a later process is left unbrazed to the temperature compensating plate. Therefore, by simply cutting off only the base portion of the peripheral edge, the peripheral edge outside of it is automatically removed. Therefore, it is possible to reduce the number of steps and improve work efficiency.

【図面の簡単な説明】[Brief explanation of drawings]

第１図Ａ　−Ｄはこの発明の一実施例の主要段階におけ
る状態を示す断面図、第２図は従来の半導体装置の一形
態を示す断面図、第３図ＡｊＢは半導体装置の表面安定
化のための従来の周縁部加工方法の過程の状態を示す断
面図、第４図は従来の方法の他の例における状態を示す
断面図である。 図において、（１）は半導体基体、（１ａ）は半導体基
体の周縁部、（２）は温度補償板、（３）はろう材、（
４）は電極である。 なお、各図中同一符号は同一または相当部分を示す。Figures 1A-D are cross-sectional views showing the main stages of an embodiment of the present invention, Figure 2 is a cross-sectional view showing one form of a conventional semiconductor device, and Figures 3A and 3B are surface stabilization of the semiconductor device. FIG. 4 is a sectional view showing the state of another example of the conventional method. In the figure, (1) is the semiconductor substrate, (1a) is the periphery of the semiconductor substrate, (2) is the temperature compensating plate, (3) is the brazing material, (
4) is an electrode. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (3)

【特許請求の範囲】[Claims] （１）半導体基体の一方の主面をその温度補償板にろう
材を介して固着し、上記半導体基体の他方の主面に電極
を形成した後、上記半導体基体の周縁部を除去しその端
面を傾斜付けするに際して、上記除去すべき上記半導体
基体の周縁部は上記ろう材によつて上記温度補償板に固
着せずにおき、この固着されていない半導体基体の周縁
部の基底部を除去することによつて、当該基底部より外
側の残余の上記半導体基体の周縁部を自動的に除去する
工程を備えたことを特徴とする半導体装置の製造方法。(1) After fixing one main surface of the semiconductor substrate to the temperature compensating plate via a brazing material and forming an electrode on the other main surface of the semiconductor substrate, the peripheral portion of the semiconductor substrate is removed and the end surface of the semiconductor substrate is removed. When tilting the semiconductor substrate, the peripheral edge of the semiconductor substrate to be removed is not fixed to the temperature compensating plate by the brazing material, and the base of the peripheral edge of the semiconductor substrate that is not fixed is removed. A method of manufacturing a semiconductor device, further comprising the step of automatically removing a remaining peripheral edge of the semiconductor substrate outside the base. （２）半導体基体の周縁部の基底部の除去にサンドプラ
ストを用いることを特徴とする特許請求の範囲第１項記
載の半導体装置の製造方法。(2) The method of manufacturing a semiconductor device according to claim 1, wherein sandplast is used to remove the base of the peripheral edge of the semiconductor substrate. （３）半導体基体の周縁部の基底部の除去に研削方法を
用いることを特徴とする特許請求の範囲第１項記載の半
導体装置の製造方法。(3) The method for manufacturing a semiconductor device according to claim 1, wherein a grinding method is used to remove the base portion of the peripheral edge of the semiconductor substrate.
JP26136784A 1984-12-10 1984-12-10 Manufacture of semiconductor device Pending JPS61139049A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26136784A JPS61139049A (en) 1984-12-10 1984-12-10 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26136784A JPS61139049A (en) 1984-12-10 1984-12-10 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS61139049A true JPS61139049A (en) 1986-06-26

Family

ID=17360852

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26136784A Pending JPS61139049A (en) 1984-12-10 1984-12-10 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS61139049A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003515159A (en) * 1999-09-29 2003-04-22 マウンテン ビュー ファーマシューティカルズ，インコーポレイテッド Quantitative detection method of virus by light scattering

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003515159A (en) * 1999-09-29 2003-04-22 マウンテン ビュー ファーマシューティカルズ，インコーポレイテッド Quantitative detection method of virus by light scattering

Similar Documents

Publication Publication Date Title
US8507362B2 (en) Process of forming ultra thin wafers having an edge support ring
US7736747B2 (en) Silicon parts joined by a silicon layer preferably plasma sprayed
JP2005123425A (en) Semiconductor substrate manufacturing method, semiconductor substrate and method for manufacturing semiconductor device
CN1078770C (en) Process for forming electrodes of electronic components and apparatus for use in process
US4892843A (en) Method of manufacturing a semiconductor device
CN108350604B (en) Method and device for producing semiconductor layers
JPS61139049A (en) Manufacture of semiconductor device
JPH08111406A (en) Method of re-etching substrate surface of high dense integrated circuit
JP3084834B2 (en) Method for manufacturing semiconductor device
TW424276B (en) Device for dry etching a defined near-edge portion of at least one surface of a coated wafer, and method therefor by gaseous etching agent
JPS5919325A (en) Etching method
JP2023129237A (en) Crystal wafer and crystal resonator manufacturing method
TWI753135B (en) Ring for protection materials
JPS634938B2 (en)
TW202337052A (en) Crystal wafer and method for manufacturing crystal oscillator capable of preventing concave-and-convex for the crystal wafer and reducing cracks during handling and transportation
JPH0936209A (en) Film formation device and substrate supporting jig for use in this device
JP2600397B2 (en) Method for manufacturing semiconductor device
JPH0427126A (en) Method of manufacturing semiconductor integrated circuit
JPS6348827A (en) Reactive ion etching process
JPS6116686Y2 (en)
JPS5939343A (en) Target used in sputtering
JPS60160126A (en) Manufacture of semiconductor device
JPS62163340A (en) Forming method for wiring of semiconductor integrated circuit
JPS59201425A (en) Processing method for rear side of wafer
JPS612328A (en) Plasma processor