JPS61137427A - Superconductive high-speed circuit - Google Patents

Abstract

PURPOSE:To obtain a logical circuit low in power consumption operating at an extremely high speed by adding Josephson junction in parallel to the output resistance of a Josephson logical circuit and the coupling resistance between logical circuits. CONSTITUTION:An input of an OR gate 1 is normally terminated only with a terminating resistance 4 as its front stage. The speed-up Josephson junction 8 for the front stage is added in parallel to the terminating resistance 4 to increase the operation speed of the OR gate. Namely, the Josephson junction 8 is initially in an conductive state, so when a signal is supplied to the input, a current flows abruptly. When the quantity of the current exceeds some value, the Josephson junction 8 enters a voltage state and a current specified by the terminating resistance 4 flows.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a logic circuit for a computer, and particularly to a Josephson logic circuit suitable for ultra-high-speed operation.

[Background of the invention]

In the field of semiconductors, adding a capacitor or diode in parallel to the output terminal of a logic circuit as a speed-up capacitor in order to increase the speed was seen in 1981, Semiconductor Materials Division, National Conference of the Institute of Electronics and Communication Engineers, 218. It was publicly known. High-speed operation is achieved by adding a capacitor or a differentiator circuit that utilizes the capacitance of a reverse biased diode. However, no consideration had been given to whether similar speed increases could be achieved with superconducting circuits such as Josephson circuits. Further, no consideration was given to the use of a Josephson junction instead of a capacitor.

[Purpose of the invention]

An object of the present invention is to provide a logic circuit that consumes low power and can operate at extremely high speed.

[Summary of the invention]

In order to achieve the above objective of speeding up, by adding a Josephson junction in parallel to the output resistance of the Josephson logic circuit and the coupling resistance between the logic circuits, the operating speed can be increased by up to 40%. It was b.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of a circuit in which the present invention is implemented in a flux-coupled quantum interference logic circuit, which is an OR gate.

The input of the ○R gate l in Figure 1 is usually the terminating resistor 4 in the previous stage.
terminated only by By adding a pre-stage speed amplifier Josephson junction 8 in parallel to the termination resistor 4, the operating speed of the OR gate can be increased. In other words, since the Josephson junction 8 is initially in a superconducting state, current flows rapidly when a signal is applied to the input. When the amount of current exceeds a certain value, the Josephson junction 8 enters a voltage state, and a current defined by the terminating resistor 4 flows. FIG. 2 shows the input/output current waveforms of the OR gate when the speed-up Josephson junction 8 for the front stage is not added.

In Fig. 2, In is the input current waveform from the previous stage, and Ou
t is the output current waveform.

In this case, the gate power supply bias rate was 70%, and the gate delay time between turnouts was 21.5 ps. At this time, the area of the Josephson junction used in the flux-coupled quantum interference circuit is: l, 5μ, superconducting current density: Jc = 500
Four junctions with 0 A/cnf and maximum superconducting current: lm = 75 μA are used, and the circuit current is 0.3 mA. Base electrode is NbN, counter electrode is Pb-In-An
It is an alloy. The terminating resistor 4 at the front stage is 10Ω. FIG. 3 shows the input/output current waveforms when the front-stage speed-up Josephson junction 8 is added in FIG. 1, and the operating conditions are exactly the same as in FIG. 2. The added speed-up Josephson junction 8 for the front stage is a junction with a maximum superconducting current I n =0.15 mA.

In this case, the gate delay time between inputs at the same power supply bias rate of 70% was 18.5 ps, which was a 16% reduction in gate delay time.

FIG. 4 is a graph showing delay times of a single OR gate and a circuit with a speed-up Josephson junction added under various power supply bias conditions. bias rate 50
It was found that the operating speed increases by about 40% at most, and as the bias rate increases, the operating speed decreases, but the operating speed still increases.

FIG. 5 is a circuit diagram when a speed-up Josephson junction is added to the 0R-AND gate.

The added joints are two speed-up Josephson joints 8 for the front stage and speed-up Josephson joint 9 for the connection.
and one speed-up Josephson junction 10 for termination. The terminating resistors 4 and 7 are 10Ω, the interstage coupling resistance 5 is 0.5Ω, and the interstage coupling resistance 6 is 7.5Ω. OR
Gates 1 and 3 are the same flux-coupled quantum interference logic circuits as in FIG. Three types of AND gates were considered: single Josephson junction (single-JJ);
- Resistance coupled logic circuit (RCJL) and current injection logic circuit (CIL). The input current required for the operation of these circuits and the output current to the next stage were all made to be the same. FIG. 6 shows changes in the delay time of the 0R-AND gate depending on the bias rate. The figure also shows changes in delay time when a resistance coupled logic circuit (RCJL) is used for the AND gate and speed-up Josephson junctions 8, 9, and 10 are added. Speed amplifier Josephson junction 8,9. It was found that by adding '10, the speed could be increased by about 30% at a bias rate of 60%, and it was found that even if the bias rate became high, there was an effect of speeding up. Similar effects could be obtained with other single Josephson junctions (single-JJ) and current injection type logic circuits.

Connect the OR gate to other direct-coupled circuits (DCL, RCJL.

A similar effect was obtained even when configured with RCL, 4JL, etc.).

In addition, as a speed-up Josephson junction, junction 1
The effect of speeding up was the same in the case of 1 piece and in the case of 2 pieces joined in series. When making one junction, one of the contact electrodes to the resistor is the base electrode,
The other electrode becomes a counter electrode, making connection difficult.

FIG. 7 is a cross-sectional view of the substrate when two Josephson junctions are joined. In the figure, L6 is the substrate 20a, 20
The base electrode 21 b is an insulating film, 22 is a counter electrode, and 12a and 12b each form a Josephson junction. When using two Josephson junctions, the input,
Both outputs (20a, 20b) serve as base electrodes.

Since the substrate wiring is made of the same material as the base electrode, connection between the terminating resistor and the two Josephson junctions is facilitated. As the speed-up Josephson junction, one or two or more junctions connected in series can be used, and an even number of junctions can be used to facilitate connection to a resistor.

FIG. 8 shows circuit elements added to increase speed. In the Josephson logic circuit, a Josephson junction 11 or a series-connected Josephson junction 12 can be used. Furthermore, the use of semiconductor materials allows the use of Schottky diodes 14. Super Schottky diodes can also be used in superconducting circuits. It has been found that even if two or more of these elements are connected in a row of paddles, the effect of increasing the height can be obtained.

As described above, it has been found that simply adding a Josephson junction or the like to a logic circuit has the effect of increasing the operating speed.

〔Effect of the invention〕

According to the present invention, the speed of the circuit can be increased simply by adding small circuit elements without changing the logic circuit, and this has a significant effect on increasing the integration of Josephson logic circuits. Furthermore, there is an effect that speeding up the circuit can be easily achieved in general superconducting circuits.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram when the present invention is implemented in an OR gate,
Figure 2 is a diagram showing the input/output current waveforms of a single OR gate, Figure 3 is a diagram showing input/output current waveforms when the present invention is implemented in an OR gate, and Figure 4 is a diagram showing the input/output current waveforms when the present invention is implemented with a single OR gate. Figure 5 is a circuit diagram in which the present invention is implemented in an OR-AND gate, and Figure 6 shows the relationship between the delay time and bias rate of the circuit in Figure 5. FIG. 7 is a cross-sectional view of a substrate when two Josephson junctions are connected, and FIG. 8 is a circuit diagram showing circuit elements to be added to increase speed. Explanation of symbols 1...OR gate, 2...AND gate, 3...Next stage OR gate, 4...Previous stage load resistance, 5...Coupling resistance a
. 6...Coupling resistance, 7...Load resistance, 8-...Speed-up Josephson junction for front stage, 9...Speed-up Josephson junction for coupling, lO...Speed-up Josephson junction for termination , 11... Josephson junction, 12... Josephson junction (for series). 13... Capacitor, 14... Schottky diode, 15... Super Schottky diode.

Claims (1)

[Claims] 1. A superconducting high-speed circuit comprising a superconducting thin film, an insulating thin film, and a resistive thin film, which is characterized in that one or more Josephson junctions are connected in parallel to the terminating resistor and coupling resistor of the circuit.