JPH023327B2 - - Google Patents
Info
- Publication number
- JPH023327B2 JPH023327B2 JP59259128A JP25912884A JPH023327B2 JP H023327 B2 JPH023327 B2 JP H023327B2 JP 59259128 A JP59259128 A JP 59259128A JP 25912884 A JP25912884 A JP 25912884A JP H023327 B2 JPH023327 B2 JP H023327B2
- Authority
- JP
- Japan
- Prior art keywords
- speed
- gate
- josephson
- circuit
- josephson junction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000008878 coupling Effects 0.000 claims description 8
- 238000010168 coupling process Methods 0.000 claims description 8
- 238000005859 coupling reaction Methods 0.000 claims description 8
- 239000010409 thin film Substances 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 8
- 239000003990 capacitor Substances 0.000 description 4
- 230000004907 flux Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Landscapes
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
- Logic Circuits (AREA)
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は計算機用論理回路に係り、特に超高速
動作に好適なジヨセフソン論理回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a logic circuit for a computer, and particularly to a Josephson logic circuit suitable for ultra-high-speed operation.
半導体の分野で、論理回路の出力端子に並列に
キヤパシターやダイオードを付加してスピードア
ツプコンデンサとして高速化を図ることは例え
ば、昭和58年度、電子通信学会全国大会半導体材
料部門218に見られるように公知であつた。キヤ
パシタや、逆バイアスしたダイオードの容量を利
用した微分回路を付加して、高速動作を実現する
ものである。しかし、ジヨセフソン回路のような
超電導回路で同様な高速化を実現可能かについて
は検討されていなかつた。また、キヤパシタとで
はなくてジヨセフソン接合を用いる点については
配慮されていなかつた。
In the field of semiconductors, the use of capacitors and diodes in parallel with the output terminals of logic circuits to increase speed was demonstrated in the Semiconductor Materials Division 218 of the 1985 National Conference of the Institute of Electronics and Communication Engineers, for example. It was publicly known. High-speed operation is achieved by adding a capacitor or a differentiator circuit that uses the capacitance of a reverse biased diode. However, no consideration had been given to whether similar speed increases could be achieved with superconducting circuits such as Josephson circuits. Further, no consideration was given to the use of Josephson junctions rather than capacitors.
本発明の目的は低消費電力でしかも、超高速な
動作が可能な論理回路を提供することにある。
An object of the present invention is to provide a logic circuit that consumes low power and can operate at extremely high speed.
上記の目的である高速化を達成するために、ジ
ヨセフソン論理回路の出力抵抗や論理回路間の結
合抵抗に並列にジヨセフソン接合を付加すること
により、最大40％程度、動作速度が速くなること
がわかつた。
In order to achieve the above objective of speeding up, we found that by adding a Josephson junction in parallel to the output resistance of Josephson logic circuits and the coupling resistance between logic circuits, the operating speed can be increased by up to 40%. Ta.
以下、本発明の実施例を図により説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第１図は本発明をORゲートである磁束結合形
量子干渉論理回路に実施した回路の回路図であ
る。第１図のORゲート１の入力は通常、前段の
終端抵抗４のみによつて終端されている。この終
端抵抗４に並列に前段用スピードアツプジヨセフ
ソン接合８を付加することによりORゲートの動
作速度を高速化できる。つまり、ジヨセフソン接
合８は最初超電導状態であるから、入力に信号が
与えられると、電流は急激に流れる。電流量があ
る値を超えると、ジヨセフソン接合８は電圧状態
となり、終端抵抗４で規定される電流が流れるこ
とになる。第２図は前段用スピードアツプジヨセ
フソン接合８を付加しない場合のORゲートの入
出力電流波形である。第２図中、Inは前段からの
入力電流波形であり、Outは出力電流波形であ
る。この場合、ゲートの電源バイアス率は70％で
あり、入出間のゲート遅延時間は21.5psであつ
た。この時、磁束結合形量子干渉回路に用いたジ
ヨセフソン接合は面積：1.5μm2、超電導電流密
度：Jc＝5000A／cm2、最大超電導電流：Im＝
75μAの接合を４個使用しており、回路電流は
0.3mAである。ベース電極はNbN、カウンター
電極はPb−In−An合金である。前段の終端抵抗
４は10Ωである。第３図は、第１図において前段
用スピードアツプジヨセフソン接合８を付加した
場合の入出力電流波形であり、動作条件は第２図
の場合とまつたく同じである。付加した前段用ス
ピードアツプジヨセフソン接合８は最大超電導電
流In＝0.15mAの接合である。この場合、同じ電
源バイアス率70％における入出力間のゲート遅延
時間は18.5psとなり、ゲート遅延時間が16％短く
なつた。 FIG. 1 is a circuit diagram of a circuit in which the present invention is implemented in a flux-coupled quantum interference logic circuit, which is an OR gate. The input of the OR gate 1 in FIG. 1 is normally terminated only by the terminating resistor 4 in the preceding stage. By adding a speed-up Josephson junction 8 for the front stage in parallel to the termination resistor 4, the operating speed of the OR gate can be increased. That is, since Josephson junction 8 is initially in a superconducting state, current flows rapidly when a signal is applied to the input. When the amount of current exceeds a certain value, Josephson junction 8 becomes a voltage state, and a current defined by terminating resistor 4 flows. Figure 2 shows the input/output current waveforms of the OR gate when the speed-up Josephson junction 8 for the front stage is not added. In FIG. 2, In is the input current waveform from the previous stage, and Out is the output current waveform. In this case, the gate power supply bias rate was 70%, and the gate delay time between input and output was 21.5 ps. At this time, the Josephson junction used in the flux-coupled quantum interference circuit has an area of 1.5 μm 2 , a superconducting current density: Jc = 5000 A/cm 2 , and a maximum superconducting current: Im =
Four 75μA junctions are used, and the circuit current is
It is 0.3mA. The base electrode is NbN and the counter electrode is a Pb-In-An alloy. The terminating resistor 4 at the front stage is 10Ω. FIG. 3 shows the input/output current waveforms when the speed-up Josephson junction 8 for the front stage is added in FIG. 1, and the operating conditions are exactly the same as in FIG. 2. The added speed-up Josephson junction 8 for the front stage is a junction with a maximum superconducting current In=0.15 mA. In this case, the gate delay time between input and output at the same power supply bias rate of 70% was 18.5 ps, which was a 16% reduction in gate delay time.
第４図は、種々の電源バイアス条件下におい
て、ORゲート単体とスピードアツプジヨセフソ
ン接合を付加した回路の遅延時間を調べたグラフ
である。バイアス率50％で最大40％程度、動作速
度が増大し、バイアス率が高くなると動作速度の
増加率は小さくなるが依然として動作速度が増大
することがわかつた。 FIG. 4 is a graph showing the delay times of a single OR gate and a circuit with a speed-up Josephson junction added under various power supply bias conditions. It was found that at a bias rate of 50%, the operating speed increases by about 40% at most, and as the bias rate increases, the rate of increase in operating speed decreases, but the operating speed still increases.
第５図はOR−ANDゲートにスピードアツプジ
ヨセフソン接合を付加した場合の回路図である。
付加した接合、前段用スピードアツプジヨセフソ
ン接合８を２個、結合用スピードアツプジヨセフ
ソン接合９を２個、終端用スピードアツプジヨセ
フソン接合１０を１個である。終端抵抗４及び７
は10Ω、段間結合抵抗５は0.5Ω、段間結合抵抗６
は7.5Ωである。ORゲート１及び３は第１図の場
合と同じ磁束結合形量子干渉論理回路である。
ANDゲートは、３種類について検討した、すな
わち、単一ジヨセフソン接合（単一JJ）、抵抗結
合形論理回路（RCJL）、電流注入形論理回路
（CIL）である。これらの回路の動作に必要な入
力電流と次段への出力電流は全て同一になるよう
にした。第６図に、OR−ANDゲートの遅延時間
のバイアス率による変化を示す。図中で、AND
ゲートを抵抗結合形論理回路（RCJL）を用い
て、スピードアツプジヨセフソン接合８，９，１
０を付加した場合の遅延時間の変化も合わせて示
している。スピードアツプジヨセフソン接合８，
９，１０を付加することにより、バイアス率60％
で30％程度高速化できることがわかり、バイアス
率が高くなつても高速化の効果があることがわか
つた。他の単一ジヨセフソン接合（単一JJ）が電
流注入形論理回路においても同様の効果を得るこ
とができた。ORゲートを他の直結形回路
（DCL，RCJL，RCL，4JLなど）で構成しても
同様の効果を得た。また、スピードアツプジヨセ
フソン接合として、接合１個の場合と接合２個を
直列に接合した場合において高速化の効果は同じ
であつた。回路を作製する上で、接合１個の場
合、抵抗への接続電極の一方がベース電極、他方
がカウンター電極となり、接続が難しくなる。 Figure 5 is a circuit diagram when a speed-up Josephson junction is added to the OR-AND gate.
The added joints are two speed-up Josephson junctions 8 for the front stage, two speed-up Josephson junctions 9 for coupling, and one speed-up Josephson junction 10 for the end. Terminal resistors 4 and 7
is 10Ω, interstage coupling resistance 5 is 0.5Ω, interstage coupling resistance 6
is 7.5Ω. OR gates 1 and 3 are the same flux-coupled quantum interference logic circuits as in FIG.
Three types of AND gates were considered: single Josephson junction (single JJ), resistive coupled logic (RCJL), and current injection logic (CIL). The input current required for the operation of these circuits and the output current to the next stage were all made to be the same. FIG. 6 shows changes in the delay time of the OR-AND gate depending on the bias rate. In the diagram, AND
Speed-up Josephson junctions 8, 9, 1 using resistance-coupled logic circuits (RCJL) for the gates.
The change in delay time when 0 is added is also shown. Speed up Josephson junction 8,
By adding 9 and 10, bias rate is 60%
It was found that the speed could be increased by about 30%, and it was found that even if the bias rate was high, there was an effect of speeding up. Another single Josephson junction (single JJ) could achieve similar effects in current injection logic circuits. Similar effects were obtained by configuring the OR gate with other direct-coupled circuits (DCL, RCJL, RCL, 4JL, etc.). Further, as for the speed-up Josephson junction, the effect of speeding up was the same in the case of one junction and in the case of two junctions joined in series. When producing a circuit, in the case of one junction, one of the electrodes connected to the resistor becomes a base electrode and the other becomes a counter electrode, making connection difficult.
第７図は、ジヨセフソン接合を２つ接合した場
合の基板断面図であるが、図において、１６は基
板２０ａ，２０ｂはベース電極２１は絶縁膜、２
２はカウンター電極であり、１２ａ，１２ｂは
夫々ジヨセフソン接合を形成している。２つのジ
ヨセフソン接合を用いた場合、入力、出力２０
ａ，２０ｂが両者ともベース電極となる。基板配
線はベース電極を同一の材質を用いて行なうの
で、終端抵抗と２つのジヨセフソン接合との接続
が容易となる。スピードアツプジヨセフソン接合
としては、１個、あるいは２個以上の接合を直列
に接続したものが使用でき、特に偶数個にすると
抵抗への接続が容易となる。 FIG. 7 is a cross-sectional view of the substrate when two Josephson junctions are bonded together.
2 is a counter electrode, and 12a and 12b each form a Josephson junction. When using two Josephson junctions, the input and output are 20
Both a and 20b become base electrodes. Since the base electrode of the substrate wiring is made of the same material, connection between the terminating resistor and the two Josephson junctions is facilitated. As the speed-up Josephson junction, one or two or more junctions connected in series can be used, and in particular, an even number makes connection to the resistor easier.
第８図は、高速化するために付加した回路素子
を示した。ジヨセフソン論理回路においては、ジ
ヨセフソン接合１１や直列接続したジヨセフソン
接合１２を使用できる。さらに、半導体材料を用
いると、シヨツトキーダイオード１４が使用でき
る。超電導回路ではスーパーシヨツトキダイオー
ドも使用することができる。尚、これらの素子は
直列に２個以上接続しても高個化の効果があるこ
とがわかつた。 FIG. 8 shows circuit elements added to increase speed. In the Josephson logic circuit, Josephson junctions 11 and series-connected Josephson junctions 12 can be used. Furthermore, the use of semiconductor materials allows the use of Schottky diodes 14. Supershot diodes can also be used in superconducting circuits. It has been found that even when two or more of these elements are connected in series, it is possible to increase the number of devices.
以上のように、論理回路に、ジヨセフソン接合
などを付加するだけで動作速度を高速にできると
いう効果があることがわかつた。 As described above, it has been found that simply adding Josephson junctions to logic circuits has the effect of increasing operating speed.
本発明によれば、論理回路を変更することなく
小形の回路素子を付加するだけで回路を高速化で
き、ジヨセフソン集積回路の高集積化に著しい効
果がある。さらに、超電導回路一般にわたつて、
回路の高速化を容易に実現できるという効果があ
る。
According to the present invention, the speed of the circuit can be increased simply by adding a small circuit element without changing the logic circuit, and this has a significant effect on increasing the degree of integration of Josephson integrated circuits. Furthermore, regarding superconducting circuits in general,
This has the effect of easily increasing the speed of the circuit.
第１図は本発明をORゲートに実施した場合の
回路図、第２図はORゲート単体の入出力電流波
形を示す図、第３図はORゲートに本発明を実施
した際の入出力電流波形を示す図、第４図はOR
ゲート単体と本発明を実施したORゲートの電源
バイアス率とゲート遅延時間の関係を示す図、第
５図はOR−ANDゲートに本発明を実施した回路
図、第６図は第５図の回路の遅延時間とバイアス
率の関係を示す図、第７図はジヨセフソン接合を
２つ接続した場合の基板断面図、第８図は高速化
のために付加すべき回路素子を示す回路図であ
る。
符号の説明、１…ORゲート、２…ANDゲー
ト、３…次段ORゲート、４…前段負荷抵抗、５
…結合抵抗ａ、６…結合抵抗ｂ、７…負荷抵抗、
８…前段用スピードアツプジヨセフソン接合、９
…結合用スピードアツプジヨセフソン接合、１０
…終端用スピードアツプジヨセフソン接合、１１
…ジヨセフソン接合、１２…ジヨセフソン接合
（直列用）、１３…キヤパシタ、１４…シヨツトキ
ーダイオード、１５…スーパーシヨツトキーダイ
オード。
Figure 1 is a circuit diagram when the present invention is implemented in an OR gate, Figure 2 is a diagram showing the input/output current waveforms of a single OR gate, and Figure 3 is the input/output current when the present invention is implemented in an OR gate. Diagram showing the waveform, Figure 4 is OR
A diagram showing the relationship between power supply bias rate and gate delay time of a single gate and an OR gate implementing the present invention. Figure 5 is a circuit diagram of an OR-AND gate implementing the present invention. Figure 6 is the circuit of Figure 5. FIG. 7 is a cross-sectional view of a substrate when two Josephson junctions are connected, and FIG. 8 is a circuit diagram showing circuit elements to be added to increase speed. Explanation of symbols, 1...OR gate, 2...AND gate, 3...Next stage OR gate, 4...Previous stage load resistance, 5
...coupling resistance a, 6...coupling resistance b, 7...load resistance,
8...Speed up Josephson junction for front stage, 9
…Speed-up Josephson junction for coupling, 10
…Speed-up Josephson junction for termination, 11
... Josephson junction, 12... Josephson junction (for series), 13... Capacitor, 14... Schottky diode, 15... Super shot key diode.
Claims (1)
超電導回路において、回路の終端抵抗及び結合抵
抗に並列に一個以上のジヨセフソン接合を接続す
ることを特徴とする超電導高速回路。1. A superconducting high-speed circuit comprising a superconducting thin film, an insulating thin film, and a resistive thin film, which is characterized in that one or more Josephson junctions are connected in parallel to the terminating resistor and coupling resistor of the circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59259128A JPS61137427A (en) | 1984-12-10 | 1984-12-10 | Superconductive high-speed circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59259128A JPS61137427A (en) | 1984-12-10 | 1984-12-10 | Superconductive high-speed circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61137427A JPS61137427A (en) | 1986-06-25 |
| JPH023327B2 true JPH023327B2 (en) | 1990-01-23 |
Family
ID=17329702
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59259128A Granted JPS61137427A (en) | 1984-12-10 | 1984-12-10 | Superconductive high-speed circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61137427A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0219268A (en) * | 1988-06-29 | 1990-01-23 | Matsushita Electric Ind Co Ltd | Part collecting apparatus |
-
1984
- 1984-12-10 JP JP59259128A patent/JPS61137427A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0219268A (en) * | 1988-06-29 | 1990-01-23 | Matsushita Electric Ind Co Ltd | Part collecting apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61137427A (en) | 1986-06-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |