JPS61136349A - Fs signal receiver - Google Patents

Abstract

PURPOSE:To cancel in a short time an offset voltage generated in a frequency discriminator by bringing a coupling capacitor to forced charging by a charging use constant-current generating part in which a magnitude and a direction of an output current are varied by an input signal. CONSTITUTION:When a signal from a receiving part 12 is applied to a frequency discriminator 13, an output VDIS of the discriminator 13 becomes that which has superposed a DC offset voltage on a frequency deviation (FS) signal. This output VDIS is inputted to a comparator 16 through a coupling capacitor 14. In this case, if ..the offset voltage is positive and also larger than an amplitude of half of a demodulating signal of the FS signal, an output voltage VOUT of the comparator 16 becomes a high output. Accordingly, a positive input signal is impressed to a charging use constant-current generating part 17, and output currents IOC1, IOC2 are outputted in the positive direction, therefore, the capacitor 14 is brough..t to forced charging. Also, when an absolute value of this charging voltage VC becomes an offset voltage, an offset voltage of the discriminator 13 comes not to be detected in an input of the comparator 16.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to frequency-shifted (FS) signal receivers, and more particularly to:
This relates to the connection between the frequency discriminator and the decoder section.

2. Description of the Related Art Conventionally, this type of receiver has a receiving section 2 as shown in FIG.
A frequency discriminator B is connected to the frequency discriminator B, and the output of the frequency discriminator N is connected to the comparator 2 through a coupling condenser.
It continued for 6km and its output was supplied to the decoder section. In this case, the bias power source Vb2 is applied to the negative input terminal of the frequency discriminator B and the comparator, and is further applied to the positive input terminal of the =7 barretor via the bias resistor B.

When the receiver n receives the FS signal, the output of the frequency discriminator B becomes the FS signal demodulated waveform with the DC offset voltage Voa superimposed on it, as shown in FIG.

As shown in FIG. 5, this DC offset voltage Vos is caused by a difference in the transmission frequency, a difference in the local oscillation frequency of the receiving unit, a frequency difference in the frequency discrimination device, etc. The center frequency of the frequency discriminator produces a frequency difference of Δf, and therefore, the output of the frequency discriminator generates a DC voltage of 8zK.

When the power supply voltage is applied to this receiver and the FS signal is received, the comparator input voltage V(N2) becomes 00 in FIG.
Similarly9, the average value of this input voltage VTN2 is VT112
(AV) changes according to the relationship shown in the following equation due to the time constant determined by the capacitor, the bias resistor δ, and the DC output resistance of the frequency discriminator n.

m=Vxxz(Av)=Vos2@8 C2”2 −
・−・−・−(1) However, the DC output resistance of the frequency discriminator shall be sufficiently smaller than the bias resistance. R2
is the value of bias resistor 2, C2 is the value of ;/capacitor U, t
is the time from power application.

Problems to be Solved by the Invention Therefore, in this conventional example, the demodulated output of the comparator output KFS signal is obtained after a delay of K and time td2 as shown in FIG. 4 (0) Ic, and after the power is applied. time t
A major drawback was that data could not be received during d2.

The present invention has been made in order to eliminate the above-mentioned drawbacks inherent in the prior art.Therefore, an object of the present invention is to forcibly charge the coupling capacitor.
It is an object of the present invention to provide a novel FS signal receiver that stabilizes a comparator voltage in a short time and enables data reception in an extremely short time after power is applied.

Means for Solving the Problems According to the present invention, a receiving section, a frequency discriminator, a coupling connecting the frequency discriminator and the comparator; (output of the comparator) has a charging means for the coupling capacitor in which the direction and magnitude of the charging current change and whose operation is intermittent by an external signal. An FS signal receiver is obtained which is characterized by being able to obtain received data.

Embodiment of the Invention Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. Referring to FIG. 1, one embodiment of the invention includes an antenna 11. Receiver part 1 Frequency discriminator 13° Coupling capacitor 14. Resistor for bias.

Comparator 16. Includes a charging constant current generator 1f.

In FIG. 1, the signal from the receiving section 13 is applied to the frequency discriminator 13, and the output vDxa of the frequency discriminator 13 is a DC offset voltage Voa superimposed on the FSS signal demodulated signal, as shown in the second example. It becomes what is given. VD is FS
Represents the amplitude of the demodulated signal.

The output VDI8 is applied to the comparator 16 via the coupling capacitor 14. In this case, the input voltage V of the comparator 16 is V'DIS+V, where Vc is the terminal voltage of the coupling capacitor 14.
If a is the time t after power is applied, then t-
Since it is Va-Q at 0, the input voltage Vgo is VI
N=VDI day.

Here, if the DC offset voltage Vos is positive, D and VO13>T, then the comparator output voltage VOt
rτ is the Htgh output, so a positive input signal is applied to the charging constant current generator 17, and the output current I is applied in the positive direction.
oc+, 1002 is output.

The output currents OC1 and 002 have the same current value, and Xo
When ol-l0CI2■work is 00, the voltage vO across the capacitor is Vo, -Ioo-t, ・・・・・・・・・・-
(2) However, C is the capacitance t of the coupling capacitor, which is the time from when the power is applied, and when 1v01 becomes the same value as 1Vosl, that is, Vos + Vo = a O, the frequency discriminator 13 The voltage Vos generated at the output of is no longer detected at the comparator input voltage v. In addition,
In the above, the output current Ioa is set such that the time at which 1Vol becomes equal to 1Vo is sufficiently smaller than time t (12 in FIG. 5) (for example, td in FIG. 2).

I am choosing my strength. Also, the conoparator input voltage Vy at this time takes a form as shown in Fig. 2@. Furthermore, if one co/parator output VOUTK is added, as shown in Figure 2 0,
Since data is generated with a delay of time td after power is applied, data can be received in a shorter time after power is applied than in the conventional example described above.

Further, if the DC offset voltage Vos is a negative voltage at the output voltage VDI of the frequency discriminator 13, the output current oa1.1002 of the charging constant current generating section 17 flows in the negative direction, which is different from the case described above. Similarly, voltage - and voltage V○
is canceled.

The operation of the charging constant current generating section 17 is controlled by a signal applied to the control terminal 19 so as to stop when the voltages Vos and Vc mentioned above are canceled.

Furthermore, the characteristics of the charging constant current generating section 17 are shown in FIG. 3(A).
A specific circuit example is shown in Figure 3 (■).

Effects of the Invention As explained above, the present invention connects a frequency discriminator and a comparator using a charging constant current generator whose operation is controlled by an external signal and whose output current changes in magnitude and direction depending on an input signal. By employing a means for forcibly charging the coupling capacitor, it is possible to cancel the offset voltage generated in the frequency discriminator in a short time after power is applied, and to ensure accurate data reception.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention;
Figures 2 (A) to 0 are diagrams showing the voltage waveforms of various parts of the embodiment shown in Figure 181, Figure 3 ■ and @ are characteristic diagrams showing an embodiment of the constant current and current generating part for charging; Specific circuit configuration diagram, 4th
The figure is a block diagram of a conventional example, and Fig. 5 (A) ~
0 is shown in Fig. 4.9 Fig. 1 shows voltage waveforms at various parts of the conventional example.
, FIG. 6 is a diagram showing the input/output characteristics of the frequency discriminator.

Claims (1)

[Claims] a receiving section, a frequency discriminator, a coupling capacitor connecting the frequency discriminator and the comparator, the comparator connected to the coupling capacitor, and determining the direction and magnitude of the charging current of the capacitor based on the output of the comparator. 1. An FS signal receiver comprising a coupling capacitor charging means whose power is changed, and a control terminal controlling an operating time of the coupling capacitor charging means.