JPS6113598B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a drive circuit for a gas discharge panel, and more particularly to a drive circuit for a gas discharge panel that performs memory display by applying alternating sustaining voltage pulses.

A gas discharge panel, also known as a plasma display panel, has electrodes covered with a dielectric layer such as low-melting point glass that are placed opposite or adjacent to each other through a space filled with a discharge gas such as neon. By applying an alternating sustaining voltage pulse to the discharge point at the opposite point or adjacent point of the electrode, and applying a write pulse to the selected discharge point so that the discharge start voltage is higher than the discharge point, the discharge point will be A discharge occurs to form a wall voltage, and after that, the sum of the wall voltage and the sustaining voltage pulse becomes the discharge starting voltage, and a discharge occurs continuously, making it possible to memorize and display by combining selected discharge points.

Furthermore, when a pulse with a narrow pulse width or a pulse with a low peak value is applied as an erasing pulse, the erasing pulse causes a discharge, but does not lead to the formation of a wall voltage, resulting in an erasing action.

In order to drive such a gas discharge panel, the configuration shown in FIG. 1 is usually adopted. In the figure, PDP is a gas discharge panel with X and Y electrodes, DRVX and DRVY are drivers, SUSX,
SUSY is a common maintenance voltage circuit, and DECX and DECY are decoders. Common sustain voltage circuit SUSX, SUSY
A sustaining voltage pulse is continuously applied to the X and Y electrodes of the gas discharge panel PDP, and when address information is added, the decoder
It is decoded by DECX and DECY, and the drivers DRVX and DRVY operate with the decoded output, and in response to operation commands such as write and erase, write pulses or erase are sent from the drivers DRVX and DRVY to the selected X and Y electrodes. A pulse is applied.

It has been proposed that the drivers DRVX and DRVY be configured to correspond to the X and Y electrodes, thereby reducing the load on the output transistors and the like to achieve greater integration.

An object of the present invention is to reduce the number of constituent elements of a driver corresponding to the X and Y electrodes as described above, thereby facilitating integration. Examples will be described in detail below.

FIG. 2 is a main circuit diagram of an embodiment of the present invention,
QX1 to QX7 are transistors, DX1 and DX2 are diodes, DX3 is a Zener diode, and Xi is an output terminal connected to the X electrode of the gas discharge panel.
DRVXi is a driver corresponding to the X electrode consisting of PNP transistors QX2 and QX3, V _Xa , V _S , V _SH , V _S
M is a voltage superimposed during writing and erasing, a sustain voltage, a voltage applied during writing, and a voltage applied during erasing, respectively.

Although FIG. 2 shows only the X side, the Y side has almost the same configuration. FIG. 3 is a waveform diagram explaining the operation, where V _X1 is the voltage applied to the selected X electrode, V _X2 is the voltage applied to the non-selected X electrode, V _Y1 is the voltage applied to the selected Y electrode, and V _Y2 is the voltage applied to the unselected Y electrode, V _A is the voltage applied to the selected discharge point, V ₁₁ and V ₂₁ are the voltages applied to the half-selected discharge point, and V ₂₂ is the voltage applied to the unselected discharge point. voltage.

During the period during which the sustain voltage pulse is applied to SUS, the transistors QX4 and QX4 of the common sustain voltage circuit
QX7 and the transistor on the Y side (not shown) operate in response to a timing signal, and a sustaining voltage pulse is applied to the X electrode connected to the output terminal Xi. At that time, the transistor of the decoder driver
The output of the decoder applied to the base of QX1 is "0". Therefore, the transistor QX1 is turned off and the output line of the decoder driver via the diode DX3 becomes "1", so the transistor
QX2 is turned off and transistor QX3 is turned on.
Then, when transistor QX4 turns on, Vs
Since the voltage is in the forward direction with respect to the PN junction between the collector and base of transistor QX3, it passes from this collector to the base, and then to the diode DX.
2, is applied to the X electrode connected to the output terminal Xi, and the discharge point at the intersection of the X electrode and the Y electrode is
Since it is capacitive, it will be charged by the applied voltage.

Also, when transistor QX7 is turned on after transistor QX4 is turned off, the charge charged at the aforementioned discharge point is transferred from the X electrode to transistor QX.
The polarity is in the forward direction with respect to the PN junction between the emitter and base of transistor QX3, and as a result, the base current flows through the resistor, so a current that is times the current amplification factor (β) of transistor QX3 flows to the collector. This transistor QX4 and transistor QX7
It will be discharged through. Therefore, as in the period SUS of V _X1 and V _X2 in Fig. 3, the X electrode
A sustaining voltage pulse of Vs will be applied.

During the write period W, the transistor QX5 is turned on instead of the transistor QX4, and the voltage V _SH is applied to the X electrode through the same path as described above. When the output of the decoder becomes "1", transistor QX1 turns on and diode DX
Since the output line of the decoder driver via Q3 becomes "0", the transistor QX2 is turned on and the transistor QX3 is turned off. Therefore, the voltage V _Xa is applied to the X electrode connected to the output terminal Xi via the transistor QX2 and the diode DX2,
It is superimposed on the voltage of _VSH . Note that the voltage V _Xa is not applied to the non-selected X electrodes.

Also, while only the selected Y electrode is grounded, the non-selected electrodes are
The voltage V _Ya is applied at the same timing as the voltage V _Xa is applied. Due _{to the} condition _{of V}
Writing is performed by applying the voltage _Xa . Further, at the falling edge of the pulse at that time, the charges charged on the electrodes are discharged along the same path as at the falling edge of the sustaining voltage pulse.

Also, during the erasing period E, the transistor QX6
is turned on, and the voltage V _Xa is further applied to the X electrode connected to the output terminal Xi by the output of the decoder in the same manner as described above. In this case, in order to narrow the pulse width, after the transistors QX2 and QX6 are turned on, the transistors QX7 and QX3 are turned on after a short period of time, forming a trailing edge of the pulse. Also, on the Y electrode side, the selected Y electrode is grounded, and the voltage V _Ya is applied to the unselected Y electrode, as in the case of writing.

Therefore, an erasing pulse with a voltage of V _SM +V _Xa is applied only to the selected discharge point to perform the erasing operation. Note that V _SM can be omitted if the erase operation is reliably performed with an erase pulse of voltage V _Xa . Furthermore, if a write operation is possible even when _Vs and _VSH are set to the same voltage, it is also possible to adopt a configuration in which _Vs also serves as the voltage of _VSH .

As explained above, the present invention provides a first PNP for electrodes of a gas discharge panel having X and Y electrodes.
Transistor QX3 and second PNP transistor
It is equipped with a driver consisting of QX2 and diode DX2, and has a common sustain voltage circuit SUSX,
A sustain voltage pulse from SUSY can be applied to each electrode, and voltages V _xa , V _ya can be applied in a superimposed manner through the second PNP transistor to form a write or erase pulse. I can do it.
In this case, the decoder driver for driving the driver corresponding to the selected electrode has the advantage of being able to be driven by the high voltage open collector transistor QX1. Furthermore, since the number of constituent elements can be reduced, there is an advantage that it can be integrated into an integrated circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a peripheral circuit of a gas discharge panel, FIG. 2 is a circuit diagram of a main part of an embodiment of the present invention, and FIG. 3 is a waveform diagram for explaining operation. DRVXi is a driver compatible with electrodes, QX1 is a decoder driver transistor, QX2, QX3 are PNP transistors for the driver, Xi is an output terminal, DX
1. DX2 is a diode, and DX3 is a Zener diode.

Claims (1)

[Claims] 1. In a gas discharge panel having X and Y electrodes, an emitter is connected to each electrode of the gas discharge panel, the collector is connected to a common maintenance voltage circuit, and a diode is connected between the base and the emitter. A first PNP which applies a sustaining voltage pulse from the common sustaining voltage circuit from the collector through the base and the diode when charging the panel side with a sustaining voltage pulse, and from the emitter through the collector when discharging. Connect the collector to the base of the transistor and the first PNP transistor, connect the emitter to the power supply that outputs the voltage to be superimposed, and connect the output line of the decoder driver to the base to correspond to the selected discharge point. a voltage applied to the electrode via the first PNP transistor and a voltage of the power supply output from the collector via the diode to form a write pulse or an erase pulse; 2 of
A drive circuit for a gas discharge panel, characterized in that it is equipped with a PNP transistor.