JPS61135163A - Charge coupled device - Google Patents
Charge coupled deviceInfo
- Publication number
- JPS61135163A JPS61135163A JP59257933A JP25793384A JPS61135163A JP S61135163 A JPS61135163 A JP S61135163A JP 59257933 A JP59257933 A JP 59257933A JP 25793384 A JP25793384 A JP 25793384A JP S61135163 A JPS61135163 A JP S61135163A
- Authority
- JP
- Japan
- Prior art keywords
- charge
- transfer
- channel
- charges
- coupled device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005421 electrostatic potential Methods 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000004065 semiconductor Substances 0.000 claims abstract description 5
- 238000006243 chemical reaction Methods 0.000 claims description 8
- 239000012535 impurity Substances 0.000 abstract description 15
- 230000007547 defect Effects 0.000 abstract description 9
- 230000006866 deterioration Effects 0.000 abstract description 6
- 230000002093 peripheral effect Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 6
- 238000003384 imaging method Methods 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/762—Charge transfer devices
- H01L29/765—Charge-coupled devices
- H01L29/768—Charge-coupled devices with field effect produced by an insulated gate
- H01L29/76833—Buried channel CCD
- H01L29/76841—Two-Phase CCD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
- H01L27/14831—Area CCD imagers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/762—Charge transfer devices
- H01L29/765—Charge-coupled devices
- H01L29/768—Charge-coupled devices with field effect produced by an insulated gate
- H01L29/76833—Buried channel CCD
- H01L29/76858—Four-Phase CCD
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Electromagnetism (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
- Facsimile Scanning Arrangements (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は電荷結合装置に関し、特に固体イメージセンナ
の信号読出し手段に適するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a charge-coupled device, and is particularly suitable as a signal readout means for a solid-state image sensor.
従来、電荷結合装置としては、第５図及び第６図に示す
ものが知られている。ここで、第６図は第５図のＸ−Ｘ
線に沿う断面図である。Conventionally, as charge coupled devices, those shown in FIGS. 5 and 6 are known. Here, Figure 6 is X-X in Figure 5.
It is a sectional view along a line.
図中の１は、ｐＷの半導体基板である。この基板１０表
面には、転送チャネルとなるｎ型不純物層２が設げられ
ている。同基板１０表面には、不純物層２の長手方向の
両側に沿ってｐ＋厘のチャネルストツノ臂層３，３が設
けられている。前記基板１上には、絶縁膜４を介して複
数の電荷転送電極５が不純物層２の長手方向と直交する
方向に設けられている。1 in the figure is a pW semiconductor substrate. On the surface of this substrate 10, an n-type impurity layer 2 serving as a transfer channel is provided. On the surface of the substrate 10, p+channel channel strut layers 3, 3 are provided along both sides of the impurity layer 2 in the longitudinal direction. A plurality of charge transfer electrodes 5 are provided on the substrate 1 with an insulating film 4 interposed therebetween in a direction perpendicular to the longitudinal direction of the impurity layer 2 .
こうした構造の電荷結合装置において、所定の電圧を前
記電極５に加えた状態の不純物層２内のポテンシャル分
布は、第７図に示す通シとなる。なお、第７図において
、６は不純物層２の可動キャリアが全て排除された状態
のポテンシャルを、７はチャネルスト７２層３のポテン
シャル（基板電位に相当する）を、８は不純物層２に蓄
積され紙面の垂直方向に転送される電荷を、９は不純物
層２内に存在する欠陥等の不良モードを夫々示す。In a charge-coupled device having such a structure, the potential distribution within the impurity layer 2 when a predetermined voltage is applied to the electrode 5 is as shown in FIG. In addition, in FIG. 7, 6 is the potential in the state where all the mobile carriers in the impurity layer 2 are removed, 7 is the potential of the channel strike 72 layer 3 (corresponding to the substrate potential), and 8 is the potential accumulated in the impurity layer 2. 9 indicates the charge transferred in the direction perpendicular to the plane of the paper, and 9 indicates a failure mode such as a defect existing in the impurity layer 2.
しかしながら、従来の電荷結合装置によれば、次に示す
欠陥を有する。However, conventional charge-coupled devices have the following drawbacks.
■ 電荷がｎ型不純物層２の転送方向（矢印人）に直交
するチャネル幅（不純物層幅）全体に亘って蓄積される
ため、少量の電荷を転送する場合、チャネル電位の変化
が小さいので電荷転送の物理的メカニズムである自己誘
起ドリフト電界が小さくなシ、熱拡散による遅い移動が
支配的となって転送速度が低下する。■ Charge is accumulated over the entire channel width (impurity layer width) perpendicular to the transfer direction (arrow) of n-type impurity layer 2, so when transferring a small amount of charge, the change in channel potential is small, so the charge is When the self-induced drift electric field, which is the physical mechanism of transfer, is small, slow movement due to thermal diffusion becomes dominant and the transfer rate decreases.
■ 例えば、一定の電荷量をトラップする欠陥が不純物
層２内に極在化する場合、電荷は必ず欠陥にトラップさ
れ、転送損失をもたらす。(2) For example, if a defect that traps a certain amount of charge is localized in the impurity layer 2, the charge will definitely be trapped in the defect, resulting in transfer loss.
つまシ、トラップされる電荷量ｔ−Ｑｔとすれば、転送
電荷量Ｑ３に対して非転送効率εは！＝Ｑｔ／Ｑｓとな
シ、Ｑｔに比例して大きくなる。従って、信号電荷を転
送すると著しい劣化をもたらす。If the amount of trapped charge is t-Qt, then the non-transfer efficiency ε is for the amount of transferred charge Q3! =Qt/Qs, which increases in proportion to Qt. Therefore, transferring signal charges causes significant deterioration.
本発明は上記事情に鑑みてなされたもので、少量の電荷
を転送する時の転送速度の低下及び欠陥による特性劣化
を改善し得る電荷結合装置を提供することを目的とする
。The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a charge coupled device that can improve the reduction in transfer speed when transferring a small amount of charge and the deterioration of characteristics due to defects.
本発明は、半導体基板と逆導電型の転送チャネルの表面
あるいはその近傍の静電ポテンシャルを電荷転送方向と
直交する方向に沿って選択的に異ならせることによって
、少量電荷転送時の転送速度の低下及び欠陥による特性
劣化を改善しようとしたものである。The present invention reduces the transfer rate during small charge transfer by selectively varying the electrostatic potential at or near the surface of a transfer channel of conductivity type opposite to that of the semiconductor substrate along a direction perpendicular to the charge transfer direction. This is an attempt to improve the deterioration of characteristics due to defects.
以下、本発明の実施例を図を参照して説明する。 Embodiments of the present invention will be described below with reference to the drawings.
実施例１
第１図及び第２図を用いて説明する。ここで、第２図は
第１図のＸ−Ｘ線に沿う断面図である。Example 1 This will be explained using FIGS. 1 and 2. Here, FIG. 2 is a sectional view taken along the line XX in FIG. 1.
図中の２１は、ｐ型のシリコン基板である。この基板２
１の表面にはｎ型不純物層（転送チャネル）２２が形成
され、この転送チャネル２２には相対的に高濃度の（ｎ
＋型）不純物層（局在チャネル）２３が基板２１Ｖｃ突
出するように形成されている。前記転送チャネル２２の
長手方向に沿う両側には１．ｐ＋型のチャネルストツ・
９層（以下、ｐＷ層と称す）２４，２４が設けられてい
る。前記基板２１上には、絶縁膜２５を介して電荷転送
電極２６が転・送チャネル２２の長手方向と直交する方
向に設けられている。なお、第２図において、ｔｏは全
チャネルの幅を、ｔ□は局在チャネル２３０幅を夫々示
す。21 in the figure is a p-type silicon substrate. This board 2
An n-type impurity layer (transfer channel) 22 is formed on the surface of 1, and this transfer channel 22 has a relatively high concentration (n
A + type) impurity layer (localized channel) 23 is formed to protrude from the substrate 21Vc. 1 on both sides along the longitudinal direction of the transfer channel 22. p+ type channel stock
Nine layers (hereinafter referred to as pW layers) 24, 24 are provided. A charge transfer electrode 26 is provided on the substrate 21 with an insulating film 25 interposed therebetween in a direction perpendicular to the longitudinal direction of the transfer channel 22 . In addition, in FIG. 2, to indicates the width of the entire channel, and t□ indicates the width of the localized channel 230, respectively.
こうした構造の電荷結合装置において、所定の電極２６
に周辺のクロックパルス（例えば、４相クロツクパルス
）を印加することによシ、電荷を紙面に垂直な方向へ転
送する。即ち、少量の電荷の場合は、第３図のポテンシ
ャル分布図に示す如く少量電荷２７を局在チャネル２３
に局在化させ、局在チャネル２３だけを転送路として電
荷を転送する。なお、第３図中の２８゜２９は夫々転送
キャリア２２の多数キャリアである電子を所定の電圧を
電極、２６に印加した状態で排除した時の静電ポテンシ
ャルで、２８は局在チャネル２３に形成される静電ポテ
ンシャルをかつ２９は転送チャネル２２に形成される静
電ポテンシャルを示す。ΔＶは、電位の変化を示す。一
方、多量電荷３０の場合は、転送チャネル２２内全体に
広がって転送される（第４図図示）。In a charge coupled device having such a structure, a predetermined electrode 26
By applying peripheral clock pulses (eg, 4-phase clock pulses) to , charges are transferred in a direction perpendicular to the plane of the paper. That is, in the case of a small amount of charge, the small amount of charge 27 is transferred to the localized channel 23 as shown in the potential distribution diagram of FIG.
The charge is localized and the charge is transferred using only the localized channel 23 as a transfer path. In addition, 28° and 29 in FIG. 3 are the electrostatic potentials when electrons, which are the majority carriers of the transfer carriers 22, are removed with a predetermined voltage applied to the electrodes 26, respectively, and 28 is the electrostatic potential in the localized channel 23. 29 represents the electrostatic potential formed in the transfer channel 22. ΔV indicates a change in potential. On the other hand, in the case of a large amount of charge 30, it spreads throughout the transfer channel 22 and is transferred (as shown in FIG. 4).
しかして、実施例１によれば、転送チャネル２２に局在
チャネル２３を設けた構造となっているため、少量電荷
を転送する場合、少量電荷を局在チャネル２３に局在化
させ、この状態で電荷転送電極２５に周辺のクロックｉ
４ルスを印加することによシ局在チャネル２３内だけを
転送路として電荷を紙面に垂直な方向へ転送できる。従
って、少量電荷であっても第３図における電位の変化Δ
Ｖが大きいため、自己誘起ドリフトによる速い転送が可
能となる。また、第３図において欠陥（Ｘ印）が図の位
置に存在した場合、少量電荷は欠陥に触れることがない
ためその影響を受けない。一方、多量電荷の場合は、第
４図く示す如く転送チャネル２２内全体に広がって転送
されるが、電荷量Ｑｓが大きいため非転送効率Ｑオ／Ｑ
ｓは小さい。According to the first embodiment, since the transfer channel 22 has a structure in which the localized channel 23 is provided, when transferring a small amount of charge, the small amount of charge is localized in the localized channel 23, and this state , the peripheral clock i is applied to the charge transfer electrode 25.
By applying four pulses, charges can be transferred in a direction perpendicular to the plane of the paper using only the inside of the localized channel 23 as a transfer path. Therefore, even if there is a small amount of charge, the change in potential Δ in FIG.
Since V is large, fast transfer due to self-induced drift is possible. Further, in FIG. 3, if a defect (X mark) exists at the position shown in the figure, the small amount of charge does not touch the defect and is therefore not affected by it. On the other hand, in the case of a large amount of charge, the charge is spread throughout the transfer channel 22 and transferred as shown in FIG. 4, but since the charge amount Qs is large, the transfer efficiency is
s is small.
実施例２
本発明を固体撮像装置の信号電荷読出しレジスタとして
使用した場合について、第８図〜第１０図を参照して説
明する。なお、第９図は第８図のＸ−Ｘ線に沿５断面図
を、第１０図は第９図の静電ポテンシャル分布図を示す
。Embodiment 2 A case where the present invention is used as a signal charge readout register of a solid-state imaging device will be described with reference to FIGS. 8 to 10. Note that FIG. 9 shows a cross-sectional view taken along the line X--X in FIG. 8, and FIG. 10 shows an electrostatic potential distribution diagram in FIG. 9.
図中の３１は、信号電荷を紙面に対して水平方向に転送
するための水平転送ＣＣＤのｎ型の転送チャネルである
。この転送チャネル３１内には、相対的に静電ポテンシ
ャルが高い（深い）ｎ”ｌｌの局在チャネル３２が設け
られている。これら転送チャネル３１、局在チャネル３
２上には、絶縁膜２４を介して２相駆動形ＣＯＤの電荷
転送電極の一対をなす蓄積電極３３と障壁電極３４が夫
々設けられている。こうした電極対には、位相が１８０
°異なる２相転送／４’ルスφ１ 。31 in the figure is an n-type transfer channel of a horizontal transfer CCD for transferring signal charges in the horizontal direction with respect to the paper surface. In this transfer channel 31, a localized channel 32 of n''ll with a relatively high (deep) electrostatic potential is provided.These transfer channels 31, localized channels 3
A storage electrode 33 and a barrier electrode 34, which form a pair of charge transfer electrodes of a two-phase drive type COD, are provided on the storage electrode 33 and the barrier electrode 34, respectively, with an insulating film 24 interposed therebetween. These electrode pairs have a phase of 180
°Different two-phase transfer/4'rus φ1.
φｚｆｒ、供給するための配線３．５，３６が接続され
ている。前記電極対群の近くには、転送された電荷を電
圧に変換して出力する出力回路３７が設げられている。Wirings 3.5 and 36 for supplying φzfr are connected. An output circuit 37 is provided near the electrode pair group to convert the transferred charges into voltage and output it.
また図中の３８は光電変換素子である。この光電変換素
子３８の近く和は、該光電変換素子３８で得られた電荷
を受は取って水平読出しＣＯＤレジスタに転送するため
の垂直転送ＣＯＤ （電荷蓄積部）３９が設げられてい
る。この垂直転送ＣＣＤ ３９には、該ＣＣＤ ３９へ
異なる転送パルスを供給するための配線４０゜４１が接
続されている。前記ＣＯＤ Ｊ ９の近くには、該ＣＯ
Ｄ ３９から水平転送ＣＯＤの転送チャネル３１、局在
チャネル３２への電荷転送を制御する制御電極４２が前
記蓄積電極３３の一部上に延在して設けられている。な
お、第９図において、ｔｏは全チャネルの幅を、ｔ□は
局在チャネル３２０幅を、ｔ２は制御電極４２と蓄積電
極３３の距離を夫々示す。また、第１０図において、４
３は局在チャネル３２に対応した深い静電ポテンシャル
を、４４は転送チャネル３１に対応した浅い静電ポテン
シャルを、４５は少量電荷を、４６は多量電荷を夫々示
す。この場合、電荷は制御電極４２の下を通って紙面左
から流入する。従って、距離ｔ□はできるだけ短かくし
、小電荷が触れるチャネル領域をできるだけ小さくする
ことが好ましい。Further, 38 in the figure is a photoelectric conversion element. A vertical transfer COD (charge accumulation section) 39 is provided near the photoelectric conversion element 38 for receiving and transferring the charge obtained by the photoelectric conversion element 38 to a horizontal readout COD register. This vertical transfer CCD 39 is connected to wires 40.degree. 41 for supplying different transfer pulses to the CCD 39. Near the COD J 9, the COD
A control electrode 42 for controlling charge transfer from D 39 to the horizontal transfer COD transfer channel 31 and localized channel 32 is provided extending over a portion of the storage electrode 33 . In FIG. 9, to indicates the width of the entire channel, t□ indicates the width of the localized channel 320, and t2 indicates the distance between the control electrode 42 and the storage electrode 33. Also, in Figure 10, 4
3 indicates a deep electrostatic potential corresponding to the localized channel 32, 44 indicates a shallow electrostatic potential corresponding to the transfer channel 31, 45 indicates a small amount of charge, and 46 indicates a large amount of charge. In this case, the charge passes under the control electrode 42 and flows from the left in the drawing. Therefore, it is preferable to make the distance t□ as short as possible and to minimize the channel region that small charges come into contact with.
こうした構造の固体撮像装置において、制御電極４２に
所定電圧を印加゛して垂直転送ＣＣＤ３９から転送チャ
ネル３１へ電荷を転送する際、電荷量が小さい場合には
転送された電荷は転送チャネル３１にわたって広がるこ
となく静電ポテンシャルが高い局在チャネル３２だけに
蓄積され、局在チャネル３２の中を通って出力回路３１
に順次転送される。ここで、小電荷が局在チャネル３２
の中に局在し転送される様子を第１１図に示す。なお、
同図において、５１１〜５１４は電極対（蓄積電極３３
、障壁電極３４）の異なる位相のパルスが印加される相
隣り合う２対電極下のポテンシャルを、５２１〜５２４
は深い静電ポテンシャル３８を含む相対的に深いポテン
シャルを夫々示す。In a solid-state imaging device having such a structure, when a predetermined voltage is applied to the control electrode 42 to transfer charges from the vertical transfer CCD 39 to the transfer channel 31, if the amount of charge is small, the transferred charges spread across the transfer channel 31. The electrostatic potential is accumulated only in the localized channel 32 with high electrostatic potential, and passes through the localized channel 32 to the output circuit 31.
are sequentially transferred to Here, a small charge is localized in the channel 32
FIG. 11 shows how the information is localized and transferred within the . In addition,
In the figure, 511 to 514 are electrode pairs (storage electrodes 33
, the potential under two adjacent pairs of electrodes to which pulses of different phases are applied to the barrier electrode 34) is expressed as 521 to 524.
represent relatively deep potentials, including deep electrostatic potential 38, respectively.
しかして、実施例２によれば、局在チャネル３２の存在
によシ実流側１と同様な効果を得ることができる。Therefore, according to the second embodiment, the same effect as the actual flow side 1 can be obtained due to the presence of the localized channel 32.
なお、実施例１及び実施例２において、本発明の効果を
顕著に得るためには全チャネルの幅ｔ０に対し局在チャ
ネルの幅ｔ１を１７２以下にすることが好ましい。In addition, in Examples 1 and 2, in order to significantly obtain the effects of the present invention, it is preferable that the width t1 of the localized channel is 172 or less with respect to the width t0 of all channels.
また、実施例１及び実施例２では、局在チャネルを１つ
形成した場合について述べたが、これに限らず、複数個
形成しても同様な効果を得ることができるとともに、各
々の局在チャネルの電位を夫々異ならしめてもその効果
は失われない。Further, in Examples 1 and 2, the case where one localized channel was formed was described, but this is not limited to this, and the same effect can be obtained even if multiple localized channels are formed, and each localized channel is Even if the potentials of the channels are made different, the effect is not lost.
更に、実施例２では、垂直転送ＣＣＤ （電荷蓄積部）
及び光電変換素子を設けた場合について述べたが、これ
らの代シに光電変換機能を備えた電荷蓄積素子を用いて
もよい。Furthermore, in the second embodiment, a vertical transfer CCD (charge storage section)
Although the case where a photoelectric conversion element and a photoelectric conversion element are provided has been described, a charge storage element having a photoelectric conversion function may be used in place of these.
実施例３ 第１２図を用いて説明する。Example 3 This will be explained using FIG. 12.
本実施例の固体撮像装置は、相対的化法いポテンシャル
を形成するための手段として、基板２１上の絶縁膜６１
ｔ−蓄積電極６２を転送電極６３のオーバラッグ付近で
相対的に厚くしたことを特徴とする。The solid-state imaging device of this embodiment uses an insulating film 61 on a substrate 21 as a means for forming a relativized potential.
A feature is that the t-storage electrode 62 is made relatively thick near the overlap of the transfer electrode 63.
しかして、実施例３によれば、部分的に厚い絶縁膜６１
の存在によシ実流側１と同様な効果を得る他、転送チャ
ネル６４は全体にわたって一様な不純物濃度と接合の深
さを有することができる。According to the third embodiment, the partially thick insulating film 61
In addition to obtaining an effect similar to that of the actual flow side 1 due to the presence of the transfer channel 64, the transfer channel 64 can have a uniform impurity concentration and junction depth throughout.
以上詳述した如く本発明によれば、少量電荷転送時の転
送速度の低下及び欠陥による特性劣化を改善し得る電荷
結合装置を提供できる。As described in detail above, according to the present invention, it is possible to provide a charge-coupled device that can improve the reduction in transfer speed when transferring a small amount of charge and the deterioration of characteristics due to defects.
第１図は本発明の実施例１に係る電荷結合装置の平面図
、第２図は第１図のＸ−Ｘ線に沿う断面図、第３図は第
２図の小電荷蓄積時の静電ポテンシャル分布図、第４図
は第２図の大電荷蓄積時の静電ポテンシャル分布図、第
５図は従来の電荷結合装置の平面図、第６図は第５図の
Ｘ−Ｘ線に沿う断面図、第７図は第６図の静電ポテンシ
ャル分布図、第８図は本発明の実施例２に係る固体撮像
装置の平面図、第９図は第８図のＸ−Ｘ線に沿う断面図
、第１０図は第９図の静電ポテンシャル分布図、第１１
図は第８図の小電荷の流れを説明するための図、第１２
図は本発明の実施例３に係る固体撮像装置の断面図であ
る。
２１・・・ｐ型のシリコン基板、２２，３１゜６４・・
・転送チャネル、２３，３２・・・局在チャネル、２４
・・・チャネルストツ／４層、２５．６１・・・絶縁膜
、２６・・・電荷転送電極、３０・・・電位の変化、３
３，６２・・・蓄積電極、３４・・・障壁電極、３５．
３６．４０．４１・・・配線、３７・・・出力回路、３
８・・・光電変換素子、３９・・・垂直転送ＣＣＤ、４
２・・・制御電極。FIG. 1 is a plan view of a charge-coupled device according to Embodiment 1 of the present invention, FIG. 2 is a sectional view taken along the line X-X in FIG. 1, and FIG. Figure 4 is a diagram of the electrostatic potential distribution during large charge accumulation in Figure 2, Figure 5 is a plan view of the conventional charge coupled device, Figure 6 is the diagram of the X-X line in Figure 5. 7 is an electrostatic potential distribution diagram of FIG. 6, FIG. 8 is a plan view of the solid-state imaging device according to the second embodiment of the present invention, and FIG. 9 is a diagram taken along the line X-X of FIG. Figure 10 is the electrostatic potential distribution diagram of Figure 9, Figure 11 is a cross-sectional view along
The figure is a diagram for explaining the flow of small charges in Figure 8, and Figure 12.
The figure is a sectional view of a solid-state imaging device according to Example 3 of the present invention. 21...p-type silicon substrate, 22,31°64...
・Transfer channel, 23, 32...Local channel, 24
... Channel stock / 4 layers, 25.61 ... Insulating film, 26 ... Charge transfer electrode, 30 ... Potential change, 3
3, 62... Storage electrode, 34... Barrier electrode, 35.
36.40.41...Wiring, 37...Output circuit, 3
8... Photoelectric conversion element, 39... Vertical transfer CCD, 4
2...Control electrode.
Claims (6)
られた第２導電型の転送チャネルと、この転送チャネル
上に絶縁膜を介して設けられた電荷転送電極と、前記転
送チャネルの表面あるいはその近傍の静電ポテンシャル
を電荷転送方向と直交する方向に沿って選択的に異なら
せる手段とを具備することを特徴とする電荷結合装置。(1) A semiconductor substrate of a first conductivity type, a transfer channel of a second conductivity type provided on the surface of the substrate, a charge transfer electrode provided on the transfer channel via an insulating film, and a transfer channel of the transfer channel. A charge-coupled device comprising: means for selectively varying the electrostatic potential at or near the surface along a direction perpendicular to the charge transfer direction.
ルギーが電荷に対して相対的に低く、この領域の幅が電
荷転送方向に直交する電荷転送チャネル幅の１／２以下
であることを特徴とする特許請求の範囲第１項記載の電
荷結合装置。(2) The energy of the electrostatic potential that is selectively made different is relatively low with respect to the charge, and the width of this region is 1/2 or less of the width of the charge transfer channel orthogonal to the charge transfer direction. A charge-coupled device according to claim 1.
転送電極と隣接して設け、かつ電荷を電荷蓄積部から電
荷転送電極へ並列して転送した後、この転送方向と直交
する方向に転送する機能を有することを特徴とする特許
請求の範囲第１項記載の電荷結合装置。(3) A charge storage section is provided adjacent to a charge transfer electrode on the surface of a semiconductor substrate of the first conductivity type, and after charges are transferred in parallel from the charge storage section to the charge transfer electrode, a direction perpendicular to this transfer direction is provided. 2. The charge-coupled device according to claim 1, wherein the charge-coupled device has a function of transferring data.
ルギーが電荷に対して相対的に低く、この領域が電荷蓄
積部に近接した部分に電荷転送方向に沿って延在してい
ることを特徴とする特許請求の範囲第３項記載の電荷結
合装置。(4) The energy of the selectively different electrostatic potential is relatively low with respect to the charge, and this region extends along the charge transfer direction in a portion close to the charge storage section. A charge-coupled device according to claim 3.
蓄積素子に隣接して光電変換子を設けることを特徴とす
る特許請求の範囲第３項記載の電荷結合装置。(5) The charge coupled device according to claim 3, characterized in that a charge storage element is used as the charge storage section, and a photoelectric converter is provided adjacent to the charge storage element.
素子を用いることを特徴とする特許請求の範囲第３項記
載の電荷結合装置。(6) The charge coupled device according to claim 3, wherein a charge storage element having a photoelectric conversion function is used as the charge storage section.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59257933A JPS61135163A (en) | 1984-12-06 | 1984-12-06 | Charge coupled device |
| DE8585115404T DE3581793D1 (en) | 1984-12-06 | 1985-12-04 | LOAD SHIFTING ARRANGEMENT. |
| EP85115404A EP0185990B1 (en) | 1984-12-06 | 1985-12-04 | Charge coupled device |
| US07/231,645 US4901125A (en) | 1984-12-06 | 1988-08-10 | Charge coupled device capable of efficiently transferring charge |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59257933A JPS61135163A (en) | 1984-12-06 | 1984-12-06 | Charge coupled device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61135163A true JPS61135163A (en) | 1986-06-23 |
Family
ID=17313211
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59257933A Pending JPS61135163A (en) | 1984-12-06 | 1984-12-06 | Charge coupled device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61135163A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006245069A (en) * | 2005-02-28 | 2006-09-14 | Sharp Corp | Solid state imaging device and electronic information apparatus |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58161364A (en) * | 1982-03-19 | 1983-09-24 | Hitachi Ltd | Charge transfer element |
-
1984
- 1984-12-06 JP JP59257933A patent/JPS61135163A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58161364A (en) * | 1982-03-19 | 1983-09-24 | Hitachi Ltd | Charge transfer element |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006245069A (en) * | 2005-02-28 | 2006-09-14 | Sharp Corp | Solid state imaging device and electronic information apparatus |
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