JPS61134999A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To completely and easily correspond to a semiconductor memory device especially, by providing plural nonvolatile memory cells, an additional row decoder circuit for selecting the plural memory cells, and decoder actuation selecting circuit in addition to the memory device. CONSTITUTION:The semiconductor storage device of this invention is equipped with a memory cell array 3 composed of memory cells, to which access is made during normal operation periods, nonvolatile memory cell array 11 composed of nonvolatile memory cells, to which no access is made during normal operations periods, and a control circuit 12 which sets the selection circuit 2 corresponding to the memory cell array 3 to a nonoperating condition in response to a control signal from the outside and the selection circuit 10 corresponding to the nonvolatile memory cell array 11 to an operating condition in response to an address signal. A decoder actuation selecting circuit 12 can record test results in the nonvolatile memory cells by actuating an additional row decoder circuit when the test results are recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated device, and particularly to a semiconductor memory device in which a nonvolatile memory section is provided in addition to normal memory cells.

[Conventional technology]

Semiconductor integrated devices such as semiconductor storage devices and microprocessors are required to have higher integration density, higher speed, and higher reliability, and various tests are conducted at the test stage after manufacturing. The results of various tests are compiled, stored, and managed as a test report.

In some cases, such test results can be determined by pasting a test record level on the surface of the semiconductor integrated device, or by tying the test record sheet to the pin of the corresponding semiconductor integrated device with wire. many. That is, the tester manually writes the test results on the label or the like according to the test.

[Problem that the invention seeks to solve]

Since test results are basically obtained for each semiconductor integrated device, it is necessary to always have a clear one-to-one correspondence between semiconductor integrated devices and test data. In that respect,
As mentioned above, it is practical and preferable to affix a test record label to an actual semiconductor integrated device, but the number of test items increases while the external dimensions of a semiconductor integrated device are limited. There is a problem in that the test results cannot be recorded sufficiently. Furthermore, since the recording label must be removed after recording is completed and is temporarily attached, there is a problem in that it is easily peeled off and the test results are lost.

A similar problem exists when a test record sheet is tied to a bottle of a semiconductor integrated device. That is, first of all, it is easy to detach from the pins, and if the paper is too large compared to the external dimensions of the semiconductor integrated device, it will be difficult to handle. Put it away.

If the test results are managed using only detailed test results, there will be problems in associating them with actual semiconductor integrated devices.

In addition, the above-mentioned test result management method essentially allows testers to make mistakes and move on to the next test without conducting the test they should have done, or write the test results as normal even though there is a problem with the characteristics. There are always possibilities within.

Furthermore, the above-described test result management method is only effective at the time of factory testing before a semiconductor integrated device is completed and shipped as a single unit. In other words, if a failure occurs when these semiconductor integrated devices are applied to an actual product and tested again while being incorporated into that product, or if a failure occurs during operation in the actual field. In such cases, it is often necessary to investigate the cause, take future improvement measures, or revise usage conditions by referring to test results from past factory tests, etc.; Even if it is preserved, it is impossible to identify it with a failed semiconductor integrated device.

This is because a large number of semiconductor integrated devices having a certain standard of quality are shipped to various users, and it is difficult to associate semiconductor integrated devices with each other after shipping.

In addition, conventional methods are a factor in electrodynamic degradation in test automation.

In view of such circumstances, it is desired that it be possible to completely and easily associate with an actual semiconductor integrated device, especially a semiconductor memory device, and that accurate and sufficient test results can be stored. Additionally, there is a need for an efficient test recording means that further promotes efficiency improvements associated with test automation. Furthermore, there is a need to prevent omissions in exams and errors in recording pass/fail results due to carelessness.

[Means to solve the problem]

In order to solve the above-mentioned problems, in the present invention, as illustrated in FIG. The nonvolatile memory cell array 11 and the selection circuit 2 for the memory cell array are rendered inactive in response to an external control signal, and the selection circuit 10 for the nonvolatile memory cell array is rendered operational in response to an address signal. There is provided a semiconductor memory device characterized by comprising a control circuit 12 that performs the following steps.

[For production]

The present invention further includes a conventional semiconductor memory device having a plurality of memory cells, a plurality of nonvolatile memory cells, an additional row decoder circuit for selecting the plurality of nonvolatile memory cells, and a decoder operation selection circuit. are doing.

The decoder activation selection circuit activates the additional row decoder circuit when recording test results so that the test results can be recorded in the non-volatile memory cells. An additional row decoder circuit is also activated when reading test results. In normal cases other than these, the conventional row decoder operates and the original plurality of memory cells are accessed.

〔Example〕

Examples will be described below with reference to the accompanying drawings.

FIG. 1 shows a configuration diagram when the present invention is applied to a semiconductor memory device as an embodiment.

The semiconductor memory device shown in FIG. 1 includes a memory cell array 3 in which a plurality of memory cells are arranged in a matrix.
, an address buffer 1 for selecting a predetermined memory cell of the memory cell array 3, a row decoder 2, a column decoder 5, a column gate circuit 6, and a sense amplifier circuit 7.
, an input/output cover sofa circuit 8, and a control circuit 4 are configured as shown in the figure. It is similar to

In addition to the above, the semiconductor memory device according to the present invention includes a nonvolatile memory cell array (or service memory cell array) 11 consisting of a plurality of nonvolatile memory cells, and an additional memory cell array for selecting a word line of the nonvolatile memory cell array 11. It includes a service memory row decoder 10 which is a row decoder, a row decoder operation selection circuit 12 for selecting whether to activate the row decoder 2 or the service memory row decoder 10, and an inverter 13.

In the embodiment shown in FIG. 1, for selecting a desired memory cell in the nonvolatile memory cell array 11, from the viewpoint of simplifying the circuit, the column decoder 5 and the column gate circuit 6 are used as bit lines for selecting a normal memory cell array. They are shared so that the acid bit line can be selected at the same time as the normal memory cell array 3. On the other hand, a service memory row decoder 10 is provided separately from the row decoder 2 so that the word lines are not selected at the same time. Either one can be activated by the service memory selection signal SMS.

The portions of the semiconductor memory device shown in FIG. 1 that are related to the present invention will be described in more detail with reference to FIG.

Address buffer 1 has a 16-bit address signal A0.
~A15 is input, A0~A7 for column decoder,
A8 to AI5 are used for the row decoder, resulting in 256 word lines WL each.

~WL2SS and 256 bit lines BLo~13L
zss is selected. Therefore, normal memory cell array 3
The bits 64 are connected in a matrix as shown. Therefore, the AND gate DG o = DG
A row decoder 2 configured with zss receives a signal from an address buffer 1 and outputs words vAWL, ~ as shown in the figure.
Define WLZSS. Similarly, a column gate circuit 6 consisting of gates CG and CGzss is connected as shown, and selects one of the bit lines BL and BLzss in response to a signal selected by the column decoder 5. A sense amplifier circuit 7 is provided at the output stage of the column gate circuit 6, so that signals can be read out.

A nonvolatile memory cell array 11 consisting of a plurality of nonvolatile memory cells connected to bit lines BL, ~BLzss, and word lines WLo~WLz in a matrix like the normal memory cell 3 is arranged in parallel with the memory cell array 3. has been done. Word line W in nonvolatile memory cell array 11
4 AND gates 5GD to select Lo~WL3
Service memory row decoder 1 consisting of O~5GD3
0 are connected as shown. That is, in this example, two bits A8 and A of the address signal are used to select the lower four word lines WL0 to WL. Therefore, the capacity of a nonvolatile memory cell is 4
X256=IK bit.

Note that an inverted service memory selection signal SMS is applied to each AND gate in the row decoder 2, and a service memory selection signal SMS is applied to each AND gate in the service memory row decoder 10.

The low decoder operation selection circuit 12 is a P channel MO3)
Transistors TRI, TRz, TR4 and N-channel M
OS transistors TR, , TR, are connected as shown. The transistors TR and TRs constitute an inverter circuit. Note that the row decoder operation selection circuit 12 selects A8 to A I related to the row decoder.
Out of 5, A is used for the service memory row decoder 10.
8 and A, in this example Alo
Row decoder 2 or service memory row decoder 1
It is used as a signal to activate 0.

An inverter 13' is provided between the row decoder operation selection circuit 12 and the service maintenance row decoder 10, but it is reversed from that shown in FIG. This is because it is assumed that the SMS signal is output as the output of the row decoder operation selection circuit 12 in FIG. 1, but in the case shown in FIG. It's just the opposite.

The operation of the circuit shown in FIG. 2 will be described below.

First, the operation of the row decoder operation selection circuit 12 will be described.

When accessing the normal memory cell array 3, the Ago bit of the address input is a normal TTL level signal. Therefore, transistors TR, and TR, remain turned off, and the gate of transistor TR, remains at Vcc.
level, and the level of node N1 becomes "low (L)". Therefore, it is inverted by the inverter formed by transistors TR4 and TR5, and the SMS signal is output as a "high" (H) level.

On the other hand, when accessing the nonvolatile memory cell array 11, the level of the A1° bit of the address input is set higher than Vcc, for example, Vcc+α=12V. As a result, transistors TR and TRz are turned on,
Node N, which is the output of transistor TR1 with small capacitance
The level of 1 becomes "H". Therefore, the SMS signal is “L”
” becomes.

When the SMS signal = H, each AND gate DG, ~DGzss of the row decoder 2 is activated, and the address buffer 1
A word line WL is selected according to a signal from the word line WL. On the other hand, when the signal is equal to L, that is, the SMS signal is equal to H, each AND gate S in the service memory row decoder 10
DG o to S DG 3 are activated. Column gate circuit 6 is driven in the same manner as before.

That is, when performing a test or normal operation using the normal memory cell array 3, set A, 0 = TTL level, and when writing the test result after the test, set <A> as described above.
t. If the voltage level is set to =Vcc+α, writing to the nonvolatile memory cell array 11 becomes possible. Of course, reading from the nonvolatile memory cell array 11 is also possible in this state.

Note that the A1° bit of the address signal is set to a high level only when writing or reading from the nonvolatile memory cell array 11 during testing. It is sufficient that the A1° bit can be set to a high level only when the semiconductor memory device is used, and it is clear that there is no need for the device in which the semiconductor memory device is used to have such a function.

The normal memory cell array 3 is as described above. A
M.

It is not limited to 5-RAM and may be any arbitrary one.

As a nonvolatile memory cell, for example, semiconductor nonvolatile M
IS type mesememory cells include MNOS memory cells and MA
Although O3 (MAS) memory cells, floating gate storage type memory cells, etc. are possible, it is preferable to select one that has good process coordination with the normal memory cell side.

Furthermore, the nonvolatile memory cell according to the present invention only needs to be written once and does not need to be erasable. Of course, a rewritable memory may be used, but it is also possible to use a read-only memory (ROM) with a fuse-blown type, and to record the test results by blowing the corresponding fuse. From this point of view, any memory that is nonvolatile in a broad sense may be used.

The data to be written to the nonvolatile memory cell array 11 includes general information such as device serial number and manufacturing loft, as well as test type and characteristics such as voltage margin, temperature margin, and speed obtained at each test stage. There is data, final pass/fail judgment results, etc. That is, the device can be identified by the serial number, and the quality of the lot can be determined by storing the manufacturing lot. In addition, by memorizing the test type, if there is a test that is missed when it should be performed sequentially, the contents of the non-volatile memory can be read out in advance when conducting the next test and it can be automatically or visually checked by the examiner. can be confirmed. In addition, the characteristic data of each test stage is not only used for automatic judgment of pass/fail at the time of shipment, but also allows one's own condition to be stored as a so-called 4 medical record.

Of course, it is possible to add the results of the previous test results, such as when some problem occurs after shipping and the product is re-tested after it has been installed in the device, or when periodic inspections are performed.

Similarly, it is also possible to save retest results after long-term storage.

It is also possible to record information other than the information related to the above-mentioned test, such as the code name of the customer to whom the product should be delivered, the date of shipment, etc.

Although the above embodiments have been described in terms of semiconductor memory devices from the viewpoint of ease of storage and subsequent access, the present invention is not limited thereto.

For example, test results of a semiconductor memory and a microprocessor in a semiconductor integrated device that integrates a semiconductor memory and a microprocessor can be similarly applied. Since microprocessors are generally subjected to more various tests than memories, it is particularly useful to record the test results. Similarly, programmable logic array (
PLA) can be used to record used gates and unusable gates. The same applies to other integrated circuits.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to completely and easily associate with a semiconductor integrated device such as a semiconductor memory device, and to permanently store accurate and sufficient test results.

Further, according to the present invention, high efficiency of recording work can be achieved.

Further, according to the present invention, it is possible to prevent omissions in tests and erroneous judgments due to carelessness, mistakes, etc.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram when applied to a semiconductor memory device as an embodiment of the present invention, FIG. 2 is a diagram showing a more specific circuit example of the device in FIG. 1,
It is. (Explanation of symbols) 1... Address buffer, 2... Row decoder, 3
...Memory cell array, 4...Control circuit,
5... Column decoder, 6... Column gate circuit,
7...Sense amplifier circuit, 8...Input/output cover sofa circuit, 10...Low decoder for service memory, 11.
. . . Nonvolatile memory cell array, 12 . . . Row decoder operation selection circuit, 13 . . . Inverter.

Claims (1)

[Claims] 1. A memory cell array consisting of memory cells that are accessed during normal operation, a non-volatile memory cell array consisting of non-volatile memory cells that are not accessed during normal operation, and a 1. A semiconductor memory device comprising: a control circuit that renders a selection circuit for a cell array non-operational and that renders a selection circuit for the nonvolatile memory cell array operable in response to an address signal. 2. The control signal according to claim 1, wherein the control signal is a voltage higher than a signal voltage applied during normal operation, and the control circuit includes a circuit that detects the voltage. Semiconductor storage device.