JPS6113398B2 - - Google Patents
Info
- Publication number
- JPS6113398B2 JPS6113398B2 JP4794881A JP4794881A JPS6113398B2 JP S6113398 B2 JPS6113398 B2 JP S6113398B2 JP 4794881 A JP4794881 A JP 4794881A JP 4794881 A JP4794881 A JP 4794881A JP S6113398 B2 JPS6113398 B2 JP S6113398B2
- Authority
- JP
- Japan
- Prior art keywords
- solder
- printed wiring
- circuit board
- printed circuit
- opening hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910000679 solder Inorganic materials 0.000 claims description 39
- 238000007598 dipping method Methods 0.000 claims description 18
- 239000011888 foil Substances 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000004907 flux Effects 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 229920001342 Bakelite® Polymers 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004637 bakelite Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000013011 mating Effects 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Molten Solder (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
【発明の詳細な説明】
本発明はプリント配線板、特に絶縁素板から打
抜かれるプリント基板に開口孔が設けられている
プリント配線板の半田デイツプ方法の改良に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a solder dipping method for printed wiring boards, particularly printed wiring boards in which openings are provided in the printed wiring board punched out of an insulating blank.
片面に予め所望パターンの導電箔回路が形成さ
れ他面から回路素子の端子足が導電箔回路に向つ
て貫通突出されるプリント基板に半田デイツプに
て半田付けを行なうプリント配線板の半田デイツ
プ方法が周知であり、広範囲の分野において効率
の良い電気回路基板として用いられている。 A solder dip method for a printed wiring board involves soldering using a solder dip to a printed circuit board on which a conductive foil circuit of a desired pattern is previously formed on one side and terminal legs of circuit elements are projected through the conductive foil circuit from the other side. It is well known and used as an efficient electrical circuit board in a wide range of fields.
第１図にはこの種のプリント配線板の一例が示
されており、プリント基板１０はベークライト或
いはプラスチツク等の絶縁材から成り、その片面
に予め銅箔等によつて導電箔回路１２が形成され
ており、所望の回路パターンがプリント基板１０
上に設けられる。そして、プリント基板１０は絶
縁素板１４から所望形状に打抜かれ、次に、半田
デイツプを行なうために前記打抜かれたプリント
基板１０が再び絶縁素板１４に抜脱自在に嵌合保
持される。そして、第２図に示されるように、プ
リント基板１０の他面から所定の回路素子がその
端子足を導電箔回路１２側に突出した状態で装着
され、周知の半田デイツプが行なわれる。従つ
て、各端子足１６と導電箔回路１２とは半田１８
によつて強固にかつ電気的に良好な導通状態で接
続固定されることとなる。以上の半田デイツプが
完了した後、プリント基板１０は絶縁素板１４か
ら抜脱され、所望の電気回路板が極めて容易に完
成することとなる。通常の場合、プリント基板、
特に小型のたとえば時計用回路基板として用いら
れるようなプリント基板にあつては一枚の絶縁素
板１４から複数枚のプリント基板が同時に打抜き
及び半田デイツプされ、この結果、大量のプリン
ト基板を単時間にかつ良好な品質で製作すること
ができるという利点を有する。 FIG. 1 shows an example of this type of printed wiring board, in which a printed wiring board 10 is made of an insulating material such as Bakelite or plastic, and a conductive foil circuit 12 is previously formed on one side of it using copper foil or the like. The desired circuit pattern is printed on the printed circuit board 10.
provided above. Then, the printed circuit board 10 is punched out into a desired shape from the insulating base plate 14, and then the punched printed circuit board 10 is removably fitted onto the insulating base plate 14 again for solder dipping. Then, as shown in FIG. 2, a predetermined circuit element is mounted on the other surface of the printed circuit board 10 with its terminal leg protruding toward the conductive foil circuit 12, and a well-known solder dip is performed. Therefore, each terminal foot 16 and conductive foil circuit 12 are connected to each other by solder 18.
This ensures a strong connection and fixation with good electrical continuity. After the above solder dip is completed, the printed circuit board 10 is removed from the insulating base plate 14, and a desired electric circuit board can be completed very easily. In normal cases, printed circuit boards,
Particularly in the case of small-sized printed circuit boards, such as those used as circuit boards for watches, a plurality of printed circuit boards are punched out and soldered at the same time from one insulating base plate 14, and as a result, a large number of printed circuit boards can be manufactured in a single time. It has the advantage of being able to be manufactured with high quality and high quality.
しかしながら、このような従来のプリント配線
板の半田デイツプ方法においても、プリント基板
１０に比較的大きな内径を有する開口孔が必要な
場合には種々の問題が生じていた。このような開
口孔はたとえばトリマコンデンサ、可変抵抗など
回路使用状態にて調整を必要とする回路素子にお
ける調整孔、接点素子のチエツク用孔或いは各接
続端子の出力取出し用孔等として用いられ、第１
図においてはトリマコンデンサ２０を導電箔回路
１２側から調整するための孔として開口孔２２が
示されている。これらの開口孔２２はドライバそ
の他の治具を挿入するために比較的大きな内径を
有し、このために、第１図のような開口孔２２が
開いた状態で半田デイツプを行なうと、フラツク
スあるいは半田が開口孔２２から矢印のごとくプ
リント基板１０の上面に盛り上り、回路素子その
他に付着するなどして電気回路を破損するという
事故が生じていた。 However, even in such a conventional solder dipping method for a printed wiring board, various problems have arisen when the printed circuit board 10 requires an opening having a relatively large inner diameter. Such opening holes are used, for example, as adjustment holes in circuit elements such as trimmer capacitors and variable resistors that require adjustment during circuit use, check holes for contact elements, or output holes for connection terminals. 1
In the figure, an opening hole 22 is shown as a hole for adjusting the trimmer capacitor 20 from the conductive foil circuit 12 side. These opening holes 22 have relatively large inner diameters for inserting drivers and other jigs, and therefore, if solder dip is performed with the opening holes 22 open as shown in FIG. Accidents have occurred in which solder bulges from the opening hole 22 onto the top surface of the printed circuit board 10 as shown by the arrow and adheres to circuit elements and other parts, damaging the electrical circuit.
このために、従来では、前記開口孔２２にマス
キングテープを貼着した状態で半田デイツプを行
なう等の手段が採られていたが、これでは作業性
が著しく低下し、また半田付着不良が生じる等の
問題があつた。 To this end, conventional methods have been taken such as performing solder dipping with masking tape pasted on the opening hole 22, but this significantly reduces workability and also causes poor solder adhesion. There was a problem.
このために、従来の改良されたプリント配線板
の半田デイツプ方法では、第２，３図で示される
ように、開口孔２２を打抜いた後に、該打抜き板
２４を一旦開口孔２２に抜脱可能に嵌合保持し、
開口孔２２を閉塞した状態で半田デイツプが行な
われる構成としている。この従来装置によれば、
半田デイツプ時に開口孔２２が打抜き板２４によ
つて閉塞されているので、フラツクス或いは半田
の漏れがなく、プリント配線板の製作歩留まりが
著しく改善された。 For this reason, in the conventional improved solder dipping method for printed wiring boards, as shown in FIGS. Allows for mating and retention
The configuration is such that solder dipping is performed with the opening hole 22 closed. According to this conventional device,
Since the opening hole 22 is closed by the punched plate 24 during solder dipping, there is no leakage of flux or solder, and the manufacturing yield of printed wiring boards is significantly improved.
しかしながら、この従来装置では、半田デイツ
プ後に打抜き板２４を開口孔２２から抜脱する作
業が面倒であり、通常の場合、ピンセツトその他
により第２図の下面から打抜き板２４を開口孔２
２から除去するが、この時にピンセツトに破損が
生じたり或いはプリント基板１０もしくは回路素
子に傷を付けてしまうなどの欠点があり、不良品
発生率が増大しまた製造工程を自動化できないな
どの欠点が生じていた。 However, in this conventional device, it is troublesome to remove the punching plate 24 from the opening hole 22 after soldering, and in normal cases, the punching plate 24 is removed from the bottom surface of the opening hole 22 using tweezers or the like.
However, at this time, there are disadvantages such as damage to the tweezers or damage to the printed circuit board 10 or circuit elements, an increase in the incidence of defective products, and the inability to automate the manufacturing process. It was happening.
本発明は上記従来の課題に鑑みなされたもので
あり、その目的は、半田デイツプ時にフラツクス
或いは半田の漏れがなくかつ製作の容易な改良さ
れたプリント配線板の半田デイツプ方法を提供す
ることにある。 The present invention has been made in view of the above-mentioned conventional problems, and an object of the present invention is to provide an improved solder dip method for a printed wiring board that does not leak flux or solder during solder dip and is easy to manufacture. .
上記目的を達成するために、本発明は、少なく
とも片面に予め導電箔回路が形成されたプリント
基板が絶縁素板から打抜かれた後、前記プリント
基板が前記絶縁素板に抜脱自在に嵌合保持された
状態で回路素子の半田デイツプが行なわれるプリ
ント配線板の半田デイツプ方法において、絶縁素
板に連通した半島状の突出部がプリント基板に設
けられる開口孔部を抜脱自在に嵌合閉塞すること
により、半田デイツプ時に前記開口孔からの半田
流れを防止するとともに絶縁素板からのプリント
基板の抜脱時に開口孔部も同時に抜脱されること
を特徴とする。 In order to achieve the above object, the present invention provides that after a printed circuit board on which a conductive foil circuit is previously formed on at least one side is punched out of an insulating base plate, the printed circuit board is removably fitted to the insulating base plate. In the solder dipping method for printed wiring boards, in which circuit elements are soldered in a held state, a peninsula-shaped protrusion communicating with the insulating base plate removably fits into and closes an opening provided in the printed circuit board. By doing so, the flow of solder from the opening hole is prevented during solder dipping, and the opening hole portion is also removed at the same time when the printed circuit board is removed from the insulating blank board.
以下図面に基づいて本発明の好適な実施例を説
明する。 Preferred embodiments of the present invention will be described below based on the drawings.
第４図には本発明を用いて複数の時計用電気回
路基板を連続的に得るための概略構成が示され、
絶縁素板１４からは複数のプリント基板１０が同
時に打抜き及び半田デイツプされる。プリント基
板１０の片面には予め導電箔回路１２が所望のパ
ターンで形成されており、該導電箔回路１２の必
要箇所に半田が固着される。 FIG. 4 shows a schematic configuration for continuously obtaining a plurality of electric circuit boards for watches using the present invention,
A plurality of printed circuit boards 10 are simultaneously punched out and solder-dipped from the insulating blank 14. A conductive foil circuit 12 is previously formed in a desired pattern on one side of the printed circuit board 10, and solder is adhered to the required locations of the conductive foil circuit 12.
本発明において特徴的なことは、プリント基板
１０に設けられる開口孔２２、実施例においては
トリマコンデンサの調整用孔が絶縁素板１４に連
通した半島状の突出部１４ａにて抜脱自在に嵌合
閉塞されていることであり、この半島状の突出部
１４ａは絶縁素板１４からプリント基板１０の外
形が打抜かれる時に同時に打抜き形成される。そ
して、プリント基板１０が絶縁素板１４に再び嵌
合保持される時、前記開口孔２２も同時に突出部
１４ａにより抜脱自在に嵌合閉塞され、従来のよ
うに、いつたん打抜かれた打抜板２４を人手によ
り開口孔２２に挿入する手間を省くことが可能と
なる。このようにして、プリント基板１０が絶縁
素板１４に嵌合され、同時に半島状の突出部１４
ａが開口孔２２に抜脱自在に嵌合閉塞した状態で
半田デイツプが行なわれる。従つて、この半田デ
イツプ時には開口孔２２からフラツクス或いは半
田が漏れることがなく、不良発生のない良好なプ
リント配線板を得ることが可能となる。 The characteristic feature of the present invention is that the opening hole 22 provided in the printed circuit board 10, in the embodiment, the adjustment hole of the trimmer capacitor, is removably fitted into the peninsular protrusion 14a communicating with the insulating base plate 14. This peninsular protrusion 14a is punched out at the same time as the outer shape of the printed circuit board 10 is punched out from the insulating blank 14. When the printed circuit board 10 is again fitted and held on the insulating base plate 14, the opening hole 22 is also removably fitted and closed by the protruding portion 14a, and as in the conventional case, the opening hole 22 is removably fitted and closed. It becomes possible to save the effort of manually inserting the plate 24 into the opening hole 22. In this way, the printed circuit board 10 is fitted to the insulating base plate 14, and at the same time, the peninsular protrusion 14
Solder dipping is performed in a state where a is removably fitted into the opening hole 22 and closed. Therefore, during this solder dipping, flux or solder does not leak from the opening 22, making it possible to obtain a good printed wiring board with no defects.
さらに、半田デイツプ完了後、プリント基板１
０は絶縁素板１４から抜き出されるがこの抜脱時
に開口孔２２を閉塞していた突出部１４ａも開口
孔２２から同時に抜脱され、従来のように人手に
よる効率の悪い除去作業を必要とすることなく極
めて容易に開口孔２２を完成させることが可能と
なる。従つて、本発明によれば、一連のプリント
配線板製造工程を全自動とすることも可能とな
り、製造効率を著しく改善することができる。 Furthermore, after completing the solder dip, the printed circuit board 1
0 is extracted from the insulating base plate 14, but at the time of this extraction, the protrusion 14a that was blocking the opening hole 22 is also removed from the opening hole 22 at the same time, requiring inefficient manual removal work as in the past. It becomes possible to complete the opening hole 22 extremely easily without having to do anything. Therefore, according to the present invention, it is possible to fully automate a series of printed wiring board manufacturing processes, and manufacturing efficiency can be significantly improved.
第５図には本発明の他の実施例が示され、プリ
ント基板１０の一方の面に設けられた端子などか
らリード線により出力を取り出す際の開口孔２２
が突出部１４ａによつて閉塞されている状態を示
し、図において突出部１４ａはほぼストレートな
形状から成る。 FIG. 5 shows another embodiment of the present invention, in which an opening hole 22 is used to take out an output from a terminal or the like provided on one side of a printed circuit board 10 using a lead wire.
The figure shows a state in which the protrusion 14a is closed by the protrusion 14a, and the protrusion 14a has a substantially straight shape in the figure.
第６図にはさらに本発明に係る突出部１４ａの
他の構造が示され、この実施例によれば突出部１
４ａは絶縁素板１４から開口孔２２に向つて狭ま
るテーパ状に形成され、開口孔部が容易に抜脱で
きる構造となつている。 FIG. 6 further shows another structure of the protrusion 14a according to the present invention, and according to this embodiment, the protrusion 1
4a is formed in a tapered shape that narrows from the insulating base plate 14 toward the opening hole 22, and has a structure that allows the opening hole portion to be easily removed.
以上説明したように、本発明によれば、絶縁素
板に連通した半島状の突出部がプリント基板に設
けられる開口孔を閉塞した状態で半田デイツプを
行なうことができるため、フラツクス或いは半田
の漏れがなく、特に開口孔に対向して回路素子が
配置される構成にあつては回路素子がフラツクス
或いは半田による熱的或いは化学的な影響を受け
ないので電気回路の不良率を著しく減少させるこ
とが可能となる。また、本発明によれば開口孔を
閉塞する突出部が絶縁素板と一体連通しているの
で、その抜脱がプリント基板自体の抜脱と同時に
行なわれ製造工程の自動化に寄与するところが大
である。 As explained above, according to the present invention, solder dipping can be performed with the peninsula-shaped protrusion communicating with the insulating base plate blocking the opening provided in the printed circuit board, thereby preventing leakage of flux or solder. In particular, in a configuration in which the circuit elements are arranged opposite to the openings, the circuit elements are not thermally or chemically affected by flux or solder, so the defective rate of the electric circuit can be significantly reduced. It becomes possible. Further, according to the present invention, since the protrusion that closes the opening is integrally communicated with the insulating base plate, its removal is performed at the same time as the removal of the printed circuit board itself, which greatly contributes to automation of the manufacturing process. .
前述した実施例では、時計用のプリント基板が
示されているが、このようなプリント基板は腕時
計用の小さな基板から掛時計用の比較的大きな基
板或いはその他任意の電気回路に用いられるプリ
ント基板に適用可能である。 In the above embodiment, a printed circuit board for a watch is shown, but such a printed circuit board can be applied to a small circuit board for a wristwatch, a relatively large circuit board for a wall clock, or a printed circuit board used for any other electrical circuit. It is possible.
第１図は従来の一般的なプリント配線板を示す
要部断面図、第２図は従来の改良されたプリント
配線板の要部断面図、第３図は第２図の要部底面
図、第４図は本発明方法に係るプリント配線板の
好適な実施例を示す概略説明図、第５，６図はそ
れぞれ本発明方法に係るプリント配線板の他の実
施例構造を示す要部平面図である。
１０……プリント基板、１２……導電箔回路、
１４……絶縁素板、１８……半田、２２……開口
孔、１４ａ……突出部。
Fig. 1 is a sectional view of the main parts of a conventional general printed wiring board, Fig. 2 is a sectional view of the main parts of a conventional improved printed wiring board, and Fig. 3 is a bottom view of the main parts of Fig. 2. FIG. 4 is a schematic explanatory diagram showing a preferred embodiment of the printed wiring board according to the method of the present invention, and FIGS. 5 and 6 are plan views of main parts showing other embodiments of the structure of the printed wiring board according to the method of the present invention, respectively. It is. 10... Printed circuit board, 12... Conductive foil circuit,
14...Insulating base plate, 18...Solder, 22...Opening hole, 14a...Protrusion part.
Claims (1)
ているプリント基板が絶縁素板から打抜かれた
後、前記プリント基板が前記絶縁素板に抜脱自在
に嵌合保持された状態で回路素子の半田デイツプ
が行われるプリント配線板の半田デイツプ方法に
おいて、絶縁素板に連通した半島状の突出部がプ
リント基板に設けられる開口孔を抜脱自在に嵌合
閉塞（マスキング）することにより、半田デイツ
プ時に前記開口孔からの半田流れを防止するとと
もに絶縁素板からのプリント基板の抜脱時に開口
孔部も同時に抜脱されることを特徴とするプリン
ト配線板の半田デイツプ方法。 ２ 特許請求の範囲１記載のプリント配線板の半
田デイツプ方法において、前記プリント基板の開
口孔に回路素子を対向配置して半田デイツプする
ことを特徴とするプリント配線板の半田デイツプ
方法。 ３ 特許請求の範囲１又は２記載のプリント配線
板の半田デイツプ方法において、開口孔を閉塞す
る半島状の突出部を開口孔に向かつて狭まるテー
パ状に形成し、プリント配線板を半田デイツプす
ることを特徴とするプリント配線板の半田デイツ
プ方法。[Scope of Claims] 1. A state in which, after a printed circuit board on which a conductive foil circuit is previously formed on at least one side is punched out of an insulating base plate, the printed circuit board is removably fitted onto the insulating base plate and held therein. In the solder dipping method for printed wiring boards in which circuit elements are soldered in the solder dipping method, a peninsular protrusion communicating with an insulating base plate removably fits and closes (masks) an opening provided in a printed circuit board. A solder dipping method for a printed wiring board, characterized in that the flow of solder from the opening hole is prevented during solder dipping, and the opening hole portion is also removed at the same time when the printed circuit board is removed from the insulating blank board. 2. The solder dipping method for a printed wiring board according to claim 1, characterized in that circuit elements are disposed facing each other in the openings of the printed wiring board and soldered therein. 3. In the solder dipping method for a printed wiring board according to claim 1 or 2, the peninsula-shaped protrusion that closes the opening hole is formed in a tapered shape that narrows toward the opening hole, and the printed wiring board is soldered-dipped. A solder dip method for printed wiring boards characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4794881A JPS57162492A (en) | 1981-03-31 | 1981-03-31 | Printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4794881A JPS57162492A (en) | 1981-03-31 | 1981-03-31 | Printed circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57162492A JPS57162492A (en) | 1982-10-06 |
| JPS6113398B2 true JPS6113398B2 (en) | 1986-04-12 |
Family
ID=12789581
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4794881A Granted JPS57162492A (en) | 1981-03-31 | 1981-03-31 | Printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57162492A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS585400U (en) * | 1981-07-02 | 1983-01-13 | 三菱電機株式会社 | Electronic component packaging |
-
1981
- 1981-03-31 JP JP4794881A patent/JPS57162492A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57162492A (en) | 1982-10-06 |
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