JPS6113340U - Recording/playback device - Google Patents

Recording/playback device

Info

Publication number
JPS6113340U
JPS6113340U JP9317284U JP9317284U JPS6113340U JP S6113340 U JPS6113340 U JP S6113340U JP 9317284 U JP9317284 U JP 9317284U JP 9317284 U JP9317284 U JP 9317284U JP S6113340 U JPS6113340 U JP S6113340U
Authority
JP
Japan
Prior art keywords
signal
recording
modulation
main
outputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9317284U
Other languages
Japanese (ja)
Inventor
憲一 佐藤
Original Assignee
三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三洋電機株式会社 filed Critical 三洋電機株式会社
Priority to JP9317284U priority Critical patent/JPS6113340U/en
Publication of JPS6113340U publication Critical patent/JPS6113340U/en
Pending legal-status Critical Current

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  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の記録再生装置の1実施例の・ ブロ
ック図、第2図aはNRZ−1方式の変調信号の波形図
、同図bはPE方式の変調信号の波形図、同図Cは同図
aの変調信号から形成されたクロック信号の波形薗、同
図dは同図bの変調信号から形成されたクロツク信号の
波形図である。 3a〜3n・・・主記録変調回路、6・・・副記録変調
回路、9・・・記録テープ、20・・・位相比較回路、
21・・・キャプスタンモータ、22・・・クロツク再
生処理部、2′5・・・基準信号形成部、27・・・駆
動回路。
Fig. 1 is a block diagram of one embodiment of the recording/reproducing apparatus of this invention, Fig. 2a is a waveform diagram of a modulation signal of the NRZ-1 system, and Fig. 2b is a waveform diagram of a modulation signal of the PE system. C is a waveform diagram of a clock signal formed from the modulation signal shown in FIG. 3a to 3n... Main recording modulation circuit, 6... Sub recording modulation circuit, 9... Recording tape, 20... Phase comparison circuit,
21... Capstan motor, 22... Clock regeneration processing section, 2'5... Reference signal forming section, 27... Drive circuit.

Claims (1)

【実用新案登録請求の範囲】 ■ 主デジタルデータを変調して主変調信号を出力する
主記録変調回路と、副デジタルデータをクロツク再生能
力係数の大きい変調方式により変調して副変調信号を出
力する副記録変調回路と、キャプスタンモータの回転に
より走行するとともに、前記主、副変調信号が異なるト
ラックにそれぞれ記録される記録テープと、該テープか
ら再生された前記副変調信号からクロツク信号を形成し
、該クロック信号にもとづく速度制御参照信号を出力す
るクロツク再生処理部と、内部形成した速度制御基準信
号を出力する基準信号形成部と、前記参照信号と前記基
準信号との位相差に比例した位相差信号を出力する位相
比較回路と、前記位相差信号に比例した駆動信号を前記
モータに供給し、前記モータの回転を前記基準信号にも
とづく基準回転に制御して前記テープの走行をサーボ制
御する駆動回路とを備えた記録再生装置。 ■ 主変調回路に、主デジタルデータを記録密度係数の
大きい変調方式により変調する手段を設けた実用新案登
録請求の範囲第1項に記載の記録再生装置。
[Claims for Utility Model Registration] ■ A main recording modulation circuit that modulates main digital data and outputs a main modulation signal, and a main recording modulation circuit that modulates main digital data and outputs a sub-modulation signal by modulating sub-digital data using a modulation method with a large clock reproduction capability coefficient. A clock signal is formed from the sub-recording modulation circuit, a recording tape that is run by the rotation of a capstan motor and on which the main and sub-modulation signals are respectively recorded on different tracks, and the sub-modulation signal reproduced from the tape. , a clock regeneration processing unit that outputs a speed control reference signal based on the clock signal, a reference signal forming unit that outputs an internally generated speed control reference signal, and a phase difference proportional to the phase difference between the reference signal and the reference signal. A phase comparison circuit that outputs a phase difference signal and a drive signal proportional to the phase difference signal are supplied to the motor, and the rotation of the motor is controlled to a reference rotation based on the reference signal to servo control the running of the tape. A recording/reproducing device equipped with a drive circuit. (2) The recording and reproducing apparatus according to claim 1, wherein the main modulation circuit is provided with means for modulating the main digital data using a modulation method with a large recording density coefficient.
JP9317284U 1984-06-20 1984-06-20 Recording/playback device Pending JPS6113340U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9317284U JPS6113340U (en) 1984-06-20 1984-06-20 Recording/playback device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9317284U JPS6113340U (en) 1984-06-20 1984-06-20 Recording/playback device

Publications (1)

Publication Number Publication Date
JPS6113340U true JPS6113340U (en) 1986-01-25

Family

ID=30650610

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9317284U Pending JPS6113340U (en) 1984-06-20 1984-06-20 Recording/playback device

Country Status (1)

Country Link
JP (1) JPS6113340U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5067023A (en) * 1973-10-12 1975-06-05
JPS50153606A (en) * 1974-05-30 1975-12-10

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5067023A (en) * 1973-10-12 1975-06-05
JPS50153606A (en) * 1974-05-30 1975-12-10

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