JPS61132089A - Speed controller for motor - Google Patents

Speed controller for motor

Info

Publication number
JPS61132089A
JPS61132089A JP59254480A JP25448084A JPS61132089A JP S61132089 A JPS61132089 A JP S61132089A JP 59254480 A JP59254480 A JP 59254480A JP 25448084 A JP25448084 A JP 25448084A JP S61132089 A JPS61132089 A JP S61132089A
Authority
JP
Japan
Prior art keywords
speed
speed control
control data
compensation
compensator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59254480A
Other languages
Japanese (ja)
Inventor
Masakatsu Nomura
昌克 野村
Tadashi Ashikaga
足利 正
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Meidensha Electric Manufacturing Co Ltd
Original Assignee
Meidensha Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Meidensha Electric Manufacturing Co Ltd filed Critical Meidensha Electric Manufacturing Co Ltd
Priority to JP59254480A priority Critical patent/JPS61132089A/en
Publication of JPS61132089A publication Critical patent/JPS61132089A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02PCONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P23/00Arrangements or methods for the control of AC motors characterised by a control method other than vector control
    • H02P23/20Controlling the acceleration or deceleration

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Control Of Electric Motors In General (AREA)

Abstract

PURPOSE:To obtain high speed responsiveness at accelerating/decelerating time or high speed time by providing a compensator to detect the speed or to calculate speed control data by the delay of sampling process or calculating. CONSTITUTION:A compensator 7 inputs speed control data of the output of a speed control calculator 6 to compensator the calculation delay by the sampling process of the calculator 6. The compensator 7 has a bypass switch 8 for releasing the compensating process. A gate circuit 9 obtains the phase control data of a power converter from the speed control data fed through the compensator 7 or the switch 8 at every phase switch element, and distributes to output the data. A speed comparator 10 releases the compensating operation by switching bypass switches 3, 8 to ON state when the detected value of a speed detector 1 becomes the set value or lower of a switching speed setter 11.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は電動機の速度制御装置に係わり、特にディジタ
ル処理方式の速度制御装置に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a speed control device for an electric motor, and more particularly to a speed control device using a digital processing method.

に来の技術 一般゛に、電動機の速度制御には電動機の速度検出値と
設定値とを比較するフィードバック制御が多く採用され
、高精度の速度制御にはディジタル処理による速度制御
装置が採用される。このディジタル処理方式では、電動
機の速度噴出にパルスピックアップ等のディジタル式速
度検出器が採用され、このディジタル量の速度検出値は
マイクロコンピユー2夕等のディジタル処理装置に取込
まれて速度設定値との比較さらには速度演算処理されて
電動機の速度制御データと゛して取出される。
In recent technology, feedback control that compares the detected motor speed value with a set value is often used for motor speed control, and speed control devices using digital processing are used for high-precision speed control. . In this digital processing method, a digital speed detector such as a pulse pickup is used to detect the speed of the motor, and this digital speed detection value is taken into a digital processing device such as a microcomputer and converted into a speed setting value. Further, the speed is subjected to speed calculation processing and extracted as motor speed control data.

例えば、パルスピックアップに電動機の回転速度に比例
した間隔のパルスを出力し、このパルス間隔をカウンタ
のクロック計数期間として該カウンタの計数値を速度検
出値としてディジタル処理装置に取込ませ、ディジタル
処理装置では速度噴出値と速度設定値との偏差を求め、
この偏差をアナログ式速度制御増幅器と同等の比例積分
(Pり演算して速度制御データを得る。また、速度制御
データは電動機の各種制御方式に従って必要な演算処理
がなされ、最終的には電動機の電源になるインバータ、
順変換器等の電力変換器の側脚信号として取出される。
For example, output pulses at intervals proportional to the rotational speed of the motor to a pulse pickup, use these pulse intervals as the clock counting period of a counter, and input the count value of the counter as a speed detection value into a digital processing device. Now, find the deviation between the speed ejection value and the speed setting value,
Speed control data is obtained by calculating the proportional integral (P) of this deviation, which is equivalent to an analog speed control amplifier.The speed control data is also subjected to the necessary arithmetic processing according to the various control methods of the motor, and is ultimately used to control the motor. Inverter as power source,
It is extracted as a side leg signal of a power converter such as a forward converter.

発明が解決しようとする問題点 ディジタル処理方式の速度制御装置は、アナログ処理方
式のものに較べて高精度制御lt−容易にするが、速度
検出やPI演算がサンプリング処理になるためサンプリ
ング時間の遅れが電動機の制御遅れの原因になることが
ある◎例えば、高速応答性を持たせるサイリスタレオナ
ード力式の直流機速度制御や誘導機のペクト”ル制御、
特に高速域の加減速時にサンプリング時間の遅れで設定
通シの加減速度、トルクを得ることができないことが起
きる。
Problems to be Solved by the Invention Digital processing type speed control devices facilitate high-precision control compared to analog processing type ones, but speed detection and PI calculation involve sampling processing, resulting in a delay in sampling time. ◎For example, thyristor Leonard force type DC machine speed control that provides high-speed response, induction motor pectol control,
Particularly when accelerating and decelerating in a high-speed range, it may not be possible to obtain the set acceleration/deceleration and torque due to the delay in sampling time.

具体的には、誘導機のベクトル制御では、トルクとすベ
シ局波数を比例するようK fill mlするが、定
格トルクで加速したときに誘導機が0.2秒で定格囮1
転数に達するものとすると1.速度検出のサンプリング
時間が10m5ecとすそとサンプリング時間内に上昇
する速度は5に(=0.0110.28100)もあり
、このサンプリング時、1間の遅れ分が適切なすベクト
ル制御を難しくする。
Specifically, in the vector control of the induction machine, K fill ml is performed so that the torque and the base station wave number are proportional, but when the induction machine accelerates at the rated torque, the rated decoy 1 is reached in 0.2 seconds.
Assuming that the number of rotations is reached, 1. If the sampling time for speed detection is 10 m5 ec, the speed that increases within the sampling time is as high as 5 (=0.0110.28100), and during this sampling, the delay of 1 hour makes appropriate vector control difficult.

問題点を解決するための手段と作用 本発明は、ディジタル処理方式の電動機の速度制御装置
において、速度検出値又は速度制御データの少なくとも
一方にサンプリング時間等の遅れを補償する補償回路を
設け、この補償回路は速度検出値又は速度制御データに
なる入力と、この入力の変化率に遅れ補償時間を乗算、
した値とを加算する構成にし、サンプリング、処理等に
よる速度制御遅れを補償した速度制御動作を達成するも
のである。
Means and Function for Solving the Problems The present invention provides a speed control device for a motor using a digital processing method, in which a compensation circuit is provided for compensating for a delay in sampling time or the like in at least one of the speed detection value or the speed control data. The compensation circuit takes the input that becomes the speed detection value or speed control data, multiplies the rate of change of this input by the delay compensation time,
The system is configured to add the calculated values, thereby achieving a speed control operation that compensates for speed control delays due to sampling, processing, etc.

実権例 第1図は本発明の一実織例を示すブロック図である。速
度検出回路1は鉱来のパルスピックアップとカウンタを
具えるディジタル式速度検出器、と同じもの、好ましく
は特開昭59−38661号公報に開示されるように、
パルスピックアップの出力パルス間隔の大小に応じて定
める数のパルス期間をサンプリング時間とし、該サンプ
リング時間  、、円のクロックパルス数から電動機の
速度検出値古来めることによって可変速範囲全域に亘っ
て速度  ゛検出精度及び応答時間をほぼ一定にする速
度検出器にされる。
Practical Example FIG. 1 is a block diagram showing one practical example of the present invention. The speed detection circuit 1 is the same as a digital speed detector comprising a conventional pulse pickup and a counter, preferably as disclosed in Japanese Patent Application Laid-Open No. 59-38661.
The number of pulse periods determined according to the magnitude of the output pulse interval of the pulse pickup is taken as the sampling time, and the sampling time is calculated from the number of circular clock pulses to the speed detection value of the motor over the entire variable speed range.゛The speed detector is made to have almost constant detection accuracy and response time.

補償回路2は速度検出回路1の出力になる速度検出値を
入力とし、該速度検出回路lのサンプリング処理による
速度検出遅れを補償する0この補償回路2にはその補償
処理を解除させるためのバイパススイッチ3が設けられ
る。加算器4は電動機の速度設定器5の設定値と補償回
路2又はバイパススイッチ3t−通した速度検出値との
差を演算する。速度制御演算部6は加算器4の出力から
サンプリング処理によって比例積分演算をして速度開開
データを得る。補償回路7は速度制御演算部6の出力に
なる速度制御データを入力とし、該速度制御演算部6の
サンプリング処理による演算遅れを補償する。この補償
回路7にはその補償処理を解除させるためのバイパスス
イッチ8が設けられる。ゲート回路9は補償回路7又は
バイパススィッチ8全通した速度制御データから電力変
換器(図示しない)の位相制御データを各相スイッチ素
子別に求めて分配出力する。速度比鮫部10は速度噴出
回路1の検出値が切換速度設定器11の設定fit以丁
になるときにバイパススイッチ3及び811:オン状態
に切換えることで補償動作を解除する。
The compensation circuit 2 inputs the speed detection value that is the output of the speed detection circuit 1, and compensates for the speed detection delay due to the sampling process of the speed detection circuit 1.The compensation circuit 2 has a bypass for canceling the compensation process. A switch 3 is provided. The adder 4 calculates the difference between the set value of the motor speed setter 5 and the speed detected value passed through the compensation circuit 2 or the bypass switch 3t. The speed control calculation unit 6 performs proportional integral calculation on the output of the adder 4 through sampling processing to obtain speed opening/opening data. The compensation circuit 7 inputs the speed control data which is the output of the speed control calculation section 6, and compensates for the calculation delay due to the sampling process of the speed control calculation section 6. This compensation circuit 7 is provided with a bypass switch 8 for canceling the compensation process. The gate circuit 9 obtains phase control data for a power converter (not shown) for each phase switch element from the speed control data passed through the compensation circuit 7 or the bypass switch 8, and distributes and outputs the obtained data. The speed ratio shark section 10 cancels the compensation operation by switching the bypass switches 3 and 811 to the ON state when the detected value of the speed ejection circuit 1 reaches the setting FIT of the switching speed setter 11.

この切換速度設定器11は例えば制+11装置がサイリ
スタレオナード方式による直流電動機の速度側−をする
ものでは直流機の基底速度に設定される。
This switching speed setting device 11 is set to the base speed of the DC motor, for example, in a case where the control +11 device operates on the speed side of a DC motor using a thyristor Leonard system.

こうした構成において、速度検出回路1の速度検出値及
び速度制御演算部6の速度制御データは、電動機が基底
速度以上の高速度領域で運転されるときにはバイパスス
イッチ3.8がオフになり、交々補償回路2,7によっ
てサンプリング処理による遅れの補償がなされて速度側
−の応答性が改善される。
In such a configuration, the speed detection value of the speed detection circuit 1 and the speed control data of the speed control calculation unit 6 are changed when the motor is operated in a high speed region higher than the base speed, and the bypass switch 3.8 is turned off. The compensation circuits 2 and 7 compensate for the delay caused by the sampling process, thereby improving the responsiveness on the speed side.

このような補償回路2及び7t−付加した遅れ補償を第
2図を参照して説明する。速度検出回路1の入力(又は
速度制御演算部6の入力)が第2図に特性fi(t) 
 で示すように加速されるとき、速度検出回路1(又は
速度制御演算部6)はサンプリング周期Ts f持って
サンプリングタイミングT’n−t l Tn + T
n+1で順次演算をする。このサンプリングタイミング
’rn−t l Tn l Til+1で夫々求められ
る出力f o (t)はサンプリング周期Ts及び演算
の遅れ金持って検出される。すなわち、出力fO(t)
の平均値は特性にで示すように入力f1(t)とに遅れ
時間Tを持って検出される。
The delay compensation added by such compensation circuits 2 and 7t will be explained with reference to FIG. The input of the speed detection circuit 1 (or the input of the speed control calculation unit 6) has the characteristic fi(t) shown in FIG.
When accelerated as shown by
Calculate sequentially with n+1. The output f o (t) obtained at each sampling timing 'rn-t l Tn l Til+1 is detected with a sampling period Ts and a calculation delay. That is, the output fO(t)
The average value of is detected with a delay time T from the input f1(t) as shown in the characteristic.

この遅れ時間Tt−補償するために、入力fl(t)を
遅れ補償時間でだけ進めた出力fO(t)とすること、
即ちクプシス演算子全便って示せば次式になるよp補償
回路2又は7で近似補償波s”を行なう。
In order to compensate for this delay time Tt, the input fl(t) is advanced by the delay compensation time to an output fO(t),
That is, if the total number of Kupsis operators is expressed as follows, the p compensation circuit 2 or 7 performs an approximate compensation wave s''.

oc、0” o(t) ) = e 5T−C(f 1
e))  =・・・・・(1)(1)式中、c、COは
ラプクス変換を示し、fo(t)は補償回路2又に7で
補償した出力、fl(1)は補償回路2又に7の入力で
ある。この(1)式中θ5Tt−チー2展開し時間Tの
一次までで近似するとeST中1+8T  ・・・・・
・・・・・・・・・・(2)となり、(1)式は実時間
で表わせば次式のようになる。
oc, 0” o(t) ) = e 5T-C(f 1
e)) =... (1) In formula (1), c and CO indicate Lapx transformation, fo(t) is the output compensated by compensation circuit 2 or 7, and fl(1) is the compensation circuit There are 7 inputs in 2 prongs. If we expand θ5Tt-Chi2 in equation (1) and approximate it up to the first order of time T, we get 1+8T in eST...
......(2), and the equation (1) becomes the following equation when expressed in real time.

即ち、サンプリング遅れによる補償には現在の入力、?
”1(t)とその変化率d/dt(fi(t))に補償
時間Tt−51!算し九値を加算することで補償ができ
る。
That is, to compensate for the sampling delay, the current input, ?
1(t) and its rate of change d/dt(fi(t)), the compensation time Tt-51! can be calculated, and the nine values are added.

この13)式をサンプリング系の演算式で表わせば次式
になる。
If this equation 13) is expressed as a sampling system arithmetic equation, it becomes the following equation.

f i (Tn−1) l  ・・・・・” −+41
第3図は補償回路2又は7の実織例を示し、上記(41
式に基づいて構成する場合である。第3図において、入
力fi(Tn)に対してサンプリング回路211とラッ
チ回路212によって1サンプル前の入力f1(Tl−
t)t−記憶しておき、この[fi(Tn−t)と今回
の入力f1(Tn)との差を加算器215で求め、これ
に乗算器21−において係数T/Taを乗算することで
変化率に補償時間Tt−乗算した[t−求め、これに加
算器215において今回の入力fi(Tn)t−加算し
て補償した出力fo(Tn) t−得る。
f i (Tn-1) l...” -+41
FIG. 3 shows an actual example of the compensation circuit 2 or 7, and shows the above (41)
This is a case where the configuration is based on a formula. In FIG. 3, the sampling circuit 211 and the latch circuit 212 generate the input f1 (Tl-
t) t- memorized, find the difference between this [fi (Tn-t) and the current input f1 (Tn) in the adder 215, and multiply it by the coefficient T/Ta in the multiplier 21-. The rate of change is multiplied by the compensation time Tt to find the current input fi(Tn)t in the adder 215 to obtain the compensated output fo(Tn)t.

なお、遅れ補償時間ではサンプリングによる遅れ時間の
ほかに、速度検出回路1又は速度制御演算部6の演算に
よる遅れも考慮して設定される。
Note that the delay compensation time is set in consideration of not only the delay time due to sampling but also the delay due to calculation by the speed detection circuit 1 or the speed control calculation unit 6.

また、′夾纏例はサイリスタレオナードの場合を示すが
、これはR4機のパルス幅変調制御やベクトル制御など
種々の連間制御方式のものに適用できるのは勿論である
。また、切換速置設定器L1と比較部lOによる補償回
路2及び7の補償処理解除は、電動機の高速と低速での
切換えに限らず加減速度の大小によって切換える構成に
するなど、サンプリング処理による遅れが問題となる制
御状態でのみ補償全行なうものにしても良い。
Further, although the ``consolidated example'' is a case of a thyristor Leonard, it is of course applicable to various continuous control systems such as pulse width modulation control and vector control of the R4 machine. In addition, the cancellation of the compensation processing of the compensation circuits 2 and 7 by the switching speed setting device L1 and the comparator 1O is not limited to switching between high and low speeds of the motor, but is also configured to switch according to the magnitude of acceleration/deceleration, etc., due to the delay due to sampling processing. It may also be possible to perform full compensation only in control states where this is a problem.

ざらに、補償回路は各サンプリング処理回路での遅れを
個別に補償するに限らず、補償口i&2又は7の何れか
一万に設けるものにして応答性を確保するものでも良い
In general, the compensation circuit is not limited to individually compensating the delay in each sampling processing circuit, but may be provided at any one of the compensation ports i&2 or 7 to ensure responsiveness.

発明の効果 本発明に工れば、ディジタル処理方式による電動機の速
度制#J装置において、速度検出や速度制御データの演
算に、サンプリング処理や演算による遅れを補償する補
償回路を設ける丸め、直流機のサイリスタレオナード制
御や碍導機のベクトル制御等の速度制御に適用して、加
減速時や高速時の高速応答性を得ることができ、また定
常時に補償処理を解除することに1って、外乱に対して
整定′  精度の良い制1111を得ることができる効
果がある。
Effects of the Invention If the present invention is applied, in a speed control #J device for an electric motor using a digital processing method, a compensation circuit for compensating for delays caused by sampling processing and calculation in speed detection and calculation of speed control data can be provided. It can be applied to speed control such as thyristor Leonard control and vector control of insulators to obtain high-speed response during acceleration/deceleration and high speed, and is also useful for canceling compensation processing during steady state. This has the effect of providing a highly accurate settling control 1111 against disturbances.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実権例を示すブロック図、第2図は
第1図における補償回路の動作説明のための特性図、第
3図は第1因、に2ける補償回路の回路図である。 l・・・速度検出回路、2,7・・・補償回路、3,8
・・・バイパススイッチ、4・・・加算器、5・・・速
置設定器、6・・・速度制御演算部、9・・・ゲート回
路、10・・・速度比較部、11・・・切侯速匿投定器
、211川サンプリング回路、212・・・2ツチ回路
、213・・・加算器、2111・・・乗算器、215
・・・加算器。
Fig. 1 is a block diagram showing one practical example of the present invention, Fig. 2 is a characteristic diagram for explaining the operation of the compensation circuit in Fig. 1, and Fig. 3 is a circuit diagram of the compensation circuit for the first factor. It is. l... Speed detection circuit, 2, 7... Compensation circuit, 3, 8
... Bypass switch, 4... Adder, 5... Speed setting device, 6... Speed control calculation section, 9... Gate circuit, 10... Speed comparison section, 11... 211 River sampling circuit, 212... 2-bit circuit, 213... Adder, 2111... Multiplier, 215
...Adder.

Claims (2)

【特許請求の範囲】[Claims] (1)電動機の速度をサンプリング処理によってディジ
タル量で速度検出し、この速度検出値と速度設定値との
偏差からサンプリング処理によって電動機の速度制御デ
ータを得るディジタル処理方式の電動機の速度制御装置
において、前記速度検出値又は速度制御データの少なく
とも一方にサンプリング時間の遅れを補償する補償回路
を設け、この補償回路は速度検出値又は速度制御データ
になる入力と、この入力の変化率に遅れ補償時間を乗算
した値とを加算する構成にしたことを特徴とする電動機
の速度制御装置。
(1) In an electric motor speed control device using a digital processing method, the speed of the electric motor is detected as a digital quantity through sampling processing, and the speed control data of the electric motor is obtained through sampling processing from the deviation between the detected speed value and the speed setting value. A compensation circuit is provided for compensating for a sampling time delay in at least one of the speed detection value or speed control data, and this compensation circuit applies a delay compensation time to the input that becomes the speed detection value or speed control data and the rate of change of this input. A speed control device for an electric motor, characterized in that it is configured to add the multiplied value.
(2)特許請求の範囲第1項において、前記補償回路は
、電動機の加減速度又は絶対速度が低いときに補償処理
を解除する手段を含む構成にした電動機の速度制御装置
(2) The motor speed control device according to claim 1, wherein the compensation circuit includes means for canceling the compensation process when the acceleration/deceleration or absolute speed of the motor is low.
JP59254480A 1984-11-30 1984-11-30 Speed controller for motor Pending JPS61132089A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59254480A JPS61132089A (en) 1984-11-30 1984-11-30 Speed controller for motor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59254480A JPS61132089A (en) 1984-11-30 1984-11-30 Speed controller for motor

Publications (1)

Publication Number Publication Date
JPS61132089A true JPS61132089A (en) 1986-06-19

Family

ID=17265634

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59254480A Pending JPS61132089A (en) 1984-11-30 1984-11-30 Speed controller for motor

Country Status (1)

Country Link
JP (1) JPS61132089A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63148881A (en) * 1986-12-12 1988-06-21 Fanuc Ltd Speed control device for servo motor
JPH01126185A (en) * 1987-11-09 1989-05-18 Matsushita Electric Ind Co Ltd Speed controller
JPH0614573A (en) * 1992-06-23 1994-01-21 Japan Radio Co Ltd Motor speed controller

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52115977A (en) * 1976-03-26 1977-09-28 Hitachi Ltd Sampling controller
JPS59172990A (en) * 1983-03-19 1984-09-29 Yaskawa Electric Mfg Co Ltd Speed calculator in ac motor control

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52115977A (en) * 1976-03-26 1977-09-28 Hitachi Ltd Sampling controller
JPS59172990A (en) * 1983-03-19 1984-09-29 Yaskawa Electric Mfg Co Ltd Speed calculator in ac motor control

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63148881A (en) * 1986-12-12 1988-06-21 Fanuc Ltd Speed control device for servo motor
JPH01126185A (en) * 1987-11-09 1989-05-18 Matsushita Electric Ind Co Ltd Speed controller
JPH0614573A (en) * 1992-06-23 1994-01-21 Japan Radio Co Ltd Motor speed controller

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