JPS61131487A - Semiconductor nonvolatile memory - Google Patents
Semiconductor nonvolatile memoryInfo
- Publication number
- JPS61131487A JPS61131487A JP25261184A JP25261184A JPS61131487A JP S61131487 A JPS61131487 A JP S61131487A JP 25261184 A JP25261184 A JP 25261184A JP 25261184 A JP25261184 A JP 25261184A JP S61131487 A JPS61131487 A JP S61131487A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- film
- insulating film
- floating gate
- nonvolatile memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 230000008878 coupling Effects 0.000 claims abstract description 9
- 238000010168 coupling process Methods 0.000 claims abstract description 9
- 238000005859 coupling reaction Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 3
- 239000011229 interlayer Substances 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 38
- 230000014759 maintenance of location Effects 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 210000003127 knee Anatomy 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000001568 sexual effect Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、浮遊ゲート電極の電位を静電容量結合によシ
制御する制御ゲート電極が、浮遊ゲート電極の上に設け
られている半導体不揮発性メモリに関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor non-volatile device in which a control gate electrode for controlling the potential of a floating gate electrode by capacitive coupling is provided on the floating gate electrode. Regarding sexual memory.
従来の浮遊グー）Ｗ不揮発性メモリは、浮遊ゲート電極
と制御ゲート電極との間の静電容量結合用層間絶縁膜を
、多結晶シリコンである浮遊ゲート電極を熱酸化して形
成していた。In a conventional floating nonvolatile memory, an interlayer insulating film for capacitive coupling between a floating gate electrode and a control gate electrode is formed by thermally oxidizing a floating gate electrode made of polycrystalline silicon.
しかしながら、多結晶シリコンの熱酸化膜（以下単純に
熱酸化膜と略す）は、単結晶シリコンの熱酸化膜に比べ
て電流が流れ易く、ま念絶縁耐圧も低い。これらのこと
は浮遊ゲート型の不揮発性メモリにおいて、保持特性の
悪化および破壊にそれぞれつながる。すなわち制御ゲー
ト電極および浮遊ゲート電極間がリーキーであったり完
全に通電していたりすること忙よって浮遊ゲート電極に
閉じ込められていたキャリアが制御ゲート電極へ逃げ、
記憶内容が消えてしまう。熱酸化膜において電流を流れ
にくくシ、絶縁耐圧を上げるには膜厚を浮くすればよい
。しかしながら、膜厚と静電容量とは反比例の関係にあ
るため、膜厚を厚くすると容量が小さくなり、容、を結
合が弱くなって制御ゲート電極で浮遊ゲート電極の電位
を制御しにくくなる。However, a polycrystalline silicon thermal oxide film (hereinafter simply referred to as a thermal oxide film) allows current to flow more easily and has a lower dielectric breakdown voltage than a single crystal silicon thermal oxide film. These things lead to deterioration and destruction of retention characteristics, respectively, in a floating gate type nonvolatile memory. In other words, if there is a leaky connection between the control gate electrode and the floating gate electrode, or if the current is completely conductive, carriers trapped in the floating gate electrode escape to the control gate electrode.
Memory contents will be erased. It is difficult for current to flow in a thermal oxide film, and the dielectric strength can be increased by increasing the thickness of the film. However, since the film thickness and capacitance are inversely proportional, increasing the film thickness reduces the capacitance and weakens the coupling between the capacitance and the capacitance, making it difficult to control the potential of the floating gate electrode with the control gate electrode.
本発明は、上述のような従来技術の欠点を克服するため
、薄くても絶縁耐圧が高くリークの少ない膜を静電容量
結合用の膜として利用し、信頼性。In order to overcome the above-mentioned drawbacks of the prior art, the present invention utilizes a thin film with high dielectric strength and low leakage as a capacitive coupling film, thereby improving reliability.
保持特性の優れた不揮発性メモリをつくることを目的と
している。The aim is to create nonvolatile memory with excellent retention characteristics.
上述の問題点を解決するため、本発明では静電容量結合
用の絶縁膜として薄くしても（３ＧＯＡ以下にしても）
絶縁耐圧が高く、しかもトンネル電流特性が単結晶シリ
コンの熱酸化膜とほぼ、同じでリーク電流の非常に少な
い高温（７００℃以上）化学気相成長法による膜（以下
ＥＩＴＯ膜と略す）を利用した。In order to solve the above-mentioned problems, in the present invention, even if the insulating film for capacitance coupling is made thin (even if it is made thinner than 3 GOA).
Utilizes a high-temperature (700°C or higher) chemical vapor deposition film (hereinafter abbreviated as EITO film) that has high dielectric strength, tunnel current characteristics similar to those of single-crystal silicon thermal oxide films, and very low leakage current. did.
第１図から第５図に本発明による実施例を示す。 Embodiments according to the present invention are shown in FIGS. 1 to 5.
第１図はチャネル注入型、第２図はトンネル注入型およ
び第５図はＰＡＯＭＯ８ｍの不揮発性メモリである。ど
の構造も基本的には同様で、半導体基板１０表面近傍に
ソース領域２およびドレイン領域５が設けられており、
これら２つの領域に挾まれた基板１０表面上にゲー゛ト
絶縁膜４があシ、その上に浮遊ゲート電極５、その上Ｖ
ｃ［（Ｔｏ膜６、さらにその上に制御ゲート電極７がそ
れぞれ設けられ・ている。FIG. 1 shows a channel injection type, FIG. 2 shows a tunnel injection type, and FIG. 5 shows a PAOMO8m nonvolatile memory. All structures are basically the same, with a source region 2 and a drain region 5 provided near the surface of the semiconductor substrate 10.
A gate insulating film 4 is formed on the surface of the substrate 10 sandwiched between these two regions, a floating gate electrode 5 is formed on it, and a V
c[(To film 6, furthermore, control gate electrode 7 is provided on it.
ｇＴＯ膜６は、制御ゲート電極７で浮遊ゲート電極５の
電位を制御するときの容量結合用絶縁膜で、高温ＯＶＤ
法で形成されている。第１図から第５図には５ｓ類のメ
モリへの実施例を示したが、上述のごとく浮遊ゲート型
で、浮遊ゲート電極の電位を浮遊ゲート電極上に設けら
れた制御ゲート電極で制御するえイブのメモリであれば
本発明を適用することが可能である。The gTO film 6 is an insulating film for capacitive coupling when the potential of the floating gate electrode 5 is controlled by the control gate electrode 7, and is used in high-temperature OVD.
formed by law. 1 to 5 show an example of a 5S type memory, and as mentioned above, it is a floating gate type, and the potential of the floating gate electrode is controlled by a control gate electrode provided on the floating gate electrode. The present invention can be applied to any memory that is large in size.
次ＧＣＨＴＯ膜と熱酸化膜とのニー７特性および°゛、
８５０℃で形成した２４０＾のＨＴＯ膜のＩ −Ｖ特性
である。熱酸化膜の方が６倍程度厚いにもかかわらず低
電圧における電流は大きい。このことは、不揮発性メモ
１７ においてＨＴＯ膜の方が保持特性が優れているこ
とを示唆している。また、保持時間が同程度となるＨＴ
Ｏ膜と熱酸化膜では、両者の膜厚は１０倍以上異なって
くる。よって、容量結合はＨＴＯ膜の方が１０倍以上大
きくなり、制御ゲート電極７で浮遊ゲート電極５の電位
を制御し易くなる。これは逆に、制御ゲート電極７と浮
遊ゲート電極５０オーバーラツプ面積を狭くすることを
可能とし、設計時の冗長性が向上する。The following are the knee 7 characteristics of the GCHTO film and the thermal oxide film, and the IV characteristics of the 240^ HTO film formed at 850°C. Even though the thermal oxide film is about 6 times thicker, the current at low voltage is large. This suggests that the HTO film has better retention characteristics in nonvolatile memo 17. In addition, HT with the same retention time
The thickness of the O film and the thermal oxide film differs by more than 10 times. Therefore, the capacitive coupling is ten times or more greater in the HTO film, making it easier to control the potential of the floating gate electrode 5 with the control gate electrode 7. Conversely, this makes it possible to reduce the overlap area between the control gate electrode 7 and the floating gate electrode 50, thereby improving redundancy during design.
第５図は第４図と同じ試料に対する絶縁耐圧分布である
。ＨＴＯ膜は分布が高電界に集中しているのに対し、熱
酸化膜はＯＭ Ｖ ／ ａ付近の絶縁破壊がみられる。FIG. 5 shows the dielectric strength distribution for the same sample as FIG. 4. The HTO film has a distribution concentrated in high electric fields, whereas the thermal oxide film shows dielectric breakdown near OMV/a.
これはピンホールであり、眉間絶縁膜にピンホールが存
在すると浮遊ゲート電極５と制御ゲート電極７とが導通
するためメモリとしての記憶能力が失われる。すなわち
、実際の製造においてＨＴＯ膜を使用した場合の歩留は
、熱酸化膜を使用した場合よりも高くなることが予想さ
れる。This is a pinhole, and if a pinhole exists in the glabellar insulating film, the floating gate electrode 5 and the control gate electrode 7 will be electrically connected, resulting in a loss of storage ability as a memory. That is, it is expected that the yield when using an HTO film in actual manufacturing is higher than when using a thermal oxide film.
本発明は以上説明したように、浮遊ゲート電極と制御ゲ
ート電極との眉間絶縁膜としてＨＴ（＞膜を使用するこ
とＫよりて不揮発性メモリの信頼性、保持特性および歩
留の向上させる効果がある。As explained above, the present invention has the effect of improving the reliability, retention characteristics, and yield of nonvolatile memory by using the HT film as the glabellar insulating film between the floating gate electrode and the control gate electrode. be.
しかも絶縁膜厚をうす（できるので、小さな制御電極電
圧でメモリ特性のコントロールが可能となり、デバイス
特性の向上にも効果がある。Moreover, since the insulating film thickness can be thinned, memory characteristics can be controlled with a small control electrode voltage, which is also effective in improving device characteristics.
第１図は本発明Ｋかかる半導体不揮発性メモリの第１実
施例の断面図、第２図は本発明にかかる半導体不揮発性
メモリの第２実施例の断面図、第３図は本発明Ｋかかる
半導体不揮発性メモリの第３実施例の断面図、第４図は
多結晶シリコンの熱酸化膜とＨＴＯ膜のＩ−Ｖ特性を示
す図、第５図は多結晶シリコンの熱酸化膜とＨＴＯ膜の
絶縁耐圧分布を示す図である。
５・・・浮遊ゲート電極
６・・・ＨＴＯ膜
７・・・制御ゲート電極
以上
出願人 新技術開発事業団 他２名
第１図
第４図
Ｍ、凪 Ｍ
第５図
電界ｔＭＶρｍｌFIG. 1 is a cross-sectional view of a first embodiment of a semiconductor non-volatile memory according to the present invention, FIG. 2 is a cross-sectional view of a second embodiment of a semiconductor non-volatile memory according to the present invention, and FIG. 3 is a cross-sectional view of a semiconductor non-volatile memory according to the present invention. A cross-sectional view of the third embodiment of the semiconductor non-volatile memory, FIG. 4 is a diagram showing the I-V characteristics of a polycrystalline silicon thermal oxide film and an HTO film, and FIG. 5 is a diagram showing a polycrystalline silicon thermal oxide film and an HTO film. FIG. 5... Floating gate electrode 6... HTO film 7... Control gate electrode and above Applicant New Technology Development Corporation and 2 others Figure 1 Figure 4 M, Nagi M Figure 5 Electric field tMVρml
Claims (1)
の絶縁膜上に設けられた浮遊ゲート電極と、前記浮遊ゲ
ート電極上に設けられた第２の絶縁膜と、前記第２の絶
縁膜上に設けられ前記第２の絶縁膜を誘電体とする静電
容量結合により前記浮遊ゲート電極の電位を制御するた
めの制御ゲートとから少なくとも構成される半導体不揮
発性メモリにおいて、前記第２の絶縁膜が７００℃以上
の高温で化学気相成長法により形成されていることを特
徴とする半導体不揮発性メモリ。a first insulating film provided on a semiconductor substrate;
a floating gate electrode provided on an insulating film; a second insulating film provided on the floating gate electrode; and a floating gate electrode provided on the second insulating film, the second insulating film being a dielectric. In a semiconductor nonvolatile memory comprising at least a control gate for controlling the potential of the floating gate electrode by capacitive coupling, the second insulating film is formed by chemical vapor deposition at a high temperature of 700° C. or higher. A semiconductor nonvolatile memory characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25261184A JPS61131487A (en) | 1984-11-29 | 1984-11-29 | Semiconductor nonvolatile memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25261184A JPS61131487A (en) | 1984-11-29 | 1984-11-29 | Semiconductor nonvolatile memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61131487A true JPS61131487A (en) | 1986-06-19 |
Family
ID=17239775
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25261184A Pending JPS61131487A (en) | 1984-11-29 | 1984-11-29 | Semiconductor nonvolatile memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61131487A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6317544A (en) * | 1986-07-10 | 1988-01-25 | Seiko Instr & Electronics Ltd | Semiconductor device |
| JPH01233772A (en) * | 1988-03-14 | 1989-09-19 | Seiko Instr & Electron Ltd | Manufacture of semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59124168A (en) * | 1982-12-28 | 1984-07-18 | Seiko Instr & Electronics Ltd | Nonvolatile semiconductor memory |
-
1984
- 1984-11-29 JP JP25261184A patent/JPS61131487A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59124168A (en) * | 1982-12-28 | 1984-07-18 | Seiko Instr & Electronics Ltd | Nonvolatile semiconductor memory |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6317544A (en) * | 1986-07-10 | 1988-01-25 | Seiko Instr & Electronics Ltd | Semiconductor device |
| JPH01233772A (en) * | 1988-03-14 | 1989-09-19 | Seiko Instr & Electron Ltd | Manufacture of semiconductor device |
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