JPS61128376A - Image memory controlling device - Google Patents

Abstract

PURPOSE:To move a horizontal image in each dot by fixing mutual timing relation between specific operations and shifting these timing from the display start timing fixed in the horizontal direction in each period of a display clock. CONSTITUTION:The mutual timing relation between the updating timing of a counted output of a horizontal counter 15 and the load timing of drawn data is fixed and these timing are shifted from the display start timing fixed in the horizontal direction in accordance with the moved distance of a displayed image within the range of 1-4 display clocks to move the image in each dot of the horizontal direction. In said constitution, a latch circuit for holding read data for the period of 4 display clocks can be omitted, and it is unnecessary to increase the size of a circuit even if the number of dots for parallel processing or the number of bits per dot is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an image memory control device in an image communication system such as a teletext system. and,
In particular, the present invention relates to an improvement in a structure for reading data from an image memory for giving a motion expression to a displayed image.

[Technical background of the invention]

In the teletext system, there is an image display function called a move function. This move function gives movement to the displayed image by shifting the display position of the image in the image display area on the display screen.

FIG. 7 shows a conventional image memory control device equipped with the above-described advanced move function.

In the figure, 11 is an image memory. This image memory 11 consists of four RAMs 111-114.

Now, as an image display area on the display screen, consider an image display area M8 consisting of 248 dots in the horizontal direction and 192 lines in the vertical direction as shown in FIG. In this case, image memo +
7 z J The storage of drawing data for VC is as follows. That is, 2 of each horizontal scan line in FIG.
The 48 dots are divided into 62 blocks 80 to B, 8 each having four consecutive dots. Each professional, RiB! 1 (0≦
If the drawing data of four dots (n≦61) is radial~d, the first drawing data a is stored in RAM J J Jn.

n, the next drawing data b
n is in RAM l l 2, the next drawing WIJf”/
e The final drawing data dn is stored in the RAM 113.
114K is stored. In other words, the position of the dot at the lower left end of the image display area M'ft is the origin (0, 0
), the drawing data of a dot represented by the coordinate value 4n on the X coordinate (horizontal coordinate) is stored in the RAM 111IC. Similarly 4m+1
The drawing data of the dots represented by the X coordinate value of "H+2"n-t4 are stored in RAM1 i jp 113 respectively.
-114.

When reading out drawing data for image display from the image memory 1 in which the drawing data is stored in this way, the four steps of each program and RiB.

Drawing data a~d! l is read out at once.

That is, the horizontal data read address assigned to each RAM 711-114 is the same. now,
For convenience of explanation, the horizontal data read address is n
Then, each block B! 104 data'n""t
are stored at addresses n of the corresponding RAMs 111 to 114, respectively.

So, for example, if n=O, the first block B
The first drawing data a in , is read from address O of the RAM 111. Similarly, drawing data b*mcos
ae is read from address O of the RAMs 112, 113, and 114, respectively.

In this way, the drawing data for four parts read out simultaneously from the image memory 11 is loaded into the parallel/serial conversion circuit (P/5) 13 via the child circuit 12. Then, one dot at a time is read out from this parallel/serial conversion circuit 13 in accordance with the raster scan display clock CP.

This read drawing data is given to a display drive circuit (not shown) via an AND circuit 14, and an image is displayed.

The reason why the image memory 11 is composed of four RAMs 111 to 114 and the drawing data is read out for four dots at a time is to make the reading of the drawing data compatible with the rasp scan V. That is, the cycle time of the image memory 11 is slower than the scan timing of raster scan. If the horizontal data read address is changed by one and the drawing data is read out while one dot is being displayed, the drawing data will not be read out in time for the raster scan. By setting the update cycle of the data read address in the direction to four times the rate when reading the drawing data in units of one dot, the reading of the drawing data is made compatible with raster scanning. Generally, this can be obtained by setting the update period of the horizontal data read address to a divisor multiple of the number of horizontal dots, excluding l, such as twice or eight times the rate when reading drawing data in units of one dot. It is something that can be done.

A data read address in the horizontal direction is output from the counter 15. A data read address in the vertical direction is output from the counter 16.

The output of counter 15.1g is each selected by selector 17.1.
11 to the image memory 1.

Here, the move function will be explained. The horizontal counter 15 is a seven-stage up counter that can be preset. The vertical color/reverse 16 is a nine-stage down counter that can be preset. Therefore, counter 15,1
By appropriately setting the Griset and G values of 6, it is possible to move the displayed image in the horizontal and vertical directions.

In this case, since the horizontal counter 15 updates the data read address on a block-by-block basis, by changing the glisset value of this counter 15, the displayed image can be moved on a block-by-block basis. The movement of the displayed image dot by dot is performed by the parallel/serial conversion circuit 13.
This is done by changing the load timing of read data from the image memory 11 relative to the image memory 11. Therefore, in FIG. 7, only one drawing data read out from the image memory 11 is shown.

The data is latched into the child circuit 12 and then loaded into the parallel/serial conversion circuit 13 according to a load timing determined according to the amount of horizontal movement of the displayed image.

Note that the vertical counter 16 is in units of lines.

This updates the data read address. Therefore, if you change the grisset value of this counter 16,
The displayed image can be moved line by line.

The gliset values of the counters 15 and 16 and the load timing of the read data to the parallel/serial conversion circuit 13 are determined according to the amount of movement of the display image. The data specifying the timing (hereinafter referred to as bias data) is provided by MicroGrosse (hereinafter referred to as MPTJ) (not shown).
is output onto the address/data bus 19. This bias data consists of horizontal direction bias data B and vertical direction bias data VB. In addition, each bias data HB, VB is binary data of 9c, t, and corresponds one-to-one to the X-coordinate value and Y-coordinate value of the above-mentioned X-Y coordinates, respectively. This indicates a state in which the displayed image is not moved. In this case, the horizontal bias data HB is set to "0" in decimal notation, and the vertical bias data VB
is set to 191 in decimal.

Figures 1 to 13 show cases in which the displayed image is moved. In the figure, M indicated by a broken line is a display image. As shown in FIGS. 10 and 11, the display image M8
When moving to the left in the horizontal direction, the horizontal bias data HB is set to satisfy HB ) O in decimal notation.

Conversely, as shown in FIGS. 12 and 13, 1. When moving to the right in the horizontal direction, bias data I (B is HB (0
is set to satisfy. Regarding the vertical direction, when moving downward as shown in FIGS. 10 and 12, the bias data VB is set to satisfy VB)191 in decimal notation. Conversely, when moving it upward, it is set to VB (191) as shown in FIGS. 11 and 13.

Here, a specific example of the move operation will be explained. FIG. 14 shows a timing diagram when moving the display image M by 2 bits to the left in the horizontal direction.

In this case, the horizontal direction bias data HB output from the MPU is 9-bit binary data that is 2 in decimal notation. Also, the vertical bias data VB is 1
This is 9-bit binary data, which is 191 in 0-base.

Upper 7 bits of horizontal bias data HB, tn, ~
HB is loaded into the latch circuit 20 at the timing of pulse L8. The upper 7 bits HB, to l express the read address in the horizontal direction in units of 4 dots. Also, all the vertical bias data VB, )VB, ~V
B is applied to the child circuit 21 at the timing of I4 pulse L. The lower two pins of horizontal bias data HB, ) HBs + HJ are D-flo and f-flo, respectively.

given as input to the programming circuit zx, x3'ltc,
The data of the D flip 70 and the latch circuits 22 and 23 are clocked at the timing of the pulse L1, and the data of the latch circuit 20 is clocked at the timing of the fall of the preset pulse XPR (see FIG. 14(c)). 15, it was canceled. /4 Lus ℃1 is horizontal display goo indicating the horizontal display start timing) /41 Lus HP (1st
It is output eight times earlier than the rising timing of CP (see Fig. 14 (,)) in the display black and ri CP (see Fig. 14 (,)). It's Luz. Here, A Luss XPR.

The timing relationship between pulse strikes is fixed.

The latch data of the latch circuit 21 is preset in the counter 16 by a pulse YP indicating the display start timing in the vertical direction.

The pulse °C1 is further provided as input data to the shift register 25 via the OR circuit 24. The shift register 25 is a four-stage register, and shifts input data at the rising timing of the display clock CP. After the shift register 25 shifts the Noculus xPR by four stages (L, , H), the shift register 25 continues the shift operation using the output Q of the fourth stage as input data. From the above, the shift register 250 has four outputs Q.~Qs! 'lre ('re display black, ri Each time 4 CP is generated, display black, ri c
One occurrence occurs with the phase shifted by one period of p. The four outputs of the shift register 250 are shown in FIG. 14(d).

The horizontal counter 15 counts up by 1 at the falling edge of the output Q of the 04th stage of the SHITON NOSTAR. Therefore, the data read address in the horizontal direction is updated by one every time four display blacks and reds occur. The count outputs Q, ~Q, of the counter 15 are
This is shown in Figure 4(f). The upper 7 bits of the horizontal bias data HB are preset in the counter 15, so at the timing of the fall of Noyals XPR, the count output of the counter 15 is << as shown in FIG. 14(f).
, is ``O'' in decimal notation.

The vertical counter 16 counts down by one at the rising edge of the horizontal synchronization signal. Therefore, one vertical data read address is updated every horizontal scanning period.

Using the data read address obtained in this way, 1e of drawing data for 4 dots is read from the image memory 11.
is read out. These four parallel data are generated at the timing of the rise of the output Qa of the fourth stage of the shift register 250.

It is latched in the child circuit 12, and is latched in this latch circuit 12 over four periods of display black and red CP. Therefore, in each horizontal scanning period, the four drawing data a0 to b0 corresponding to the leading pro, riB, are displayed from the rising timing of the horizontal display r-) pulse XPR, as shown in FIG. The signal is latched by the latch circuit 12 four cycles ago at the CP. Thereafter, the data in the latch circuit 12 is updated in units of programs every four display clocks CP.

The data of the child circuit 12 is a load pulse LD given from the selector 26 via the inverter circuit 27.
It is loaded into the parallel/serial conversion circuit 13 at the timing of . The data loaded into the parallel/serial conversion circuit 13 is converted into serial data by being read out one dot at a time according to the display black and red CP. In order to read out all the load data, this parallel/serial conversion circuit 13 requires four periods of display black and red CP. Therefore, the data read address output from the counter 15 is the display clock CP as described above.
It is updated once every four cycles.

Here, the generation of the load pulse LD will be explained.

The selector 26 is connected to the D7 logic circuit 22.2.
According to the Q output and the Q output of 3, the shift register 250
Select one of the four outputs Q, ~Q. This selection output is inverted by an inverter circuit 27 and becomes a load/dulse LD.

The Q output and Q output of the D-Furi, Pflo, and Pf circuits 22 and 23 are the lower two bits of the horizontal bias data HB, respectively.
Determined by the contents of HB, , HBl. Therefore, the selection contents of the selector 26 are also the lower two pits H.
It is determined by the contents of B, , and HB. The selection contents are organized into buttons as shown in Table 1 below.

Table 1 In this case, the horizontal bias data line is 2 in decimal
Therefore, HB, =Q, I'LB, , = 1
becomes. Therefore, the selector 26 selects the shift shift and the first stage output q of the Nostar 25. As a result, the load pulse LD is horizontally displayed r as shown in FIG.
-) Display black from the rising timing of pulse P,
It is output three cycles earlier in the CP. At the timing of the rise of this rotor 4 pulse LD, the child circuit 12
data is loaded into the parallel/serial conversion circuit 13. Therefore, the parallel/serial conversion operation of the drawing data is started two cycles before the rising timing of the horizontal display dart/fourth pulse HP in the display black and ri CP. As a result, as shown in FIG. 14(h) IC, in each horizontal scanning period, the drawing data a@, b@ for the first 2 bits and 9 bits of the leading program B6 are discarded, and the drawing data a@, b@ of the first 2 bits, Drawing data c0 from the eyes passes through the AND circuit 14 and is applied to the display drive circuit. As a result, the displayed image M is moved two degrees to the left in the horizontal direction.

Next, the display image M is moved to the right side Vc5 in the horizontal direction.

The case of moving by the distance will be explained with reference to FIG. 15.

In this case, the horizontal bias data flIB is 10
This is binary data that is -5 in decimal.

If bias data HB, YB are negative, these are 2
is expressed in complement form. Therefore, the count outputs Q0 to Q of the horizontal counter 15 are delayed by one cycle of the display clock CP from the rising timing of the horizontal display 5a, )/#rus P, as shown in FIG. 15(f). Decimal numbers are OK.

As a result, the drawing data a corresponding to the first pro, RiBo
, ~d, as shown in Fig. 15G) VC, the horizontal display f
-) There is a delay of 4 cycles in the display clock CP from the rising timing of z#rus HP.
be touched.

Also, because the bias data HB is expressed using two's complement, the lower two y
) HB@HHJ are both 1. Therefore, as is clear from Table 1 above, the selector 26 selects the output Q of the third stage of the shift register 250. Therefore, as shown in FIG. 14(h), the four drawing data a, to d, corresponding to the first block B, are delayed by five cycles in the display black and CP from the rising timing of the horizontal display Gutnors HP. , are read out one pit at a time from the parallel ZvX column conversion circuit 13.

As a result, the displayed image M is moved to the right in the horizontal direction by 5 pits.

In this way, in the circuit shown in Fig. g7, by changing the grisset value of the counter 15, the display image M8 can be moved in the horizontal direction in steps of 300 degrees. As a result, the displayed image is moved dot by dot in the horizontal direction. Here, the reason why the latch circuit 12 holds the read data of the image memory 11 for four cycles of the display clock CP is that during these four display clock periods, the shift register 250 has four outputs Q, -Q, This is to select one of them as the Rohtonorth LD.

and ζ, the display image M is displayed as shown in FIG.

When moving 5 dots to the right in the horizontal direction, an area of 5 dots from the left end of the image display area M8 is an extra area for display. Therefore, this area must be made transparent and not visible. This processing is performed by the transparent dirt signal generation circuit 28.

! FIG. 16 shows the configuration of the transparent y-t signal generating circuit 28.

FIG. 17 is a timing chart showing the operation of the transparent r-) signal generating circuit 28 when the displayed image is moved horizontally to the right by 5 r.

The NAND circuit 281 in FIG. 16 receives count outputs from the horizontal counter 15 at the 2nd bit, the 4th bit Q, to the 6th bit, the 6th bit Qai.

Therefore, if the count output of the counter 15 is a decimal number other than 62.63, the output of the NAND circuit 281 is OUT,
is 1.

Further, the most significant bit Q of the counter 15 is inputted to the inverter circuit 282VC. The most significant bit q becomes O when all outputs of the counter 15 reach 60'. At this time, the preceding block B, 04 drawing data a, to d, corresponding to the horizontal data read address O in decimal notation are read out.

Output OUT of inverter circuit 282, and NAND circuit 2
The output OUT of 81 is input to an AND circuit 283.

The output OUT of the AND circuit 283 is the inverter circuit 28
The output OUT of the signal D7 is latched by the gate pull circuit 285. This inverter circuit 284 is for inverting the output Qyo of the third stage of the shift resolver 250.

Therefore, D-Fri, Pu70. Q output O of the programming circuit 285
UT.

becomes 1 at the 05th dot in the image display area M, as shown in FIG. This Q output OUT is load/4 pulse LD
D-free, f70. The signal is input to the f circuit 286. Therefore, the Q output OU of the %D71J frog circuit 286
T, as shown in FIG. 17, is the image display area M106
This Q output OUT, which becomes 1 at the dot, becomes a transparent dart signal and is applied to the AND circuit 14 in FIG.

Therefore, an area of 5 dots and 500 g from the left end of the image display area M1 is displayed transparently.

In addition, in this case, the output otrr of the ant 0 circuit 283,
D flip-flop circuit 2 with wam load pulses L and D
The same transparent dirt signal can be obtained by latching 1j5Vc. However, as shown by the dotted line in the load/4rus LD, 1
If the display black is delayed by CP, the transparent r-) signal will be obtained by adding the extra four dots. Therefore, the D flip-flop circuit 284 is required to prevent r-to such extra bits.

Next, move the display image M to the left side in the horizontal direction by 7 degrees.

The case of moving the object will be explained with reference to FIG. 18. The period in which the output OUT□ of the NAND circuit 28 is O is when the count value of the horizontal counter 150 is 62.63. Also, when the horizontal counter 15 counts 64, the 7th bit becomes 1, so the inverter circuit 2
The output OUT of 82 becomes 0 as shown in FIG. By inputting the output OUT 1 of the NAND circuit 281 and the output OUT of the inverter circuit 282 to the AND circuit 283, the NAND circuit 28 is output from the AND circuit 283.
Output OUT of 1, output OUT that becomes 0 at the falling edge of
, is obtained. This output OUT is the output OUT of the inverter circuit 284, and the D7 lip-frog circuit 28
5.I'm busy doing things, so display image M.

From the terminal end of the display, an output OUT is obtained which becomes 0 one cycle before CP. By applying this output OUT to the D flip-flop circuit 286 with a load pulse LD, the transparent f-) becomes 0 at the end of the display image Ml.
I get a signal.

In this case as well, the output of the AND circuit 283 is connected to the load pulse L
If you latch with D, D 717, book.

The same output as the output OUT of the decircuit 286 is obtained.

However, if the load/4th pulse LD is output with a delay of 1 display black as shown by the dotted line.

The transparent r-) signal is r-
)Can not do it. Therefore, it can be seen that the output of the AND circuit 283 must be latched into the D-flip, pflo, / circuit 285 with the output of the digitizer circuit 284.

That is, D7'Jy gua 0. The switching circuit 285 has the role of shifting the phase of the output OUT of the AND circuit 283 to generate a transparent r-) signal at a predetermined position. There is a latch circuit 12. This latch circuit 12 is connected to the image memory 11
This is for outputting the parallel data of
is a circuit involved in writing drawing data into the image memory 11. Here, the data writing process will be briefly explained.

This data writing process is performed by the MPU during a period other than the image display period, for example, during a blanking period. First, a data write address is outputted onto the address/data bus 19 by the MPU, and the horizontal address is given to the selector 11 and the vertical address is given to the selector 18.

Selector 17. Ill selects the data write address from the MPU during the blanking period according to the control signal BS, and selects the count output of the counters 15 and 16 as the data read address during the other periods. Similarly to the data read address, the data write address in this case also accesses the RAMs 111 to 114 simultaneously.

Is the drawing data passed through the address/data path 19? - to the gate circuit 29. When the enable signal EN is input, the e-) circuit 29 opens the dart and supplies the input data to the four RAMs 111 to 114 of the image memory 11.

It is determined in accordance with the output of the decoder 30 which of the four RAMs J 11 to 114 the drawing data is written to.
That is, when the decoder 30 is given the write timing/4 pulses, it generates any one of the four write permission pulses W, ~W, according to the write light instruction data MSic, and applies it to the corresponding RAM. . Then, the RAM K drawing data to which the write permission pulse has been applied is written.

[Problems with background technology]

As explained above, in the conventional image memory control device for the move function, when performing parallel/serial conversion of the drawing data read out from the image memory 11 and when generating the transparent 11'-) signal, etc. A latch circuit 12 is required for bit alignment. Therefore, when the number of parallel processing dots increases (when the frequency of display black and (due to an increase in gradation, etc.), or when a signal similar to a transparent ff-) signal increases, etc.
-The increase in hardware will be enormous. [Objective of the Invention] This invention was made to deal with the above situation, and even if there is an increase in the number of parallel processing dots, the hardware will be significantly increased. An object of the present invention is to provide an image memory control device that can execute move processing without having to do so.

[Summary of the invention]

This invention fixes the mutual timing relationship between the update timing of the horizontal data read address and the load timing of the drawing data read from the image memory, and sets these timings relative to the fixed display start timing in the horizontal direction. By making it possible to shift in units of one cycle of the display/indication clock for raster scan according to the amount of horizontal movement of the display image, it is possible to move the display image in units of one dot or g in the horizontal direction. It is configured to do so.

[Embodiments of the invention]

Hereinafter, the present invention will be described in detail with reference to the drawings.

Figure K1 is a circuit diagram showing the configuration of an embodiment of the present invention. In FIG. 1, the same parts as in FIG. 7 are given the same reference numerals.

The difference in FIG. 1) ζ from the previous diagram wE7 is the preset timing of the latch data of the child circuit 20 for the horizontal counter 15)C.

Update timing of color/re 150 count output, and parallel/serial conversion circuit 23! 'l: The relative timing relationship between the three timings of loading the read data from the image memory 1 is fixed, and these three timings are fixed.
This timing can be shifted in units of one cycle of the display CP with respect to the fixed display start timing in the horizontal direction.

That is, the preset Hals XPR is given as input data to the three-stage shift register 35, and the display clock
shifted according to P. The outputs Q, .about.Q of the third stage of the shift register 350 and the delete pulse XPR are inputted to the selector 36VC.

The selector 36 selects one of four input clocks whose phase is shifted by one cycle of the display clock CP. Which one to select depends on the lower two bits of the horizontal bias data plate output from the MPU, HB, , H.
The output content is determined by the content of B, D7, and differential 0.
It is determined according to the outputs of f circuits 22 and 23.

The selection output Q of this selector 36 is the counter 1 in the horizontal direction.
5's delice becomes the tonogurusu, and the latch circuit 20,
The current data is input to the counter 15. Further, the selection output Q of the selector 36 is given as input data to a four-stage shift register 38 via an OR circuit 32, and is shifted accordingly. After this shift register 38 finishes shifting the selected output Q of the selector 36, it continues the shifting operation by using the fourth stage output Q as input data.

The output Q3 of the fourth stage of the shift register 380 is given to the horizontal counter 15 as a counting clock. Therefore, the counter 15 starts counting four display clocks after the data of the child circuit 20 is preset, and advances the count every four display clocks. Note that the vertical counter 16 operates in the same manner as in FIG. 7 above.

The fourth stage output Q of the shift register 38 is further inverted by an inverter circuit 39VC. This inverted output is the load/
The signal is applied to the parallel/serial conversion circuit 13 as a 4-channel LD.

Movement amount of display image M and bias data HB.

The relationship between VB and VB is the same as that explained in FIGS. 9 to 13 above, and the method of setting the bias data HB and VB is also the same as before.

Horizontal bias data) Lower 2 pits of IB! 'I
, , HB, and the selection contents of the selector 36 are shown in Table 2 below.

Table 2 Here, we will give a specific example of the amount of movement of the display image M.
The operation of the diagram will be explained. First, a case in which the display image M□ is moved two dots to the left in the horizontal direction will be described with reference to FIG. In this case, horizontal bias data I (lower two pins of B,) HB.

HB is each 0.1. Therefore, as is clear from Table 2, the selector 36 selects the first stage output Q of the shift register 35, as shown in FIG.

At the timing of the fall of the first stage output, the counter 15 receives a signal as shown in FIG.

This counter 15 is the fourth stage output Q of the shift register 38.
, (see Figure 82(f)).
Count one by one for each CP displayed.

Counter 15 is preset in decimal format.
As shown in FIG. 2 (0), the drawing data a, to d for the first four characters, B, and B, are read out from the image memory 11. The drawing data a to d are stored in the shift register 38. Since the parallel/serial conversion circuit 13Vc is loaded at the timing of the rise of the rotor pulse LD obtained by inverting the fourth stage output Q, by the inverter circuit 39, the parallel/serial conversion circuit 13Vc is loaded. /Serial conversion is executed from 2 display clocks 02 minutes before the display start timing in the horizontal direction. Therefore, the image display is as follows:
The first two drawing data 'O1b++ are discarded, and 3
This is done from the th drawing data c0. As a result, an image is displayed in which the display image M is moved to the left side in the horizontal direction by 2 dots and t.

Note that if the horizontal direction bias data HB is set to 3 in decimal notation, the lower two pits of this bias data HB)
Since HB, , and HB are 1 and 1, respectively, the selector 36 selects preset/4rus XPR. Therefore, parallel/serial conversion starts 3 display clocks cp before the horizontal display start timing, and
The image is displayed starting from the fourth drawing data d.

In other words, the display image M8 is displayed by being moved to the left in the horizontal direction by three dots.

Similarly, if tB (1 bias data) is set to 0°1 in decimal notation, the selected output Q of the selector 36 becomes the third stage output Q2 and the second stage output Q of the shift register 350, respectively, and the displayed image M is completely An image is displayed without being moved, and an image is displayed with the display image M1 moved one dot to the left in the horizontal direction.

Next, a case will be described in which the display image *M is moved five degrees to the right in the horizontal direction with reference to FIG.

In this case, the horizontal direction bias data HE is set to -5 in decimal notation. Since this is expressed in this complement format, the lower two bits of the bias data HB are HBe ”
1 * HB 1 person becomes 1. Therefore, the selection output Q of the selector 36 becomes Preset/4 Lus C1, as shown in FIG. 3 (@). In addition, the count output of the counter 15 becomes 0 in decimal form after one display clock CP from the horizontal display start timing, as shown in FIG. 3(h) Vc. Therefore, the drawing data read out from the image memory 1 becomes as shown in FIG. As a result, the displayed image M is moved to the right in the horizontal direction by five degrees, as shown in FIG. 3(j).

Next, the operation of the transparent dirt signal generation circuit 40 will be explained.

FIG. 4 is a circuit diagram showing a specific configuration of the transparent dirt signal generating circuit 40. As shown in FIG. The difference between FIG. 4 and FIG. 16 is that the D-flip and Pflode circuits 285 required for shifting the phase in FIG. 16 are not required.

Here, first, the transparent r-) process when moving the display image M to the right side in the horizontal direction by 5 dots will be explained with reference to FIG.

The output OUT 1 of the NAND circuit 401 in FIG.
It is. In the inverter circuit 402, the 7 of the counter 15
The stage output is input. This inverter circuit 402
The output OUT of the counter 150 count output is 0.
When it becomes , it changes to 1 as shown in FIG. now,
Since the output OUT of the NAND circuit 401 is 1, the output OUT of the inverter circuit 402 passes through the ``1t AND circuit 403.
UT, the D flip-flop circuit 404 is turned on by the output OUT of the inverter circuit 39 (same as LD) which inverts the fourth stage output Q1 of the 7th tracer 38.

Image display starts four display cycles after the output of the counter 15 reaches '0'.

In other words, the output of the inverter circuit 402 is I
When it reaches Vc, it means that image display starts after 4 display blacks and CP. 'The output OUT of the inverter circuit 39 rises 4 display clocks after the output OUT of the inverter circuit 402 becomes 1,
By connecting the output OUT of the AND circuit 403 to the D flip-flop circuit Io4, the Q output OUT of the D flip-flop circuit 404 rises in synchronization with the start of image display. . If this Q output OUT is input to the AND circuit 14 as a transparent signal, image display can be prohibited in an area of 5 dots from the left end of the image display area M8.

Next, move the display image M to the left side in the horizontal direction by 7 degrees.

The transparent r-) processing in the case of moving by the distance will be explained with reference to FIG. The output OUT of the NAND circuit 401 is O
During the period, the count output of the horizontal counter 15 is 1.
This is 62.63 in 0-decimal notation. When the count output of this counter 15 reaches 64, its seventh stage output Q1 becomes 1.
becomes.

Therefore, the output OUT 2 of the inverter circuit 402 becomes 0 when the count output of the counter 15 reaches 64.

Output OUT of NAND circuit 401 and inverter circuit 4
The output OUT of the AND circuit 403 to which the output OUT of 02 is input is 150 count output of the counter 621
When it becomes C, it becomes O. Output OU of AND circuit 403
The falling edge of T is the output OUT of the inverter circuit 39,
Because it is slightly delayed from the rise of D-furi, f70. f
Since the Q output OUT of the circuit 404 becomes 0, the Q output OUT of the AND circuit 403 becomes 0.
After P, it becomes O.

As a result, D7, the Q output of the Pfrodde circuit 404
UT becomes O after the display of the final program Lt is completed, and image display in an area of 7 degrees from the right end of the image display area M is prohibited.

In Figures 5 and 6, each output OUT, ~OUT
, are fixed, and the transparent f-) processing is performed by shifting the phase of these with respect to the horizontal display start timing according to the horizontal bias data HB. Therefore, as before, D-free.

There is no need to shift the phase of the output of the AND circuit 403 using the Pflo and f circuits.

As detailed above, in this embodiment, the update timing of the horizontal counter 150 count output and the image memory 1
The mutual timing relationship between the load timings of the drawing data read out from 1 is fixed, and these timings are changed from 1 to 4 display clocks with respect to the fixed horizontal display start timing depending on the amount of movement of the display image M. By shifting the image within a range of , it is possible to move the image in dot units in the horizontal direction.

According to such a configuration, as in the conventional case where the update timing of the count output of the counter 15 is fixed and the load timing of read data from the image memory 11 is made variable, in order to determine the phase of the load timing,
The latch circuit 12 that holds the read data for four display clock periods becomes unnecessary. As a result, even if the number of parallel processing dots or the number of bits per dot or dot increases, the circuit scale does not increase.

In this embodiment, the latch circuit 12 is not required, but a shift register 35 is required to obtain the update timing and load timing of the count output having four types of phases. However, this shift register 350 circuit configuration is not related to the number of dots of drawing data, so it is difficult to perform parallel processing.

Even if the number of chips increases, the circuit scale does not increase much, and 1
If the number of dots per dot only increases, the total circuit size remains unchanged.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and can be implemented in various other ways.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide an image memory control device that can execute move processing without significantly increasing the hardware even if the number of parallel processing increases.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention, and FIG.
3 is a timing chart for explaining the move process in the device shown in FIG. 1, and FIG. 4 is a circuit diagram showing an example of a specific configuration of a transparent dirt signal generation circuit in the device shown in FIG. , FIGS. 5 and 6 are timing charts for explaining the transparent dart processing of the circuit in FIG. 4, FIG. 7 is a circuit diagram showing the configuration of a conventional image memory control device with a move function, and FIG. The figures are diagrams for explaining access to drawing data in the image memory shown in Figure 7, Figures 9 to 13 are diagrams for explaining movement of a display image in relation to the image display area, Figure M14, Figure 15 shows the layout of Figure 7.
FIG. 16 is a circuit diagram showing an example of a specific configuration of the transparent r-) signal generating circuit in the device shown in FIG. 7, and FIGS. 17 and 18 16 is a timing chart for explaining the transparent r-) process of the circuit of FIG. 16. FIG. 1 No... Image memory, J3... Serial/parallel conversion circuit, 14... AND circuit, 15.16... Counter,
17, Ill...Selector, 19...Address/data bus; tO, zl...Latch circuit, :12,2
3,,, D 7s, 7s70. programming circuit, 29... dirt circuit ~ 30... decoder, 35.38... shift register, 36... selector, 32... OR circuit, 39... inverter circuit, 40... transparent ff-)
Signal generation circuit. Applicant's representative Patent attorney Takehiko Suzue Figure 5 0UTs Figure 6 HP. = UTs Fig. 17 0tJT6 +++--1 Fig. 18 0LJT4 'L-Choichi-Koro-ko "''''---L-
L-J QLIT6−−−−−″−−−−1 L−＋＋＋＋＋＋＋−＋＋ Translation

Claims (1)

[Scope of Claims] An image memory in which drawing data is accessed by horizontal and vertical addresses corresponding to horizontal and vertical coordinates on an image display area, and a plurality of dot units continuous on a horizontal scanning line from this image memory. a data read address generation means for generating a data read address for reading out the drawing data; and a plurality of drawing data simultaneously read from the image memory are loaded in accordance with the data read address outputted from the data read address generation means. , a parallel/serial conversion means for outputting the plurality of loaded drawing data one dot at a time according to a display clock for raster scanning, and reading out the data according to the amount of horizontal movement of the display image on the image display area. Initial value setting means for setting an initial value in the horizontal direction of the address generation means; Mutual timing between the horizontal address update timing of the data read address generation means and the load timing of the read data to the parallel/serial conversion means. timing shifting means capable of shifting these timings in units of one cycle of the display clock according to the amount of movement of the display image in the horizontal direction with respect to the fixed display start timing in the horizontal direction while keeping the relationship fixed; An image memory control device comprising: