JPS61127143A - Analyzing method for trouble on semiconductor device - Google Patents
Analyzing method for trouble on semiconductor deviceInfo
- Publication number
- JPS61127143A JPS61127143A JP24890684A JP24890684A JPS61127143A JP S61127143 A JPS61127143 A JP S61127143A JP 24890684 A JP24890684 A JP 24890684A JP 24890684 A JP24890684 A JP 24890684A JP S61127143 A JPS61127143 A JP S61127143A
- Authority
- JP
- Japan
- Prior art keywords
- current
- semiconductor device
- trouble
- pulse
- control circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体装置の故障解析方法に関し、もつと詳
しくは金属酸化膜半導体電界効果型トランジスタ(MO
S−FETという)や、パワーバイボーラトランノスタ
などの半導体装置の耐圧劣化モードの故障時に、その故
障箇所を焼損させて発見するようにした半導体装置の故
障解析方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a failure analysis method for a semiconductor device, and more particularly to a method for analyzing failure of a semiconductor device.
The present invention relates to a failure analysis method for a semiconductor device, such as an S-FET (S-FET) or a power bibolar trannostar, in which the failure location is discovered by burning out when the failure occurs in a pressure deterioration mode of the semiconductor device.
背景技術
従来からMOS−FETやパワーパイボーラトランノス
タなどの半導体装置の耐圧劣化が起こりた場合、この故
障置所を発見することがその信頼性向上のために必要と
なっていゐ、そこで、たとえばMOSFETを例にとる
と通常このMOS−FETは敗多くの小トランジスタの
集合として製乍され、少ないもので1110個、多いも
のでは一万個以上の小トランジスタが1チツプ内に収め
られている。このトランジスタが耐圧劣化を起こした場
合、このトランジスタのどの部分が故障になったのかを
見つける必要があった。BACKGROUND ART Conventionally, when breakdown voltage deterioration occurs in a semiconductor device such as a MOS-FET or a power polar transistor, it has been necessary to find the location of the failure in order to improve its reliability. Taking a MOSFET as an example, a MOS-FET is usually manufactured as a collection of many small transistors, with as few as 1,110 small transistors and as many as 10,000 or more small transistors housed in one chip. When this transistor's breakdown voltage deteriorated, it was necessary to find out which part of this transistor had failed.
そこで従来では、故障したデバイスは表面の封止樹脂を
除去したのち、表面を顕微鏡で観察し、故障箇所が不明
のときは、表面から1層づつ除去しながら顕微鏡で観察
するという方法がとられてきた。Conventionally, the sealing resin on the surface of a failed device is removed, and then the surface is observed under a microscope. If the location of the failure is unknown, one layer at a time is removed from the surface and observed under a microscope. It's here.
このような先行技術では、@祭者の熟練の程度により発
見できたりできなかったりし、場合によっては相当の人
間が観察しても発見し得ない場合があった。したがって
素子の信頼性が劣化していた。また1つの故障の発見に
費やす暗闇は極めて大であり、作業性の観、αからも好
ましいものではなかった。With such prior art, it may or may not be discovered depending on the level of skill of the person performing the ritual, and in some cases, it may not be possible to discover it even if a considerable number of people observe it. Therefore, the reliability of the device has deteriorated. Furthermore, the amount of time it takes to discover a single failure is extremely large, which is not desirable from the viewpoint of workability or α.
目 的
本発明の目的は、上述の技術的課題を解決し、故障して
いる半導体装置を焼損させることによって容易に故障箇
所を発見することができ、故障発見のための検査時間を
可及的に低減することができる半導体装置の故障解析方
法を提供することである。Purpose The purpose of the present invention is to solve the above-mentioned technical problems, to easily find a faulty part by burning out a faulty semiconductor device, and to minimize the inspection time for finding faults. An object of the present invention is to provide a failure analysis method for a semiconductor device that can reduce the number of failures.
実施例
第1図は、本発明の一実施例の構成を示すブロック図で
あ4.半導体装rM1の故障を解析するための解析装置
i2は、電流印加のための電流源3と、電圧計4と、電
流[3および電圧計4を制御するたとえばマイクロコン
ピュータなどによって実現される制御回路5と、半導体
装!!1に電1ma3からの電流を伝えるプローブ針6
とを含む、半導体装r!11は複数の小型モストランノ
スタ7からvlI成される。プローブ針6は半導体装i
t1の表面を覆う酸化膜な突き破ってドレインから電流
を与える。Embodiment FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. The analysis device i2 for analyzing failures in the semiconductor device rM1 includes a current source 3 for applying current, a voltmeter 4, and a control circuit realized by, for example, a microcomputer to control the current [3 and the voltmeter 4]. 5. Semiconductor equipment! ! Probe needle 6 that transmits the current from the electric current 1ma3 to 1
Semiconductor equipment r! 11 is made up of a plurality of small most lannostas 7. The probe needle 6 is a semiconductor device i
A current is applied from the drain by breaking through the oxide film covering the surface of t1.
第2図は、本発明に従う半導体解析装r!12によって
故障解析を行う場合の、半導体装111の電気回路図で
ある。半導体装置1のドレインから電流源3によって第
3図に示されるように、パルス状の過電流が印加される
。この過電流に対応した電圧を電圧計4によって測定す
る。半導体装ra1は!@2図(2)で示されるように
、小型モストランノスタ7が数個並列に接続されて、1
つのパワートランジスタを構成している。たとえば半導
体装置1がある程度その故障は所が推定できる程度であ
る場合には、第3図(1)で示されるように同一波形を
有するパルス電流を与え、このようなパルス電流を印加
中には電圧計4によって測定されるドレイン電圧がパル
スピーク値にモニタリングされ、不良品が順次破壊され
ていき、この変化率は処理回路5によって読み取られる
1作業者が目視できる程度に焼損された状態では、電圧
の降下率が極めて大となり、この降下率が予め定めた値
に達したときには、処理回路5によって電流が停止され
る。このようにして、ドレイン電圧を電圧計4によって
測定して、電圧降下度が予め定めた値に遠したことが検
出されたときには、即座に電流印加を停止することによ
って、半導体装lt1の不良箇所が目′視することが可
能な程度の状態の焼損を与えることができ、したがって
不良箇所を容易に見つけ出すことが可能となる。したが
って、従来のような手作業では検知がお(れ不良箇所が
消失してしまい、不良原因の解析作業が不可能であると
いう問題は解消される。FIG. 2 shows a semiconductor analysis system r! according to the present invention. 12 is an electrical circuit diagram of the semiconductor device 111 when failure analysis is performed using the semiconductor device 112. FIG. A pulsed overcurrent is applied from the drain of the semiconductor device 1 by the current source 3 as shown in FIG. A voltage corresponding to this overcurrent is measured by a voltmeter 4. Semiconductor equipment RA1! @2 As shown in Figure (2), several small Most Rannostars 7 are connected in parallel, and one
It consists of two power transistors. For example, if the failure of the semiconductor device 1 can be estimated to some extent, a pulse current having the same waveform as shown in FIG. 3(1) is applied, and while such a pulse current is applied, The drain voltage measured by the voltmeter 4 is monitored to a pulse peak value, and the defective products are sequentially destroyed, and the rate of change is read by the processing circuit 5.In a state where the product is burnt out to the extent that it can be visually observed by a worker, When the voltage drop rate becomes extremely large and reaches a predetermined value, the current is stopped by the processing circuit 5. In this way, when the drain voltage is measured by the voltmeter 4 and it is detected that the degree of voltage drop is far from a predetermined value, the current application is immediately stopped to detect the defective location of the semiconductor device lt1. It is possible to cause burnout to such a degree that it can be seen with the naked eye, thus making it possible to easily find the defective location. Therefore, the problem that conventional manual detection fails and the defective location disappears, making it impossible to analyze the cause of the defect, is solved.
半導体装ii!1が、外見上では故障してるか否か判ら
ない程度である場合には、第3図(2)で示されるよう
な階段状のパルス電流を印加する。このようにすれば半
導体装111の故tIiIs所を目視できる程度の焼損
状態に短時間で:a威さすことが可能となる。Semiconductor equipment ii! 1, if it is not obvious from the outside that it is malfunctioning, then a step-like pulse current as shown in FIG. 3 (2) is applied. In this way, it is possible to bring the damaged portion of the semiconductor device 111 into a burnt-out state that is visible to the naked eye in a short period of time.
このようにしてドレイン電圧の変化率が、予め定めた値
に達したときには、即座に電流を停止するようにしたの
で、故障箇所を過度に焼損させることはなく、適度な管
損状態を達成させることが可能となる。In this way, when the rate of change in drain voltage reaches a predetermined value, the current is immediately stopped, thereby preventing excessive burnout of the faulty part and achieving a moderate tube damage condition. becomes possible.
また、処理回路5によって電流源3から希望のパルス電
流を発生させるようにしたので、半導体装置の種類に応
じて、また、故障の程度に応じてパルスの大ささや幅な
どを設定することができ、したがって電流の平均値を容
易に調整することがでさろので、広範囲な半導体装置の
故障解析方法に好適に実施することが可能となる。In addition, since the processing circuit 5 causes the current source 3 to generate a desired pulse current, the magnitude and width of the pulse can be set depending on the type of semiconductor device and the degree of failure. Therefore, since the average value of the current can be easily adjusted, it is possible to suitably implement a failure analysis method for a wide range of semiconductor devices.
効 果
以上のように本発明によれば、半導体装置に流される過
電流に対応した電圧を測定するため、故障箇所の焼損状
態が容易に検知することができ、また、そのため誰でも
容易に目視することができる程度に故障箇所を過度に焼
損させることが可能となる。さらにまた、パルス状の電
流を用いるため電流の平均値を容易にllI整すること
ができ、そのため種々の半導体!IIおよび種々の故障
程度に対しても確実に故障解析を行なうことが可能とな
る。Effects As described above, according to the present invention, since the voltage corresponding to the overcurrent flowing through the semiconductor device is measured, it is possible to easily detect the burnt state of a faulty part, and therefore anyone can easily visually observe it. It becomes possible to excessively burn out the failure location to the extent that it is possible to do so. Furthermore, since a pulsed current is used, the average value of the current can be easily adjusted, and therefore various semiconductors can be used. It becomes possible to reliably perform failure analysis even for II and various failure degrees.
第1図は本発明の一実施例の構成を示すブロック図、第
2図は故障解析装置を用いて解析する際の半導体装置1
の回路図であり、第3図は半導体装r!11に印加され
るパルス電流の波形図である。FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a semiconductor device 1 when analyzed using a failure analysis device.
FIG. 3 is a circuit diagram of the semiconductor device r! 11 is a waveform diagram of a pulse current applied to the circuit 11. FIG.
Claims (1)
応した電圧を測定しつつ過電流の流れる部分を焼損させ
るようにしたことを特徴とする半導体装置の故障解析方
法。1. A failure analysis method for a semiconductor device, characterized in that a pulsed overcurrent is passed through the semiconductor device, and a voltage corresponding to the current is measured while burning out a portion through which the overcurrent flows.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24890684A JPS61127143A (en) | 1984-11-26 | 1984-11-26 | Analyzing method for trouble on semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24890684A JPS61127143A (en) | 1984-11-26 | 1984-11-26 | Analyzing method for trouble on semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61127143A true JPS61127143A (en) | 1986-06-14 |
Family
ID=17185187
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24890684A Pending JPS61127143A (en) | 1984-11-26 | 1984-11-26 | Analyzing method for trouble on semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61127143A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006047294A (en) * | 2004-06-29 | 2006-02-16 | Sanyo Electric Co Ltd | Semiconductor element analysis method |
-
1984
- 1984-11-26 JP JP24890684A patent/JPS61127143A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006047294A (en) * | 2004-06-29 | 2006-02-16 | Sanyo Electric Co Ltd | Semiconductor element analysis method |
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