JPS61126841A - Communication equipment - Google Patents

Abstract

PURPOSE:To ensure secrecy of communication by changing simultaneously a physical format at a serial interface, e.g., a frame format or a parity at the transmission side and the reception side. CONSTITUTION:Every time a data of a prescribed bit number is received, a prescribed status/control bit (e.g., a bit designating parity) stored in the first address of a memory 201 is fed to a comparator 208, compared with a status from a reception circuit main body RE, and when the both are coincident, a normal signal is outputted. Then a control count from a control count memory 202 is loaded by a counter 203 and the count is decremented every time one record (1 byte, n-record or n-byte) is transmitted. When '00000000' is detected, the operation is repeated from the start of a special format data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a communication device that is an improved serial interface device between electronic devices.

[Background Technique #1] When transferring serial data signals between electronic devices,
When the interface device is a standard component, the same interface device is often owned by another person, and in that case, the transferred contents are immediately decoded. Therefore, even if you want to keep secrets, you cannot do so. In particular, when configuring a LAN (local area network) using radio waves, there is a problem that the contents of the communication may be intercepted.

[Object of the Invention] The present invention has been made by focusing on the above-mentioned conventional problems, and it is possible to ensure the confidentiality of communication even when the interface device is a standard component when transmitting serial data signals. The purpose is to provide a communication device that can.

[Summary of the Invention] The present invention provides changing means for simultaneously changing the physical format, such as the frame format or parity, in a serial interface on the transmitting side and the receiving side.

[Embodiments of the Invention] FIG. 1 is a diagram showing an example of special format data used in the present invention.

The special format data shown in Figure 1 is sent from the sending side to the receiving side before or during normal data transmission, and it determines which parity or frame format will be used to send data in the future. be. The special format data is composed of a transmission format and a reception format, and these two formats are exchanged. In other words, the master station sends a transmission format and a reception format, and the slave station receives and transmits in accordance with the format.

The above transmission format is "Control format type", "Control count O", "Control bit O", "Control count 1", [Control bit 1], ......, "Control count n ”, “control bit n”, rooo
It is composed of ooooOJ. The "type of control format", each "control count", and each "control bit" consist of 1 byte. Then, the number shown next to the characters "control count" and the number shown next to the characters "control bit" are the same, forming a set.

Here, the above [control format type] is
It specifies whether to control data in byte units, record units, or record block units, and also specifies how many times the above series of special format data is to be used. , which specifies the number of the set to start from. Note that when controlling data in units of bytes, data may be controlled in units of n bytes, and when controlling data in units of records, data may be controlled in units of n records (n is is an integer).

The above "control bits" specify the type of frame format (for example, the number of stop bits),
This is used to specify the presence or absence of parity, odd parity, or even parity. The above-mentioned "control count" specifies the length (byte or record length) to use when the format specified by the corresponding [control bit] is used.

Note that roooooooOJ written at the end of the transmission format shown in FIG. 1 is a terminator, and indicates the end of the transmission format.

The reception format is "control format type", "control count 0", "status/control bit O", "control count 1",
"Status/control bit 1",...
......, [control count n], "
status/control", rooooooo
ooJ r composition sales tale.

Each "status/control bit" consists of one byte. Here, the above-mentioned "type of controller/ref format" and "control count" are the same as in the case of the above-mentioned transmission format, and "status/control bit" is the same as in the case of "control bit". .

Note that "0OOOOOOoO" written at the end of the reception format shown in FIG. 1 is a terminator and indicates the end of the reception format.

The above transmission format and reception format are sent according to a predetermined agreement. This allows the transmission format and reception format to be clearly distinguished from general data. An example of such a promise is that each byte of the transmit and receive formats is processed to cause a parity error before being sent, and the receiving device must ensure that the information is in the transmit and receive formats (i.e. , control information). These control information are sent every predetermined time (
For example, it is sent every second, every minute, every hour, every day). Further, the above control information may be sent and received via another line, and it is also possible to store the above storage information in a predetermined storage means and distribute it to specific members.

FIG. 2 is a block diagram showing an example of a transmitting circuit used in the present invention.

The transmitting circuit 100 includes a transmitting circuit body TR of a UART (universal asynchronous receiver and transmitter), a control bit memory 101, a control count memory 102, a counter 103, a zero detection circuit 104, a counter 105, and a selector 10.
6 and a write address register 107.

The control bit memory 101 stores the contents of "control bit O" to "control bit n", and stores the type of frame format (for example, the number of stop bits), the presence or absence of parity, odd parity, or even number. It stores the parity designation and specifies the physical format.

The control count memory 102 is used to specify the length (in bytes or words) to use when a predetermined format is used.

Next, the operation of the embodiment shown in FIG. 2 will be explained.

First, the special format data (transmission format and reception format) shown in Figure 1 is sent to the receiving side,
The receiving side recognizes that data is being sent based on the special format data. On the other hand, transmitting circuit 1
Control bit information and control count information sent via the 00 data bus are stored in a control bit memory 101 and a control count memory 102, respectively.

Next, when sending general data, do the following. That is, first, according to the address stored in the write address register 107, information on a predetermined control bit 0 is stored in the control count memory 101, and information on a predetermined control bit 0 is stored in the control count memory 102.
information is stored.

Then, each time data of a predetermined number of bits is transmitted, a predetermined control bit (for example, a bit specifying parity) stored in the first address of the control bit memory 101 is sent.

Then, the counter 103 loads the control count from the control count memory 102, and decrements its value every time the 1st data is sent as a Lou code (or 1 byte).

When the count value becomes zero, the counter 105 increments the count value by one, and based on that value, the control bit memory 101 outputs the information of control bit 1, and the control count memory 102 outputs the information of control bit 1. Information for control count 1 is output. Then, data is transmitted according to the format specified by control bit 1 during the number of records specified by control count 1. When data transfer for the number of records specified by control count 1 is completed, zero detection circuit 104 is activated, so control bit 2) control count 2 is read out, and the above operation is repeated. And roooooooo
When oJ is detected, the operation is repeated from the beginning of the transmission format.

FIG. 3 is a block diagram showing an example of a receiving circuit used in the present invention.

The receiving circuit 200 includes a UART receiving circuit body RE, a status bit memory 201, a control count memory 202, a counter 203, and a zero detection circuit 20.
4, a counter 205, a selector 206, a write address register 207, and a comparator 208.

The status/control bit memory 201 stores the contents of "status/control bit O" to "status/control bit n", and stores the type of frame format (for example, the number of stop bits) and the parity. It stores the presence/absence or designation of odd parity or even parity, and is expected to change the physical format, and operates in the same way as the control bit memory shown in FIG. Control count memory 202) Counter 203, zero detection circuit 204, counter 205, selector 206, and write address register 207 are similar to the elements/circuits shown in FIG.

The comparator 208 compares the bits from the status/control bit memory 201 and the status from the receiving circuit body RE, and outputs a normal status signal when they match.

Next, the operation of the embodiment shown in FIG. 3 will be explained.

First, the receiving side receives the special format data (transmission format and reception format) shown in FIG. 1 from the transmitting circuit 100, and the subsequent data is sent based on the special format data.
do. That is, control bit information and control count information are stored in the status/control bit memory 201 and control count memory 202, respectively.

When receiving general data, do the following. That is, first, according to the address stored in the write address register 207, a predetermined status/control bit 0 is stored in the status/control bit memory 201, and a control count O is stored in the control count memory 202.

Next, each time data of a predetermined number of bits is received, a predetermined status/control bit (
For example, the bit that specifies parity) is
It is compared with the status from the receiving circuit main body RE, and if the two match, a normal signal is output. Then, the counter 203 loads the control count from the control count memory 202, and decrements the count value every time the above data is sent by code (1 byte, n records, or n bytes).

When the count (direct) reaches zero, the counter 205
increments its count by one and, based on that value, stores the status/control bit memory 20.
1 outputs status/control bit 1, and control count memory 202 outputs control count 1. Then, during the number of records specified by control count 1, when control bit 1 completes the data transfer of one word, zero detection circuit 104 is activated, and status/control bit 2) control count 2 is read out. The above operation is repeated. And roooo.

When 000J is detected, the operation is repeated from the beginning of the special format data.

In addition, the UART transmitting circuit main body TR shown in FIG. 2,
The UART receiving circuit main body RE shown in FIG. 3 may be a commercially available standard product or may be one with special specifications.

In the above embodiment, the parity is changed, but
Frame format, flag, bucket, NRZI,
The zero insert format may be changed. Parity, frame format, flag, packet, NRZI, and zero insert format are all physical formats, and changing any one of these means changing the physical format.

[Effects of the Invention] The present invention has the effect that when transmitting serial data signals, it is possible to ensure the confidentiality of communication even if the interface device is a standard component.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of special format data used in the present invention. FIG. 2 is a block diagram showing an example of a transmitting circuit. FIG. 3 is a block diagram showing an example of a receiving circuit. TR...Transmission circuit main body, RE...Reception circuit main body, 1
00... Transmission circuit, 101... Control bit memory, 102.202... Control count memory, 201... Status/control bit memory, 200... Receiving circuit. Patent applicant: ASCII Co., Ltd. 1 Moth 1 group → 4 people Futomamat

Claims (4)

[Claims] (1) A communication device characterized by having a physical format changing means for simultaneously changing the physical format of a serial interface on a transmitting side and a receiving side. (2) The communication device according to claim 1, wherein the physical format is a parity or frame format. (3) In claim 1, the physical format changing means includes: storage means for storing the parity content or the frame format; and a storage means for storing the parity content or the frame format; A communication device comprising: a counting means for counting; and an instruction means for instructing the storage contents of the storage means in a predetermined order every time the counting means counts a predetermined number of the transfer data. (4) The communication device according to claim 1, wherein the changing means changes the parity or the frame format multiple times within a predetermined period.