JPS61126696A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To investigate an actual defective density even by a memory using an ECC circuit and to find easily a faulty relief effect by making the Error Correcting Code (ECC) into a non-action condition by an external signal. CONSTITUTION:When an external signal from an input terminal 1 is supplied through a protecting circuit 4 and the input of an ECC control signal generating circuit 2 goes to be a high level, the output of the circuit 2 is inverted to H and an ECC circuit 5 is made to an non-action condition. The memory using the ECC circuit goes to be the memory essentially which does not have the ECC circuit, and even by the memory using the ECC, the actual defective density can be investigated, a faulty relief effect by the ECC can be easily found. As this result, when the defective density of the memory is sufficiently low, the changing-over is correctly judged to make smaller the chip size deleting the ECC circuit.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention is based on BCC (Error Correcting).
The present invention relates to a semiconductor memory device incorporating a code) circuit.

[Technical background of the invention and its problems]

In recent years, as the capacity of semiconductor memories has increased, a decrease in yield due to memory defects has become a problem. As a remedy for this defect, a method using a redundant circuit has come to be used, but since this method switches the defective memory cell with the memory cell of the redundant circuit, it takes time and effort to perform this switching operation. It was necessary.

As an alternative to this, a system based on the ECC method of large computers has begun to be used in some areas. In this system, a parity pit memory cell is provided in addition to the memory cell, thereby automatically detecting and correcting errors.
Memory using GCC requires memory cells for parity bits and circuits for error detection and correction in addition to memory cells, which increases the chip size (approximately 30% larger in the conventional example). is a drawback.

Memory generally has a high defect density in the early stage of product commercialization, so the relief effect of BCC is large, but as the defect density decreases with the progress of process technology, the relief effect of ECC decreases (1. The area occupied by the BCC circuit It is thought that this will occur. In this case, a device without an ECC circuit will be more advantageous. Therefore, in order to deal with this, first of all, what is the defect density and how much of it is due to ECC? It is necessary to investigate whether it has been rescued.

In a memory with a built-in L2 FXcc circuit, error detection and correction are automatically performed within the chip, so it is difficult to examine defect density and defect repair rate. Furthermore, when analyzing a defect that cannot be repaired by the BCC circuit, it is conceivable that the automatic correction function of the ECC circuit may mask part of the defect phenomenon, making analysis difficult.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and includes a circuit that makes the ECC circuit non-operational by an external input signal, thereby investigating the yield and defect density of the ECC circuit in the non-operating state. The present invention aims to provide a semiconductor memory device whose defect relief effect can be easily investigated.

[Summary of the invention]

The present invention includes a semiconductor memory device main body incorporating an ECC circuit, and a circuit for rendering the BCC circuit inactive by an external input signal.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a circuit diagram showing the main parts of the same embodiment, and 1 is an input terminal (ponding pad) for inputting an external input signal.
, 2 is an ECC discrimination signal generation circuit that generates a signal to put the ECC circuit in a non-operating state according to the state of an external input signal, 3 is a resistor, and 4 protects the gate element of the BCC control signal generation circuit 2. The input protection circuit 5 is an ECC circuit that receives the output of the ECC control signal generation circuit 2 as an input.

[7] Under normal operating conditions, input terminal 1 is not connected to the external input bin, and ECC control signal generation circuit 2
Input A is at <1L' (low) level due to resistor 3, and output B is at 'L level. In this state, BCC
Circuit 5 is operating.

Here, at the time of wafer sorting (wafer quality inspection), a signal at the input terminal JK'H' (high) level is applied. If the resistor 3 is set to a sufficiently large resistance value, the input A of the g, cc control signal generation circuit 2 will be 'H level, and the output B will be
becomes the IIHII level, and the FCC circuit 5 becomes inactive. If the memory is operated in this state, the actual defect density of the chip can be investigated.

We also assembled the chips of the above wafer for failure analysis.
By connecting input terminal 1 and external input bin with bonding wire, EC can be controlled by changing the external input signal.
The effect of C can be easily confirmed.

In FIG. 1, the resistor 3 is connected to the input terminal, but this may be formed by a transistor. Further, although the resistor 3 is connected between the input terminal and the ground, it may also be connected between the power supply Vcc. The ECC control signal generation circuit 2 may be of any type as long as the output signal changes depending on the input signal, for example, a two-stage inverter 11.1 as shown in FIG.
2, it can be easily configured. Further, in the above example, the input signal and the output signal B are in the same phase, but they may be in opposite phases.

〔Effect of the invention〕

According to the present invention, the actual defect density of a memory using FfCC can be investigated, and the defect relief effect of BCC can be easily seen. This allows us to accurately judge the advantages and disadvantages of using an ECC circuit, and if the defect density of memory becomes sufficiently low due to advances in process technology, we can switch to a product with a smaller chip size by removing the ECC circuit. It is also possible to conclude that.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an embodiment of the present invention, and FIG. 2 is a partially detailed diagram of the same configuration. 1... Input terminal, 2... ECC control signal generation circuit,
3...Resistance, 5...ECC circuit, 11.12...
inverter.

Claims (1)

[Claims] ECC (Error Correcting Code)
A semiconductor memory device comprising: a semiconductor memory device main body having a built-in circuit; and a circuit for setting the ECC circuit in a non-operating state by an external input signal.