JPS61126696A - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- JPS61126696A JPS61126696A JP59247359A JP24735984A JPS61126696A JP S61126696 A JPS61126696 A JP S61126696A JP 59247359 A JP59247359 A JP 59247359A JP 24735984 A JP24735984 A JP 24735984A JP S61126696 A JPS61126696 A JP S61126696A
- Authority
- JP
- Japan
- Prior art keywords
- ecc
- circuit
- memory
- ecc circuit
- memory device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Semiconductor Memories (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明はBCC(Error Correcting
Code )回路を内蔵した半導体記憶装置に関する。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention is based on BCC (Error Correcting).
The present invention relates to a semiconductor memory device incorporating a code) circuit.
近時、半導体メモリの大容量化にともない、メモリの欠
陥による歩留り低下が問題となってきた。この欠陥救済
策として、冗長回路を用いたものが使用されるようにな
ったが、これは不良のメモリセルを冗長回路のメモリセ
ルと切り換える方式であるため、この切り換えの操作に
時間、手間が必要であった。In recent years, as the capacity of semiconductor memories has increased, a decrease in yield due to memory defects has become a problem. As a remedy for this defect, a method using a redundant circuit has come to be used, but since this method switches the defective memory cell with the memory cell of the redundant circuit, it takes time and effort to perform this switching operation. It was necessary.
これに代わるものとして、大型計算機のECC方式を応
用したものが一部で使用されるようにかった。これはメ
モリセルの他にパリティピットのメモリセルを設け、こ
れにより誤りを自動的に検出し訂正するものである。
gccを用いたメモリでは、メモリセルの他にパリテ
ィビットのメモリセル、及び誤シ検出、訂正のための回
路が必要となるため、チップサイズが大きくなる(従来
例では約30%大きくなる)のが欠点である。As an alternative to this, a system based on the ECC method of large computers has begun to be used in some areas. In this system, a parity pit memory cell is provided in addition to the memory cell, thereby automatically detecting and correcting errors.
Memory using GCC requires memory cells for parity bits and circuits for error detection and correction in addition to memory cells, which increases the chip size (approximately 30% larger in the conventional example). is a drawback.
一般にメモリは、製品化の初期段階では欠陥密度が高い
ため、 BCCによる救済効果は大きいが、プロセス技
術の進歩にともない欠陥密度が低下すると、 ECCに
よる救済効果は低下(1、BCC回路の占める面積が効
いてしまうということが起こると考えられる。このよう
になるとECC回路のないものの方が有利となる。従っ
てこれに対応するため、まず欠陥密度がどの程度である
か、またそのうちどれくらいがECCにより救済されて
いるかを調査する必要がある。Memory generally has a high defect density in the early stage of product commercialization, so the relief effect of BCC is large, but as the defect density decreases with the progress of process technology, the relief effect of ECC decreases (1. The area occupied by the BCC circuit It is thought that this will occur. In this case, a device without an ECC circuit will be more advantageous. Therefore, in order to deal with this, first of all, what is the defect density and how much of it is due to ECC? It is necessary to investigate whether it has been rescued.
L2かしFXcc 回路を内蔵したメモリでは、誤り
検出、訂正がチップ内で自動的に行なわれてしまうため
、欠陥密度、不良救済率を調べるのは困難である。また
BCC回路によっても救済できない不良を解析する際に
、 ECC回路の自動訂正機能のために不良現象の一部
がマスクされ、解析が困難となることも考えられる。In a memory with a built-in L2 FXcc circuit, error detection and correction are automatically performed within the chip, so it is difficult to examine defect density and defect repair rate. Furthermore, when analyzing a defect that cannot be repaired by the BCC circuit, it is conceivable that the automatic correction function of the ECC circuit may mask part of the defect phenomenon, making analysis difficult.
本発明は上記実情に鑑みてなされたもので、外部入力信
号によりECC回路を非動作状態とするだめの回路をそ
なえ、これによりECC回路非動作状態での歩留り、欠
陥密度を調査し、ECC回路の欠陥救済効果を容易に調
査できる半導体記憶装置を提供しようとするものである
。The present invention has been made in view of the above-mentioned circumstances, and includes a circuit that makes the ECC circuit non-operational by an external input signal, thereby investigating the yield and defect density of the ECC circuit in the non-operating state. The present invention aims to provide a semiconductor memory device whose defect relief effect can be easily investigated.
本発明は、 ECC回路を内蔵した半導体記憶装置本体
と、外部入力信号により前記BCC回路を非動作状態と
するための回路とを具備したものである。The present invention includes a semiconductor memory device main body incorporating an ECC circuit, and a circuit for rendering the BCC circuit inactive by an external input signal.
以下図面を参照して本発明の一実抱例を説明する。第1
図は同実施例の要部を示す回路図であり、1は外部入力
信号を入力するための入力端子(ポンディングパッド)
、2は外部入力信号の状態に応じてECC回路を非動作
状態とするための信号を発生するECC制別信号発生回
路、3は抵抗、4はBCC制御信号発生回路2のゲート
素子を保護する入力保護回路、5はECC制御信号発生
回路2の出力を入力とするECC回路である。An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a circuit diagram showing the main parts of the same embodiment, and 1 is an input terminal (ponding pad) for inputting an external input signal.
, 2 is an ECC discrimination signal generation circuit that generates a signal to put the ECC circuit in a non-operating state according to the state of an external input signal, 3 is a resistor, and 4 protects the gate element of the BCC control signal generation circuit 2. The input protection circuit 5 is an ECC circuit that receives the output of the ECC control signal generation circuit 2 as an input.
[7かして通常の動作状態では、入力端子1は外部入力
ビンと接続されておらず、 ECC制御信号発生回路2
の入力Aは抵抗3のため<1L′(低)レベルとなって
おり、出力Bは′Lルベルであシ、この状態ではBCC
回路5は動作している。[7] Under normal operating conditions, input terminal 1 is not connected to the external input bin, and ECC control signal generation circuit 2
Input A is at <1L' (low) level due to resistor 3, and output B is at 'L level. In this state, BCC
Circuit 5 is operating.
ここでウェハソート(ウェハの良否検査)時に、入力端
子J K ’H’ (高)レベルの信号を与える。抵抗
3を充分大きな抵抗値に設定しておけば、 g、cc制
御信号発生回路2の入力Aは′Hルベルとなり、出力B
はIIHIIレベルとなってFCC回路5が非動作状態
となる。この状態でメモリの動作を行なえば、チップの
実際の欠陥密度が調査できる。Here, at the time of wafer sorting (wafer quality inspection), a signal at the input terminal JK'H' (high) level is applied. If the resistor 3 is set to a sufficiently large resistance value, the input A of the g, cc control signal generation circuit 2 will be 'H level, and the output B will be
becomes the IIHII level, and the FCC circuit 5 becomes inactive. If the memory is operated in this state, the actual defect density of the chip can be investigated.
また不良解析用に上記ウェハのチップをアセンブリし、
入力端子1と外部入力ビンとをボンディングワイヤで接
続すれば、外部入力信号を変化させることにより、EC
Cの効果を容易に確認できるものである。We also assembled the chips of the above wafer for failure analysis.
By connecting input terminal 1 and external input bin with bonding wire, EC can be controlled by changing the external input signal.
The effect of C can be easily confirmed.
なお第1図では、入力人に抵抗3を接続したが、これは
トランジスタで形成してもよい。また抵抗3は入力人と
接地との間に接続したが、これは電源Vccとの間に接
続してもよい。ECC制御信号発生回路2は入力信号に
応じて出力信号がかわるものであればどのようなもので
もよく、例えば第2図の如く2段のインバータ11゜1
2により容易に構成できる。また上記の例では入力信号
人と出力信号Bが同相となるものを示゛したが、これは
逆相であってもよい。In FIG. 1, the resistor 3 is connected to the input terminal, but this may be formed by a transistor. Further, although the resistor 3 is connected between the input terminal and the ground, it may also be connected between the power supply Vcc. The ECC control signal generation circuit 2 may be of any type as long as the output signal changes depending on the input signal, for example, a two-stage inverter 11.1 as shown in FIG.
2, it can be easily configured. Further, in the above example, the input signal and the output signal B are in the same phase, but they may be in opposite phases.
本発明によれば、FfCCを用いたメモリで実際の欠陥
密度が調査可能となり、またBCCによる不良救済効果
が容易にわかる。これによシECC回路を用いた場合の
得失が正確に判断でき、プロセス技術の進歩によシメモ
リの欠陥密度が充分に低くなつた場合、ECC回路を削
除してチップサイズを小さくした製品に切り換えるとい
う判断もできるものである。According to the present invention, the actual defect density of a memory using FfCC can be investigated, and the defect relief effect of BCC can be easily seen. This allows us to accurately judge the advantages and disadvantages of using an ECC circuit, and if the defect density of memory becomes sufficiently low due to advances in process technology, we can switch to a product with a smaller chip size by removing the ECC circuit. It is also possible to conclude that.
第1図は本発明の一実施例の構成図、第2図は同構成の
一部詳細図である。
1・・・入力端子、2・・・ECC制割信号発生回路、
3・・・抵抗、5・・・ECC回路、11.12・・・
インバータ。FIG. 1 is a configuration diagram of an embodiment of the present invention, and FIG. 2 is a partially detailed diagram of the same configuration. 1... Input terminal, 2... ECC control signal generation circuit,
3...Resistance, 5...ECC circuit, 11.12...
inverter.
Claims (1)
回路を内蔵した半導体記憶装置本体と、外部入力信号に
より前記ECC回路を非動作状態とするための回路とを
具備したことを特徴とする半導体記憶装置。ECC (Error Correcting Code)
A semiconductor memory device comprising: a semiconductor memory device main body having a built-in circuit; and a circuit for setting the ECC circuit in a non-operating state by an external input signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59247359A JPH0754640B2 (en) | 1984-11-22 | 1984-11-22 | Method of manufacturing semiconductor memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59247359A JPH0754640B2 (en) | 1984-11-22 | 1984-11-22 | Method of manufacturing semiconductor memory device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS61126696A true JPS61126696A (en) | 1986-06-14 |
JPH0754640B2 JPH0754640B2 (en) | 1995-06-07 |
Family
ID=17162244
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59247359A Expired - Lifetime JPH0754640B2 (en) | 1984-11-22 | 1984-11-22 | Method of manufacturing semiconductor memory device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0754640B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0689595A (en) * | 1990-02-13 | 1994-03-29 | Internatl Business Mach Corp <Ibm> | Dynamic random access memory having on-chip ecc and optimized bit and redundancy constitution of word |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5622294A (en) * | 1979-07-31 | 1981-03-02 | Nippon Telegr & Teleph Corp <Ntt> | Memory circuit |
JPS5690500A (en) * | 1979-12-25 | 1981-07-22 | Toshiba Corp | Semiconductor memory device |
JPS59175094A (en) * | 1983-03-22 | 1984-10-03 | Mitsubishi Electric Corp | Semiconductor memory |
-
1984
- 1984-11-22 JP JP59247359A patent/JPH0754640B2/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5622294A (en) * | 1979-07-31 | 1981-03-02 | Nippon Telegr & Teleph Corp <Ntt> | Memory circuit |
JPS5690500A (en) * | 1979-12-25 | 1981-07-22 | Toshiba Corp | Semiconductor memory device |
JPS59175094A (en) * | 1983-03-22 | 1984-10-03 | Mitsubishi Electric Corp | Semiconductor memory |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0689595A (en) * | 1990-02-13 | 1994-03-29 | Internatl Business Mach Corp <Ibm> | Dynamic random access memory having on-chip ecc and optimized bit and redundancy constitution of word |
Also Published As
Publication number | Publication date |
---|---|
JPH0754640B2 (en) | 1995-06-07 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EXPY | Cancellation because of completion of term |