JPS61126664U - - Google Patents
Info
- Publication number
- JPS61126664U JPS61126664U JP799485U JP799485U JPS61126664U JP S61126664 U JPS61126664 U JP S61126664U JP 799485 U JP799485 U JP 799485U JP 799485 U JP799485 U JP 799485U JP S61126664 U JPS61126664 U JP S61126664U
- Authority
- JP
- Japan
- Prior art keywords
- control unit
- stores
- read
- communication control
- adapter package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Exchange Systems With Centralized Control (AREA)
- Monitoring And Testing Of Exchanges (AREA)
Description
第１図は本考案に係わる試験用アダプタパツケ
ージの一実施例を示す回路図、第２図はそれが適
用された場合の試験構成を示す系統図、第３図は
その動作を説明するためのフローチヤート、第４
図は従来の試験構成を示す系統図、第５図はその
動作を説明するためのフローチヤートである。
１０……主記憶装置、１１……中央制御装置、
１２……コンソール、１３……データチヤネル制
御装置、３１……パーソナルコンピユータ、３２
……フロツピーデイスク制御装置、３３……デイ
スプレイユニツト、４０……試験用アダプタパツ
ケージ、１０１〜１１５，４０２……ＲＡＭ、３
２０，３２１，３２２……フロツピーデイスク、
４０１……ＲＯＭ、４０３……入力レジスタ、４
０４……直列データ通信制御部、４０５……出力
レジスタ、４０６〜４０８……入出力端子、４０
９……データ端末インタフエースコネクタ部。
Fig. 1 is a circuit diagram showing an embodiment of the test adapter package according to the present invention, Fig. 2 is a system diagram showing the test configuration when the test adapter package is applied, and Fig. 3 is a circuit diagram showing the test configuration when the adapter package is applied. Flowchart, 4th
The figure is a system diagram showing a conventional test configuration, and FIG. 5 is a flowchart for explaining its operation. 10...Main storage device, 11...Central control unit,
12...Console, 13...Data channel control device, 31...Personal computer, 32
...Floppy disk control device, 33...Display unit, 40...Test adapter package, 101-115,402...RAM, 3
20,321,322...Floppy disk,
401...ROM, 403...input register, 4
04... Serial data communication control unit, 405... Output register, 406-408... Input/output terminal, 40
9...Data terminal interface connector section.
Claims (1)
、主記憶装置制御命令を実行することにより直列
データ通信を可能とする通信制御手段と、前記通
信制御手段により読み込まれたプログラムを格納
する一時記憶部とを備えたことを特徴とする試験
用アダプタパツケージ。 A read-only memory that stores an initial program, a communication control unit that enables serial data communication by executing a main storage control command, and a temporary storage unit that stores the program read by the communication control unit. A test adapter package characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP799485U JPS61126664U (en) | 1985-01-25 | 1985-01-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP799485U JPS61126664U (en) | 1985-01-25 | 1985-01-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61126664U true JPS61126664U (en) | 1986-08-08 |
Family
ID=30486866
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP799485U Pending JPS61126664U (en) | 1985-01-25 | 1985-01-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61126664U (en) |
-
1985
- 1985-01-25 JP JP799485U patent/JPS61126664U/ja active Pending
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