JPS61124177A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve the withstand voltage between a source and a drain without forming a diffused N<-> type layer like a LDD structure by forming a high density transistor threshold value controlling impurity layer from a substrate at part of a channel between the source and the drain. CONSTITUTION:In a channel region between a source S and a drain D, part of a gate G side, i.e., the state that an impurity layer 13 is implanted in high density is obtained, and the other portion becomes the same impurity density as a substrate 11. Here, the state that a channel N<-> is formed as designated by a broken line even if a gate voltage is 0V, i.e., a depletion state is provided at the gate G side of the source S and the drain D in the portion that the layer 13 is removed by suitably selecting the impurity density of the electrode material of the gate electrode 14', i.e., the polysilicon and the substrate 11. Thus, the withstand voltage between the source S and the drain D can be improved by selecting the impurity density of the polysilicon of the gate electrode 14' with respect to the impurity density of the substrate 11.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device having an MO8 type structure, and particularly to a semiconductor device having an MO8 type structure.
This improves the breakdown voltage between the source and drain of an O8 type transistor.

[Conventional technology]

In recent years, semiconductor devices have become highly integrated.

Densification is progressing, but one of the problems is that M
There is a drop in breakdown voltage between the source and drain of an O8 type transistor.

To counter this, it is necessary to prevent the drain depletion layer from extending into the channel region. Generally, the impurity concentration in the channel region is increased, the gate oxide film is thinned, and the drain and source junctions are made shallow. It is considered to do.

Conventionally, in order to improve the source and drain breakdown voltage, for example, an LDD (Lightly Drain) as shown in FIG.
Transistors with a doped drain structure and transistors using graded source/drain structures have been proposed.

In other words, the manufacturing method for LDD structure transistors was 5E in the 1983 IEDM (p. 63-66).
PO8 and its properties were published in 1980 I
E8VOL-ED 27 & 8 (p, 1859-1
867 S, 0 GURA et al.), but the third
To explain using a diagram, a low concentration diffusion layer N- is formed on the gate (G) side of each of the N+ source (S) region and drain (D) region on the P-type S1 substrate (1), and the drain (D) weakens the electric field from source 4 (S).
), the effective voltage applied between the drain (D) and the drain (D) is reduced to improve the breakdown voltage. In addition, in Figure 3, (2)
8i02 is an oxide film, and (3) is a gate electrode made of poly S1.

In addition, a transistor using a Dale-Brad source/drain forms the source and drain with a gently sloped impurity concentration distribution, and this concentration distribution weakens the electric field strength near the celltrain.

[Problem that the invention seeks to solve]

However, according to the prior art, in the case of the LDD structure, each gate (of the source (S) and drain (D)) (
There is a problem that a low concentration diffusion layer IN- must be formed on the G) side, and furthermore, this diffusion layer N-.

In other words, if a resistance component enters the series between the source (S) and drain (D), the transistor characteristics will deteriorate. In addition, in the case of the Dalei Brad source/drain structure, a single layer of N is placed around the source and drain layers in the substrate, and as mentioned above, it is necessary to form the concentration distribution of the drain during the manufacturing process. C,
Moreover, since a single layer of N is formed around the entire circumference of the drain, L
There is a disadvantage that the transistor characteristics are lower than in the case of the DD structure.

[Means for solving problems]

The present invention takes the above points into consideration and aims to improve the withstand voltage between the source and the drain without using the above-described structure.
An impurity layer having a higher concentration than the substrate of the transistor is formed in a part of the channel part between the drains on the gate side, and the other part of the channel part is made to have an impurity concentration equal to that of the substrate, and is formed on the gate electrode. The present invention provides a semiconductor device characterized in that a material is used in which a channel is formed on the gate side of each of the source and drain at the substrate-to-gate voltage OV.

[For production]

Therefore, an impurity layer for transistor threshold control with a higher concentration than the substrate is formed in a part of the channel part between the source and drain, and in the other part of the channel part, that is, a part with the same impurity concentration as the substrate. ,
Since a channel can be formed on each gate side of the drain by simply selecting the gate electrode material, L
Unlike the DD structure, it is possible to improve the breakdown voltage between the source and drain without forming a single diffusion layer N in advance.

〔Example〕

Next, the present invention will be explained in detail with reference to FIGS. 1 and 2 showing one embodiment thereof.

FIG. 1 shows a semiconductor device of the present invention, that is, an MO8 type transistor, and a method for manufacturing the same will be explained with reference to FIG.

First, as shown in FIG. 2(a), a P-type S1 substrate 01)
The surface is oxidized to form an oxide film of Si02, and ions are implanted from above as shown by the arrows to form a highly concentrated impurity layer 03 for controlling the threshold of the transistor.

Next, as shown in FIG. 5B, a gate metal such as poly 8iQ4) is deposited on the oxide film α, and this is turned into a pattern using a resist Q5).

Then, using the resist 051 on the gate metal 04) as a mask, as shown in FIG. 3(C), the substrate is etched by 0υwoaoooo to 5000λ along with the oxide film.

Furthermore, as shown in the figure (d), the surface of the substrate 01) is oxidized to form an oxide film α) of 5i02, which is the same as the gate metal described above. JSI04) is again deposited on the entire surface of the substrate αυ.

Next, RIE (Reactive Ion Etching)
Using the etching technique, the holes IJ 51 (14) on the surface of the substrate 0]) are etched so that the poly 5iQ4) in the lateral direction of the substrate αη remains, and as shown in FIG. 1, the gate electrode 04) is completed. , N@, that is, source (S), drain (
D) is formed.

At this time, in the channel region between the source (S) and drain (D), impurities are introduced into a part of the gate (G) side, that is, the impurity layer Q [with] at a higher concentration than the substrate 0]). The other parts have the same impurity concentration as the substrate 01). Here, by appropriately selecting the impurity concentration of the electrode material of the gate electrode 04)', that is, the impurity concentration of poly-Si and the impurity concentration of the substrate θη, the source (S) in the region excluding the impurity layer θ east of the channel region can be , the drain (D) has a channel /I/
A state in which N- is formed, that is, a depression state is reached.

For example, in the example, the concentration P type 1×l0 of the substrate 01)
15M, impurity @03 concentration P type 5 x 10 Wei, poly S+
The concentration of the source (S) and the drain (D) is N-type]X1020Ad, and the concentration of the source (S) and drain (D) is N-type]X]020/d. Note that the thickness of the gate oxide film α is 500A.

Therefore, even if the diffusion layer N- is not formed in the manufacturing process as in the LDD structure, the source (S), drain (D) (7) (-
A channel N can be formed near each gate (G), and the channel N- formed by the depletion state together with the impurity layer 03 for controlling the threshold of the transistor.
Therefore, the breakdown voltage between the source (S) and drain (D) can be improved.

〔Effect of the invention〕

As described above, according to the semiconductor device of the present invention, the withstand voltage between the source and drain of an MO8 type transistor can be improved without using a conventional LDD structure.

[Brief explanation of drawings]

1 and 2 show one embodiment of the semiconductor device of the present invention, FIG. 1 is a sectional view, FIGS. 2(a) to 2(d) are sectional views showing the manufacturing process, and FIG. 3 is a sectional view showing the manufacturing process. 1 is a cross-sectional view of an MO8 type transistor with a conventional LDD structure. 01)...Substrate, 0■...Impurity layer, 04)'...
・Gate voltage 1i, (S)...source, (D)...
Drain, (G)...Gate.

Claims (1)

[Claims] (1) An impurity layer having a higher concentration than the substrate of the transistor is formed in a part of the gate side of the channel part between the source and drain of the MOS transistor, and the other part of the channel part is made to have the impurity concentration of the substrate. A semiconductor device characterized in that the gate electrodes are made of a material that forms a channel on the gate side of each of the source and drain when the voltage between the substrate and the gate is 0V.