JPS61123278A - Dither picture data restoring circuit - Google Patents

Abstract

PURPOSE:To simplify the control of error recovery processing by processing a data in block line through a pipeline and avoiding data processing in a different block line from being executed during the pipeline processing to clear an error immediately after it takes place. CONSTITUTION:Received compression data is fed to a forecast order code decod ing circuit 1, where the compression data code is decoded and the forecast level is identified. An output of the circuit 1 is fed to a pattern number recovery circuit 2 via a register 9, where the pattern number of the coded block is recovered by forecasting reversely the future pattern from the pattern of the reference block and the forecast level. Then the pattern number is fed to a dither picture recovery circuit 3 to recover the corresponding dither picture data. All circuits are controlled by a block unit data transfer control circuit 12, a line unit data transfer control circuit 13 and control circuits 5-8 so that the line is transited to the next block line after the same block line processing is finished.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dither image data restoration circuit that restores dither image data compressed by a pattern predictive coding method.

[Conventional technology]

A dither method is known as a method of pseudo-expressing halftones using black and white binary values, for example, as shown in FIG. 3(a).

(b) and (0) indicate the threshold values of the 4×4 Bayer type, halftone type, and spiral type dither matrices, respectively. When multivalued image data is binarized using such a dither matrix, many short white or black run lengths (the length of consecutive pixels of the same color) appear, so data compression using a standard method such as the MH method is not possible. It's something you can't expect.

Therefore, a pattern predictive coding method has been proposed as a compression method for dithered image data.

In the pattern predictive coding method, for example, each block is divided into blocks of 2 x 4 pixels, a pattern with a high frequency of appearance among the black and white patterns in each block is used as a basic pattern, and two adjacent blocks are coded using this basic pattern. When a 4 x 4 Bayer dither matrix is used, the 4 x 4 pixels are divided into an upper row and a lower row, as shown in Figure 4. If you attach a pattern fish (pattern number) to each, pattern magnets 0 to 8
is a pattern that appears as a gradation pattern, and pattern fish 9 to 15 are added patterns, making a total of 32 types of patterns as basic patterns. This 3
98% of the entire image area can be expressed using two types of basic patterns.

FIG. 5 shows encoded blocks BL of 2×4 pixels,
and reference blocks BL, BL, and the prediction order of the encoded block BLo is the reference blocks BL, BL,
It is determined by the statistical properties of the image with respect to the black and white pattern of BLz, for example, the reference professional BL, .
The black and white pattern of the same pattern fish as the black and white pattern of BL2 will be number 1.

Figure 6 shows the correspondence between prediction ranks and codes; when the prediction rank is No. 1, the shortest code length "1" is assigned, and when the prediction rank is No. 2, a longer code length is assigned. “0”
1", and then a longer code is assigned as the prediction rank decreases. Also, patterns that cannot be expressed only with basic patterns are treated as non-basic patterns and raw data is inserted in the * mark. Also, line synchronization The signal EOL is
It uses the same codes as the MR system, and the code length of each code is shown on the right side.

FIG. 7 shows a flowchart of data compression processing, and the encoded block input is, for example, the 2×
A coded block BL of 4 pixels is input. It is determined whether or not this encoded block BL corresponds to the basic pattern shown in FIG. Prediction is made using the pattern fish of the block, the prediction order is converted into a code as shown in FIG. 6, and the pattern fish of the encoded block is used as the pattern fish of the next reference block. If it is not a basic pattern, the pattern of the encoded block is approximated by the basic pattern and a pattern fish is added,
The raw data of the encoded block is used as the code inserted into the stamp pad as shown as a non-basic pattern in FIG. 6, and the pattern block of the encoded block is used as the pattern of the next reference block.

Further, FIG. 8 shows a flowchart for restoring a compressed code, in which received compressed data is input, code decoding is performed, and whether or not it is a basic pattern is identified. In the case of a basic pattern, prediction rank decoding is performed, the pattern of the encoded block is deduced from the predicted rank, the pattern is converted to a dithered image, and the pattern of the encoded block is converted to the next reference block. This is a pattern fish. If it is not a basic pattern, create a pattern fish by approximating the raw data in the code with the basic pattern, output the raw data as it is as a dithered image, and use the created pattern fish as the pattern magic of the next reference block. That is.

FIG. 9 shows a block diagram of a conventional dither image data restoration circuit, in which 1 is a prediction order code decoding circuit, 2 is a pattern fish reproduction circuit, 3 is a dither image reproduction circuit, 4 is an output buffer memory circuit, and 4 is an output buffer memory circuit. Parts 4a, 4b (BFl
, BF2). Further, numerals 5 to 8 are control circuits for controlling the aforementioned circuits 1 to 4, respectively, numerals 9 to 11 are registers whose latch timings are controlled by the respective control circuits 5 to 8, and numeral 14 is a data transfer control circuit for each block.

The received compressed data is applied to the prediction rank code decoding circuit 1, where the code of the compressed data is decoded, and whether or not it is a basic pattern is identified and the prediction rank is identified. Also, when an error such as an error in which there is no corresponding code in the compressed data or an error in which a line synchronization signal is not present at a predetermined position is detected, only this predicted rank code decoding circuit 1 is used until the next one-dimensional line synchronization signal is found. It continues to operate.

The output data of the prediction order code decoding circuit 1 is latched into the register 9 and applied to the next pattern prevention reproducing circuit 2. The pattern fish reproducing circuit 2 reproduces the hidden pattern of the encoded block by performing inverse constellation from the predicted order and the pattern fish of the reference block. This pattern data is applied to the dither image reproduction circuit 3 via the register 10, and dither image data corresponding to the pattern pattern is reproduced. This dithered image data is applied to the output buffer memory circuit 4 via the register 11.

In the output cover sofa memory circuit 4, the output cover sofa parts 4a and 4b each have a capacity of 1 block line,
When dither image data is being written to one side, it is controlled by the control circuit 8 to read from the other side, and in the case of error detection, the data of the immediately preceding block line is output instead of the block line data where the error has occurred. It is controlled as follows.

As mentioned above, the prediction order code decoding circuit 1. Pattern fish reproduction circuit 2. In the dither image reproduction circuit 3 and the converter sofa memory circuit 4, respective control circuits 5 to 8 are controlled by the data transfer control circuit 14, and pipeline processing is performed. Further, when a non-basic pattern is identified, the raw data of the non-basic pattern is transferred to each circuit as it is and is output from the converter sofa memory circuit 4.

Fig. 10 is an explanatory diagram of the operation timing during normal operation, and shows the restoration operation of compressed data encoded at 864 blocks/line with a resolution of 16 lines/mm on 9/10/11 to latch the data. The timing is shown, EOL in (a) is a line synchronization signal, and 1 to 864 are blocks. Further, (d) shows writing to the output buffer memory circuit 4, and (e) shows reading from the output buffer memory circuit 4, where BFI shows writing and reading in the output buffer section 4a and BF2 shows writing and reading in the output buffer section 4b.

As mentioned above, the conventional dithered image data restoration circuit performs complete pipeline processing, so for example,
When the prediction rank code decoding circuit 1 is processing the line synchronization signal EOL of the n+1 block line and the data of block l, the pattern fish reproduction circuit 2 processes the data of block 864 of the n block line, and the dither image reproduction circuit 3 In this case, the data of block 863 of the n block line is being processed.

[Problem that the invention seeks to solve]

In the conventional dithered image data restoration circuit, since complete pipeline processing is performed, even if the prediction rank code decoding circuit 1 starts processing the n+l block line, the conversion block sofa memory circuit 4 contains n blocks. This means that writing of data on the line has not yet been completed. Therefore, a problem arises in operation when an error occurs. 11 and 12 show the operation timing of the conventional example when an error occurs. In each figure, (a) is an error clear pulse, (b), (
c) and (d) indicate the timing for latching data in registers 9, 10, and 11, respectively, and (Q) and (
f) shows writing to and reading from the buffer memory circuit 4, BF1 shows the operation of the output buffer section 4a, and BF2 shows the operation of the output buffer section 4b.

As an error recovery process when an error occurs, the entire circuit is stopped, and then only the predicted order code decoding circuit 1 is operated until the next one-dimensional line synchronization signal EOL +11 is found, and the two-dimensional line synchronization that appears during that time is Signal E OL (
2), and then returns to normal operation after outputting the block line data just before the block line in error by the counted number instead.

In FIG. 11, an error occurs in which the line synchronization signal EOL is not detected after block 864, and an error clear pulse is output at time t1 due to the error detection, and the code that has been decoded up to that point is By saying that there was an error in the error, the entire data recovery circuit including the output buffer section 4a that is currently being written is immediately cleared, and prediction is continued until the next one-dimensional error in-synchronization signal EOL (1) is detected. Only the rank code decoding circuit 1 is in operation, and the two-dimensional line synchronization signal EOL (21) is counted, and by the detection of the -dimensional line synchronization signal EOL (11), the counted number is output from the cover sofa section 4b (BF2). The block line data that was written before the error occurred is repeatedly read and sent, and when the sending ends, processing starts from block 1 after the line synchronization signal EOL (1).Therefore, normal operation starts from time t1. The time until time t2 when the error returns is the time for error recovery processing.

Also, in FIG. 12, the two-dimensional line synchronization signal EOL
This is a case where an error occurs such as not finding the corresponding code at time t3 after (2), and at this point, the data written to the output cover section 4a is correct, and the final data of the block line is not written. has not yet been completed. Therefore, at time t4 when writing of the final data of the block line to the output cover sofa section 4a is completed, an error clear pulse is outputted to clear the entire data restoration circuit. Then, as in the case described above, only the prediction order code decoding circuit 1 continues to operate, and the -dimensional line synchronization signal E O
The two-dimensional line synchronization signal E
OL (21 is counted. Then, the count number is repeatedly read out from the output cover 7 front section 4a (BFI) in which correct data has been written. Therefore, an error clear pulse is generated from time t3. Time t
4 is the standby time, and the time from time t4 to time t5 when normal operation is returned is the time for error recovery processing.

As described above, in the conventional system, complete pipeline processing is performed, which has the disadvantage that two types of control must be performed depending on the state at the time of error occurrence.

The present invention aims to improve the above-mentioned conventional drawbacks and simplify control when an error occurs.

[Means for solving problems]

The dithered image data restoration circuit of the present invention includes a prediction rank decoding circuit, a pattern reproduction circuit, a dithered image reproduction circuit, an output buffer memory circuit, and performs pipeline processing in each of the circuits for processing within a block line. In between, each of the circuits is provided with a control circuit that causes the processing to proceed to the next block line after completing the processing of the same block line.

[Effect]

Processing within the same block line performs data restoration processing at high speed using pipeline processing, and after each circuit finishes processing the same block line, it starts processing the next block line, so when an error occurs, It is possible to immediately clear the entire circuit and perform error recovery processing without waiting time.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which the same reference numerals as in FIG. 9 indicate the same parts, 12 is a block unit data transfer control circuit, and 13 is a line unit data transfer control circuit. The block unit data transfer control circuit 12 has almost the same control function as the data transfer control circuit 14 in FIG. 9, and the line unit data transfer control circuit 1.
3 is a prediction order code decoding circuit 1, a pattern fish replay circuit, a dither image replay circuit 3, and an output buffer memory circuit 4.
It has a control function so that after all of the blocks have finished processing the same block line, the processing shifts to the next block line. These block unit data transfer control circuit 12 and line unit data transfer control circuit 13 are as follows:
It can be configured by a microprocessor, etc., and reads the status information of each circuit via each control circuit 5 to B under program control, and judges whether processing is completed for each block and block line. let them do it;
It is also possible to control the continuation or stop of processing in each circuit.

FIG. 2 is an explanatory diagram of the operation timing of the embodiment of the present invention, in which (a) shows the error clear pulse, (b), (C1, (
dl indicates the timing at which data is latched into the registers 9, 10, and 11, respectively, and (el, (fl) indicate the write and read operations of the output buffer memory circuit 4.

After the processing of the final block 864 of the block line consisting of
Processing of the block to be read begins. Therefore, time t6
, an error clearing pulse is output as shown in (a) when an error occurs in which the corresponding code cannot be found, and even if the entire circuit is cleared, the processing of the block line immediately before it is completed. Since there is no need to wait, the error can be cleared immediately upon occurrence. Then, in this case, due to error recovery processing,
After sending out the repeatedly read data from the output cover sofa section 4a, the normal operation returns from time t7. Therefore, the period from time t6 to time t7 is the time for error recovery processing.

Also, if an error such as a line synchronization signal not being found occurs, immediately clear the entire circuit with an error clear pulse, clear the contents of the output buffer section of one of the output buffer memory circuits 4 that is currently being written, and then Since the restored data of the immediately previous block line has been written to the other output cover section, error recovery processing is performed by repeatedly reading and transmitting this data.

Therefore, regardless of the state at the time of error occurrence, error recovery can be performed using the same control.

〔Effect of the invention〕

As described above, the present invention provides a prediction rank code decoding circuit 1. Pattern fish reproduction circuit 2. Dithered image reproduction circuit 3. Processing in the output buffer memory circuit 4 and block lines is performed by pipeline processing in each of the circuits, and between block lines, a line is used in which each circuit moves to the next block line processing after all of the circuits have finished processing the same block line. This system is equipped with unit data, a control circuit consisting of a transfer control circuit 13, etc., and since there is no period during pipeline processing where data of a different block line is being processed, an error can be cleared immediately when it occurs. There is an advantage that the error recovery process can be shifted to the error recovery process, and the control of the error recovery process is simpler than in the conventional example.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is an explanatory diagram of operation timing when an error occurs in the embodiment of the present invention, and Fig. 3 is a block diagram of an embodiment of the present invention.
Figures 8) to (C) are explanatory diagrams of a 4x4 dither matrix, Figure 4 is an explanatory diagram of the basic pattern of the pattern predictive encoding method, Figure 5 is an explanatory diagram of encoded blocks and reference blocks, Fig. 6 is an explanatory diagram of code allocation in the pattern predictive coding method, Fig. 7 is a flowchart of data compression processing, Fig. 8 is a flowchart of data restoration processing, Fig. 9 is a block diagram of a conventional data restoration circuit, and Fig. 10. 1 is a diagram illustrating the operation timing of the conventional example during normal operation, and FIGS. 11 and 12 are diagrams illustrating the operation timing of the conventional example when an error occurs. 1 is a prediction rank code decoding circuit, 2 is a pattern prevention reproducing circuit,
3 is a dither image reproduction circuit, 4 is an output buffer memory circuit, 4a and 4b are output buffer sections (BFI, BF2),
5 to 8 are control circuits, 9 to 11 are registers, 12 is a block unit data transfer control circuit, and 13 is a line unit data transfer control circuit.

Claims (1)

[Claims] In a dithered image data restoration circuit based on a pattern predictive coding method, a prediction order code decoding circuit and a pattern No. Processing within the playback circuit, dither image playback circuit, output buffer memory circuit, and block line is performed by pipeline processing in each circuit, and between block lines, the next processing is performed after all of the above circuits have finished processing the same block line. A dithered image data restoration circuit comprising: a control circuit for shifting to block line processing.