JPS61122993A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To increase and strengthen a driving ability to realize a high speed of a reading speed by operating a sense amplifier in a non-selected block after bit lines of respective blocks are connected in series to one another by turning a switch on. CONSTITUTION:Immediately after all switches for connecting bit lines are turned on, making a clock phi' H, and turning a transistor Q15 on, sense amplifiers of all blocks are activated. In this manner, after the switch is turned on, a sense amplifier of a non-selected block is also operated to increase a driving ability. Accordingly, even when a bit line BL becomes individual, a difference in an electric potential between bit lines is rapidly restored to make fast a time to change a next address and attain a high speed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention divides each bit line into a plurality of blocks,
This invention relates to a semiconductor memory device in which the bit lines of each block can be connected in series by switches and each block is provided with a sense amplifier, and an attempt is made to further speed up the operation of this type of memory device.
1 [Prior Art] As the capacity of semiconductor memory increases, the number of memory cells connected to each word line and bit line increases, but this increases the load capacitance of the word line and bit line, making it difficult to operate at high speed. It is a hindrance to To improve this point, word lines or bit lines may be divided.

Figure 6 shows an example in which the bit lines of each column are divided into multiple parts.
L and BL, BL. and BL, , -... are divided 0, 1, . . . of the i-th column. . . . is the numbered bit line pair. Coo”Cgn, C10-C1n.

. . . are memory cells belonging to the same column, but are connected to and divided into blocks. B
Ko.

BK+, . . . indicate such blocks. Each block BKo, BK+, . . . is provided with a sense amplifier SAa, SAD, . . ., respectively.
It is activated 0 0' 1 t' by the selection signals BSo, BS+, . . . Tadasu and S, , S, and Sl, . . . are switches that connect the bit lines of each block in series and open them. Ql and Q2 are transfer gates controlled by the column selection signal Y, and DB. , DB is a data bus.

In the memory configured as described above, when a word line of block BKo is selected and a cell in the i-th column belonging to the word line is selected, first, only sense amplifier SAo is activated by block selection signal BSo. As a result, bit line B
The differential voltages t i of L'HIBL' are connected in series, and the gates Q1 .
Open Q2 and these pi-IJI! The pair is connected to data buses DB and DB, and data is read onto the data buses.

(Problem to be Solved by the Invention) The advantage of the bit line division described above is that the load capacitance of each sense amplifier during sensing operation is small (only for one divided bit line pair).However, Switch S, + S?'l S; + S:'+...
. . is turned on and each bit line pair is connected, the load capacitance of the sense amplifier increases to the value before the bit line division. Therefore, the time it takes to finally generate the required voltage difference on the data buses DB and Di is not shortened much. The present invention attempts to improve this point by also utilizing the sense amplifier of the non-selected processor.

[Means for solving problems]

The present invention divides each bit line into a plurality of blocks,
The bit lines of each block can be connected in series using switches, and each block is equipped with a sense amplifier.
In a semiconductor memory device in which, following word line selection, the sense amplifier in the block to which the selected word line belongs is operated, and then the switch is turned on to connect the bit lines of each block in series, the switch is turned on. This is characterized in that the sense amplifiers in non-selected blocks are also operated after this.

[Effect]

When the bit line pro and ivy series connection switch is off, each block is separated individually and the load capacitance is small, so the sense amplifier in the selected block is operated to quickly expand the bit line potential difference. Furthermore, when the switch is turned on and the bit lines of each block are connected, the sense amplifiers in the non-selected blocks are also operated, thereby increasing the drive capability and increasing the read speed. This will be explained in detail below with reference to illustrated embodiments.

〔Example〕

In the present invention, if the word line (not shown) of block BKo in FIG.
, BL, activates the sense amplifier SAo by the signal BSo. and BLI... and BL? and ``p'' are connected in series, and then the sense amplifiers SA+, . A sense amplifier SAo is used for a memory that performs such an operation.

Details of S A + , . . . are shown in FIG. 1. In the figure, QIO.

Ql2 is a p-channel MO3) transistor, Qll.

Q13 to GLts are n-channel MOS transistors. QlO+ Qz and Ql2 and Ql3 are each C
A MOS inverter is configured, and a flip-flop is configured by cross-connecting these two inverters. The transistor QI4 is turned on by the block selection signal BS and activates this sense amplifier, but the transistor Q15 connected in parallel with it is connected to the clock that becomes H (high) after the aforementioned bit line connection switch is turned on. It is turned on by φ'. This signal φ' is simultaneously applied to all intra-block sense amplifiers.

The operation will be explained with reference to the time chart of FIG. 2. When address Add changes at time to, precharge signal P is generated, and all bit line pairs BLt, BLi
are precharged so that they have the same potential (for example, Vcc - Vth). This bit line precharge circuit is composed of transistors Q3 to Q5 shown in FIG. 7(a), for example. Although the figure relates to block BKa, each block is provided with a similar configuration. Next, if word line WLo (see FIG. 7) is selected at time t1, cell COO is selected in the column of FIG. 6, and bit line pair BL of block BKo is selected based on the cell information.

BL? A minute potential difference is generated between the two. Therefore, when the block selection signal BSa is set to H at time t2 to activate the sense amplifier SAo (transistor QI4 is turned on in FIG. 1), the potential difference between the bit line pair BL, , B[0 is amplified. When a sufficient differential voltage is applied to BL, BL, by this sensing operation, the clock pulse φ is set to H at time t3, and the switch 1' shown in FIG.
Turn on all... These switches are, for example, an n-channel transistor Q6 as shown in FIG. 7 (bl).
The circuit configuration is such that the transistor Q7 is used alone, or as shown in FIG. 3C, a p-channel transistor Q7 is further connected in parallel to the transistor Q7, and these transistors are simultaneously driven at the same time.

The process up to this point is the same as before, and immediately after turning on the switch, the other focus lines Bx, :, st, :',...
Since the potentials of . However, in the present invention, immediately after this (t4), the clock φ' is set to H, the transistor Q15 in FIG. 1 is turned on, and the sense amplifiers of all blocks are activated. In this way, after t4, the sense amplifiers S A of non-selected blocks BK+, ...
+, . . . also participate in the operation, and - the drive ability increases at the same time. Therefore, even if the number of bit lines is reduced to one, the potential difference between the bit line pairs BL, , BL, (BL, , BL, hereinafter the same) quickly returns to the value immediately before t3. The broken line in FIG. 2 shows the conventional bit line potential change. As a result, the time t5 at which the address Add can be changed next is brought forward and the speed is increased.

FIG. 3 is a schematic diagram showing an example of a clock φ generation circuit (address change detection circuit) ATD. In this circuit ATD, the row (ROW) address for selecting a word line is A o
%A n, detect the change for each address bit. For example, if the address Aa changes as shown in FIG. 4, the delay circuit DLY delays it for a certain period of time. And exclusive logic first time Fjl! By calculating the delayed output Aa' and the address Aa using EOR, a pulse φ0 having the width of the delay time is obtained. This is done for all address bits to obtain similar pulses φJ to φn.

These pulses φ0 to φn do not all change at the same time, so they are OR gates. Add these in R and get the second
A clock φ that always changes when the address Add shown in the figure changes is created. In FIG. 2, this is delayed and the pulse width is also changed, but a circuit explanation of this portion will be omitted.

Clock φ' is created by further delaying the above-mentioned clock φ. Therefore, if the entire signal generation system is illustrated, it will be schematically shown in FIG. In the figure, Ai is '7-F line WL
The address bit that selects the address is taken into the address buffer 1 and decoded by the row decoder 2. Aj is an address bit (part of At) for selecting a block, and is taken into the address buffer 3 and decoded by the block decoder 4. 5 is the above-mentioned ATD, which generates clocks φ and φ'. In order to make the fall of this clock φ correspond to the next address change timing (ts in FIG. 2), it is preferable to use a flip-flop 6 that is clocked at the clock φ and reset at the rise of the precharge signal P mentioned above. . The same applies to φ'.

〔Effect of the invention〕

As described above, according to the present invention, there is an advantage that the read speed of a bit line split type semiconductor memory device can be increased by also utilizing sense amplifiers of non-selected blocks.

[Brief explanation of the drawing]

Fig. 1 is a main circuit diagram showing an embodiment of the present invention, Fig. 2 is its operating waveform diagram, Figs. 3 to 5 are explanatory diagrams of various signal generation circuits, and Fig. 6 is a bit line split type. Explanatory diagram of memory, 7th
The figure is a detailed view of the part. In the figure, BKo, BK+, ...-- are blocks, BL?
BL,... are divided bit lines, S?
,S! .・・・・・・ is the bit line connection switch, SAo, SA
+. ... is a sense amplifier, Q14 is a transistor for activating the sense amplifier of the selected block, and Q15 is a transistor for activating the sense amplifier of the non-selected block.

Claims (1)

[Claims] Each bit line is divided into a plurality of blocks, the bit lines of each block can be connected in series with a switch, and each block is provided with a sense amplifier. The sense amplifier is operated, and then the switch is turned on to connect the bit lines of each block in series, and after the switch is turned on, the sense amplifiers in non-selected blocks are also operated. semiconductor storage device.