JPS61121785A - Speed detector of servo motor - Google Patents

Abstract

PURPOSE:To stably lead a motor to normal speed by providing the third monostable multivibrator having an output pulse shorter than the counting period in the front state of the first monostable multivibrator. CONSTITUTION:A speed controller 12 inputs the output of a frequency generator 25 connected with a motor 24 to a limiter 13, and inputs the output to the third monostable multivibrator 26. The third monostable multivibrator 26 outputs a pulse shorter than the counting period by a counter 15. The output of the multivibrator 26 is led through the second sampling pulse forming circuit 21 to the second sample-holding circuit 19, and the other is input to the first multivibrator 14. The counter 15 counts the output signal of a clock signal generator 16 at the prescribed number synchronously with the rise of the output of the multivibrator 14, and then returns to the reset of the multivibrator 14 to obtain a reset signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a speed detection circuit for a seven-point servo in a recording/reproducing type disc player or the like.

[Background of the invention]

A recording/sickle reproducing type disc player detects a mark signal for recording positioning that is provided in advance at one location per revolution on a disc-shaped recording medium (hereinafter referred to as a disc), and uses this signal to control the motor servo system. This constitutes a phase control circuit. This is to synchronize the external video signal with this mark signal and align the recording position when recording information on the disc.1. For this reason, the sampling frequency of the phase control circuit system becomes low, and the characteristics of the motor alone become a problem, making it impossible to obtain a large open-loop gain.

Therefore, it is essential to have a configuration that uses a speed control circuit to improve the characteristics of a single motor.Therefore, a known example of a motor servo circuit for a recording/reproducing disc player is shown in Fig. 1, and will be described in detail below. do. Incidentally, FIG. 2 is an operational waveform diagram of each part of the first speed control circuit 12 when the rotation speed is normal.

In Fig. 1, 1 is a disk, 2 is a mark signal for recording position alignment (hereinafter simply referred to as a mark signal) recorded in advance on the inner circumference of disk 1, and the external video signal is an odd field. The recording start point is aligned so that the mark signal position is about 7H (H: ~horizontal scanning period) before the vertical synchronizing signal (or even field). As is well known, this is to align the address signal (not shown) on the disc 1 with the overscan area on the playback screen and prevent the address signal from appearing on the playback screen. 5 is a photosensor made of an infrared light emitting diode or the like; 4 is a waveform shaping circuit that shapes the waveform of the mark signal; 5 is a phase control circuit; and 6 is a reference signal generation circuit. Delay circuit 7. First trapezoid waveform creation circuit 8. First sample and hold circuit9. 1st°0 phase compensation circuit 10. It is composed of a first sampling pulse generation circuit 11. 12 is a speed control circuit, and a limiter circuit 13. First mono-multi circuit (hereinafter referred to as M/8 circuit) 14. Counter circuit 15, clock signal generation circuit 16. The second? v
l/ht circuit 17. Second trapezoid waveform creation circuit 18. No.

2 sample hold circuit 19. Second phase compensation circuit 2
0. It is composed of a second sampling pulse generation circuit 21. 22 is an adder circuit, 25 is a motor drive circuit, 24
is a motor, and 25 is a frequency generator.

In such a system, when the disk 1 is rotated using a Tanabata starting circuit (not shown), the photosensor 3 detects the mark signal 2, which passes through the waveform shaping circuit 4 to the first sampling pulse generation circuit. A waveform-shaped mark signal is input to 11. On the other hand, the output signal of the reference signal generation circuit 6 is delayed by a sufficient amount of time in a delay circuit 7, roughly passed through a first trabezoid waveform generation circuit 8, and then inputted into a first temple hold circuit 9. In the sample hold circuit 9, the output signal of the first sampling pulse generation circuit 11 and the first
A phase comparison is made with the output signal of the trapezoid waveform generating circuit 8, and the error signal is amplified and processed through the first phase compensation circuit 10, and then input to the adder circuit 22.

Further, the speed control circuit 12 inputs the frequency generator output (FIG. 2A) linked to the motor 24 to the limiter circuit 15, and outputs the output (FIG. 2B) to the second sampling pulse generation circuit. 21 (the output signal is shown in Fig. 2G) and is led to the second sample and hold circuit 19, and the other one is connected to the first
It is input to the M/M circuit 14 of. The counter circuit 15 counts the output signal of the clock signal generation circuit 16 by a predetermined number in synchronization with the rising signal during the "H2 level" period of the output of the first M/M circuit 14 (FIG. 2C). 1 M
The waveform shown in the second diagram is obtained by returning the signal to the reset input of the /M circuit 14. The output pulse width due to the CR time constant of the first M/M circuit 14 should be longer than the count period Tc, and the "H" level is held during the count period Tc.
The output pulse width is limited by the reset signal. In addition, the second M/M circuit 17 (output signal processing shown in Fig. 2E),
A trapezoid waveform (FIG. 2F) is generated by inputting it to the trapezoid waveform generating circuit 18, and speed detection is performed in the second sample and hold cycle @19. At this time, by setting the starting point of the slope part of the trabezoid waveform (FIG. 2 F) near the rising part of the next frequency generator signal, the CR time constant of the trabezoid waveform creation circuit 18 is made as small as possible, and the temperature changes. This reduces recording position drift due to Although this configuration increases the number of components in the counter circuit 15, it has the advantage that there is little change in the count period Tc due to temperature.

The output signal of the second sample hold circuit 19 is
After being amplified and processed through the phase compensation circuit 2o, the signal is input to the addition circuit 22 together with the output signal of the phase control circuit 5. The motor 24 is controlled via a motor drive circuit 23.

However, when starting a motor in a conventional system like this,
There has been a problem that the motor locks at half the rotational frequency (90 rpm). This is due to a mechanism similar to a chip, and will be explained using FIG. In other words, when the motor rotation frequency is equal to or lower than the reciprocal frequency (1T") twice the count period Tc, the first M/M
When the power of the circuit 14 is 1 level, the reset signal of the output of the counter circuit 15 is always inputted at least once, and the first M/M circuit 14 is retriggered at the rising edge of the reset signal. Furthermore, commercially available M/M circuits have a function of being retriggered by the rising (or falling) signal of the reset input, and furthermore, the rotation frequency of Tanabata gradually increases. 8 (Fig. 5), when the frequency of the reciprocal of twice the count period Tc (2Tc) approaches, as shown in Fig. 5B, when the first M/M circuit 14 manual power is @H level, the counter circuit The reset signal (FIG. 5D) within the 15 output is input once, and the first M/M circuit 14 is retriggered at the rising edge of the signal (FIG. 5C').

In addition, in order to synchronize the timing of starting counting in the counter circuit 15 with the rise of the frequency generator signal, the first M
/M circuit 14 output is input to the reset terminal of the counter circuit 15, and as mentioned above, the first M/M circuit 1
4 is re-triggered and its output once becomes @H'' level, the counter circuit 15 receives this and starts counting, so that the counting operation in the counter circuit 15 is re-executed (see Fig. 5). D), second M/M circuit 17
The extra trapezoid waveform that does not correspond to the frequency generator signal (
As a result, a tofu bezoid waveform with twice the frequency of the frequency generator signal is generated at approximately equal intervals, as if it were rotating at the normal rotation speed, and the second sampling Pulse creation circuit 21 output (Figure 5G)
is what locks onto this extra trapezoid waveform.

In addition, the first M/M circuit 14, the counter circuit 15, and the clock signal generation circuit 16 are omitted, and instead, a new M/M circuit (not shown) is separately provided between the limiter circuit 15 and the second M/M circuit 17. The output pulse width is set, for example, to the count period TCK shown in the second diagram. As a result, the CR time constant of the trapezoid waveform generating circuit 18 can be made small, and the speed can be detected by the same operation as in the known example shown in FIG. This method has the advantage of a simple circuit configuration, but on the other hand, it
The CR time constant used to set the output pulse width in the circuit becomes thick, which causes the problem of large recording position drift due to temperature changes, as described above.

Note that related devices of this type include, for example,
Examples include JP-A-57-69425 and JP-A-5B-97156.

[Purpose of the invention]

The purpose of the present invention is to eliminate the drawbacks of the above-mentioned known examples, and to
To provide a speed detection circuit for a motor servo circuit that stably locks at a normal rotation speed after starting in the evening.

[Summary of the invention]

The main point of the present invention is to provide a first mono-multi circuit that sets the count start timing to prevent the counter circuit that sets the output timing of the speed detection trabezoid waveform from re-executing the counting operation when the motor is started. A second pulse having an output pulse width shorter than the count period is preceded by a second pulse having an output pulse width shorter than the count period.
The purpose is to provide a monomulti circuit.

In other words, when the motor is started, the rotational frequency is equal to the count period T.
Even if the frequency is below the reciprocal of twice a, the first mono-multi circuit output pulse that sets the count start timing of the counter circuit will go to "L" level at the rising edge of the reset signal of the counter circuit output. Another advantage is to provide a second monomulti circuit whose output pulse width is set to be shorter than the count period before the first monomulticircuit.

[Embodiments of the invention]

The present invention will be explained using an embodiment shown in FIG. Further, in FIG. 4, parts having the same functions as those in the known example shown in FIG. 1 are designated by the same numbers, and their explanations will be omitted. Note that FIG. 5 is an operational waveform diagram of each part of the fourth speed control circuit 12 when the motor is started.

In FIG. 4, reference numeral 26 denotes a fifth M/M circuit, which is set to have an output pulse width shorter than the count period by the counter circuit 15. In the same figure, the Tanabata pull-in operation by the phase control circuit 5 and the like (this is the same as the known example shown in FIG. 1 and is therefore omitted, and here, the description will focus on the trapezoid waveform generation mechanism in the speed control circuit 12).

In FIG. 4, the speed control circuit 12 inputs the output of a frequency generator 25 (FIG. 5A) linked to the motor 24 to the limiter circuit 15, and transmits the output (FIG. 5B) to the fifth M/M.
It is input to the circuit 26. Is this sixth M/M circuit 26 shorter than the count period Tc by the count circuit 15?
The output of the circuit 26 is sent to the second sampling pulse generation circuit 2.
1 to the second sample and hold circuit 19, and the other input to the first M/M circuit 14.

The counter circuit 15 receives the first M/M circuit 14 output (the 5th
After counting a predetermined number of output signals from the clock signal generation circuit 16 in synchronization with the rising signal in Figure D), the first M/M
By returning it to the reset input of the circuit 14, the waveform shown in FIG. 5E is obtained. At this time, even if the motor rotation speed is less than the frequency () which is the reciprocal of twice the count period Tc, as shown in FIG. Since the rising portion of FIG. 5E) is input, the first M/M circuit 14
is not retriggered. Therefore, re-execution of the counting operation in the counter circuit 15 can be prevented, and the counter circuit 15 can be prevented from re-executing the counting operation.
The output signal (Fig. 5E) is sent to the second M/M circuit 17 (the output signal is sent to the second M/M circuit 17 (Fig. 5F), and the second trapezoid waveform creation circuit 1
It is possible to obtain a trapezoid waveform (Fig. 5G) corresponding to the old frequency generator by inputting the same number of days. As a result, the speed is detected in the second sample hold circuit 19 using this trabezoid waveform and the output of the second sampling pulse generation circuit 21 ((2) in FIG. 5), and the rotation speed is locked to the normal rotation speed.

Furthermore, as shown in FIG. 6, a KWIt is configured to limit the output pulse width of the limiter circuit 15 by using a differentiating circuit 27 using a CR circuit and a waveform shaping circuit 28 instead of the fifth M/M circuit 26. Also good.

〔Effect of the invention〕

According to the present invention, in order to prevent re-execution of the counting operation of the counter circuit that sets the output timing of the trapezoid waveform for speed detection when the motor is started, the first monomulti circuit sets the count start timing. A second mono multi-circuit with an output pulse width shorter than the count period is provided in the preceding stage, and the motor stably performs the pulling operation to the normal rotation speed without locking the motor at half the rotation frequency.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional motor servo circuit, Figure 2 is a waveform diagram showing the operating waveforms of each part of the speed control circuit in Figure 1 at the normal rotation speed, and Figure 5 is when the motor in Figure 1 is started. A waveform diagram showing the operating waveforms of each part of the speed control circuit in
FIG. 4 is a block diagram of the first embodiment of the present invention, and FIG. FIG. 6 is a block diagram of a second embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Disk, 2... Mark signal for recording position alignment, 5... Phase control circuit, 12... Speed control circuit,
14... First M/M circuit, 15... Counter circuit, 16... Clock signal generation circuit, 17... Second M/M circuit, 18... Second trapezoid waveform creation Circuit, 24... Motor, 25... Frequency generator, 26
...Fifth M/M circuit, 27... Differential circuit.

Claims (1)

[Claims] 1. A limiter circuit that shapes the waveform of a frequency generator signal in conjunction with a motor, a mono-multi circuit that outputs a predetermined pulse width according to a rising or falling signal of the limiter circuit output, and a mono-multi circuit that A counter circuit that counts a predetermined number of reference signals in synchronization with the output pulse, and an output signal of the counter circuit that resets the monomulti circuit, and creates a trapezoid waveform from the output signal of the counter circuit to control the output of the limiter circuit. A speed detection circuit of a type in which a rising or falling signal is sampled and held using a detected signal, wherein a circuit for limiting the pulse width of the output of the limiter circuit is provided in the mono-multi circuit input stage. Servo speed detection circuit. 2. A speed detection circuit for a motor servo according to claim 1, wherein the circuit for limiting the pulse width of the limiter circuit output is comprised of a monomulti circuit or a differential circuit.