JPS61121518A - Converting circuit for input signal level - Google Patents

Abstract

PURPOSE:To drive an inverter circuit with a data signal of a low amplitude by combining two MISFETs and a capacitor. CONSTITUTION:Both FET 9 and 10 are turned on while a clock pulse of forward phase applied to a terminal 3 is kept at a high level. Then a capacitor 11 is charged with a data signal of a low amplitude of 0-1V. Then said clock pulse is changed to a low level and FET 9 and 10 are turned off. Thus the voltage level rises up at the drain side of the FET 10, and the electric charge charged to the capacitor 11 has no place to shunt. Therefore the data signal of 0-1V is changed to 1-2V for the input voltage of an inverter consisting of FET 12 and 13. As a result, an inverter consisting of FET 12 and 13 is driven. In such a way, an inverter circuit can be driven with a data signalof a low ampli tude.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to an input signal level conversion circuit that is capable of transmitting a data signal of a lower level than the signal level inside an integrated circuit.

Conventional configurations and their problems In circuits where analog circuits and digital circuits are mixed,
A phenomenon often occurs in which the signal-to-noise ratio (S/N ratio) of the analog signal is degraded due to the loop-around of the digital signal to the analog circuit.

For example, when a TTL level logic integrated circuit is mixed into a TV or video video signal circuit, the amplitude of the video analog signal is approximately 2Vp-p, while the amplitude of the digital signal of the logic integrated circuit is 5Vp-p. Since the waveform is a rectangular wave, it has wide frequency components, and depending on the mutual arrangement of analog signal lines and digital signal lines, analog signals can easily be interfered with by digital signals. This is especially true when the frequency of digital signals is high, so in circuits that mix conventional analog circuits and digital circuits, it is necessary not only to layout the printed circuit board but also to separate them using a shield case, which increases the cost. The drawbacks are that it increases the number of steps and man-hours.

Purpose of the Invention The present invention reduces the amplitude of digital signals in digital integrated circuits that are used in combination with analog circuits to prevent digital signals from interfering with analog signals, facilitates the mounting of electronic equipment, and provides a shield case. 0 Structure of the Invention The present invention has been made for the purpose of eliminating the above problems and reducing cost and man-hours. further, one terminal of a capacitor is connected to the connection point between the drain electrode of the first MIS transistor and the input terminal of the inverter, and the other terminal of the capacitor and the drain of the second MIS transistor are connected to each other. The input signal level according to the first aspect of the present invention is characterized in that the gate terminal of the first MIS type transistor and the gate terminal of the second transistor are connected to each other.
This embodiment will be described based on the circuit diagram of FIG. 1 and the timing diagram of FIG. 2. In FIG. 1, it is assumed that power supply terminal 1 is a power supply terminal on the integrated circuit side, and sV is applied thereto. The power supply terminal 2 is a power supply terminal to which a voltage lower than that of the power supply terminal 1 is applied, and it is assumed that 1V is currently applied thereto.

Now, clock pulses having voltage waveforms as shown in FIG. When an input as shown in FIG. 2C synchronized with the clock pulse is applied to the transistor 6, the connection line between the drain terminal 7 of the transistor 5 and the input terminal 8 of the input signal level conversion circuit according to the present invention is as shown in FIG. 2D. , Q~
A signal waveform with a voltage amplitude as low as 1 V appears. However, since the voltage waveform with a low amplitude as shown in FIG. 2d does not reach the drive level of the inverter, the integrated circuit cannot be operated as it is.

Therefore, the level of the low-amplitude data signal is converted to a level that can drive the input circuit composed of transistors 12 and 13 using on-off transistors 9 and 1o and capacitor 11 using positive-phase clock pulses. The drive level of the inverter configured with transistor 13 is normally such that the threshold voltage of transistor 13 as an enhancement driver is approximately 0. Since the threshold voltage of the transistor 12 as a TV voltage source node is approximately -2V, the input voltage at which the output becomes No) is approximately 1V.
．． 3v or less, the input that becomes low is approximately 1.7v or more.

In other words, to drive the inverter made up of transistors 12 and 13, it is only necessary to convert the level of a 0 to 1 V signal to about 1 to 2 V. In other words, when the positive-phase tarok pulse is at the 71 level, transistors 9 and 10 are activated. It is turned on to charge the capacitor 11 with a low amplitude data signal of Q~1V. Next, when the positive phase clock pulse becomes low level and transistors 9 and 1o are turned off, the voltage on the drain side of transistor 10 rises as shown in the voltage waveform θ in FIG. Then, since the charge charged in the capacitor 11 has no place to escape, the input voltage of the transistors 12 and 13 is as shown in the voltage waveform shown in FIG. The level is converted to 2V, and the inverter composed of transistors 12 and 13 is driven.

Note that the transistor 14 is controlled by a reverse-phase clock pulse, and when the inverter composed of transistors 15 and 16 has a positive-phase clock pulse at a high level, it outputs a data signal. It is provided so that it does not operate while the capacitor 11 is being charged, and it operates in the same way even if it is inserted into the input of the inverter made up of transistors 12 and 13, but considering the characteristics, Figure 1 The output voltage waveform that finally appears at the output terminal 1 is shown in Figure 2g.
The waveform will look like this.

Embodiment 2 An example of operating with a single power source will be described as a second embodiment with reference to FIG. 3.

In the circuit shown in Fig. 3, the diplenoid transistor 1
8 and 19 and the debrasion type transistors 20 and 2
1 is connected in series to obtain a low voltage such as 1V. ○One way to obtain a low voltage is to simply divide the power supply voltage using a resistor made of a diffusion layer or polysilicon. The method using depletion type transistors has the advantage that it can be made smaller and that the divided voltage does not easily fluctuate due to fluctuations in the power supply voltage.

The circuit shown in FIG. 3 has the same basic operation as the circuit shown in FIG. Easy to design according to characteristics.

Effects of the Invention As can be seen from the above explanation, the present invention makes it possible to reduce the amplitude of digital signals between metal-oxide film-semiconductor type digital integrated circuits that are used in combination with analog circuits. It has the effect of preventing interference with digital signals, making it easier to implement electronic equipment, and eliminating the need for conventionally necessary shield cases, which are rare, reducing costs and man-hours, and its industrial value is enormous. .

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a first embodiment of the input signal level conversion circuit according to the present invention, FIGS. 2a to 2g are diagrams showing voltage waveforms for explaining the operation of FIG. 1, and FIG. FIG. 3 is a circuit diagram of a second embodiment of the input signal level conversion circuit according to the invention; 5.9, 10, 13, 14, 16... Enhancement type transistor, 12, 15, 18° 19.2
0, 21, 22. 23...Depression type transistor.

Claims (1)

[Claims] The drain electrode of a first MIS transistor whose source electrode is an input terminal is connected to the input terminal of an inverter, and the connection point between the drain electrode of the first MIS transistor and the input terminal of the inverter is connected to one side of a capacitor. the other terminal of the capacitor and the drain terminal of the second MIS transistor;
An input signal level conversion circuit characterized in that a gate terminal of the first MIS type transistor and a gate terminal of the second transistor are connected.