JPS61121078U - - Google Patents

Info

Publication number
JPS61121078U
JPS61121078U JP422985U JP422985U JPS61121078U JP S61121078 U JPS61121078 U JP S61121078U JP 422985 U JP422985 U JP 422985U JP 422985 U JP422985 U JP 422985U JP S61121078 U JPS61121078 U JP S61121078U
Authority
JP
Japan
Prior art keywords
field
writing
memory
television device
reading
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP422985U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP422985U priority Critical patent/JPS61121078U/ja
Publication of JPS61121078U publication Critical patent/JPS61121078U/ja
Pending legal-status Critical Current

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  • Studio Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図……この考案の実施例のブロツク図、第
２図……その動作説明図、第３図……その読み出
し用切換信号を作成する回路の回路図、第４図…
…従来装置のブロツク図。 １……Ａ／Ｄコンバータ、２ａおよび２ｂ……
フイールドメモリ、３……Ｄ／Ａコンバータ、４
……切換スイツチ、ＳＷ１……書き込み用切換ス
イツチ、ＳＷ２……読み出し用切換スイツチ。 Fig. 1...Block diagram of an embodiment of this invention, Fig. 2...Explanatory diagram of its operation, Fig. 3...Circuit diagram of a circuit for creating the readout switching signal, Fig. 4...
...Block diagram of a conventional device. 1...A/D converter, 2a and 2b...
Field memory, 3...D/A converter, 4
...Selector switch, SW1...Write selector switch, SW2...Reader selector switch.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 小画面用ビデオ信号をフレームメモリに書き込
んだ後書き込み速度より速い速度で読み出すこと
により時間軸圧縮を行なう２画面テレビジヨン装
置に於て、フレームメモリとして各フイールド信
号を交互に記録する２つのフイールドメモリを備
え、両フイールドメモリの書き込みおよび読み出
しのタイミングをずらし一方のフイールドメモリ
の読み出しを行なつているとき他方のフイールド
メモリの書き込みを行なうようにしたことを特徴
とする２画面テレビジヨン装置。 Two field memories that alternately record each field signal as a frame memory in a two-screen television device that performs time axis compression by writing a small-screen video signal into a frame memory and then reading it out at a faster speed than the writing speed. 2. A two-screen television device, characterized in that the writing and reading timings of both field memories are shifted so that when one field memory is being read, the other field memory is being written.
JP422985U 1985-01-18 1985-01-18 Pending JPS61121078U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP422985U JPS61121078U (en) 1985-01-18 1985-01-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP422985U JPS61121078U (en) 1985-01-18 1985-01-18

Publications (1)

Publication Number Publication Date
JPS61121078U true JPS61121078U (en) 1986-07-30

Family

ID=30479603

Family Applications (1)

Application Number Title Priority Date Filing Date
JP422985U Pending JPS61121078U (en) 1985-01-18 1985-01-18

Country Status (1)

Country Link
JP (1) JPS61121078U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01157176A (en) * 1987-07-28 1989-06-20 Sanyo Electric Co Ltd Digital television receiver and data processor to be used by receiver

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01157176A (en) * 1987-07-28 1989-06-20 Sanyo Electric Co Ltd Digital television receiver and data processor to be used by receiver

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