JPS61120211A - Accuracy monitor method of sampling cycle - Google Patents

Abstract

PURPOSE:To monitor the presence or absence of a fault with high accuracy by measuring the width of a sampling cycle by the time decided by the executing time and frequency of an instruction word of a program and comparing the measured value with a standard for decision. CONSTITUTION:A circuit device which fetches the input information by sampling consists of a crystal oscillation circuit 1 which produces the master clock signal, a dividing circuit 2 which divides the master clock signal to produce the sample signal, a sample holding circuit 3 which fetches the analog input information synchronously with the sample signal, an A/D converting circuit 4, a memory 5 and a primary arithmetic unit 6. Then a specific program for monitor of sampling cycle accuracy is stored to a memory of the unit 6. This action is repeated by making use of the processing idle time. The specific program includes an increment instruction, a cycle shift deciding instruction and a branching instruction with repeats both said increment and deciding instructions. Then the program is measured by the time decided by the executing time of an instruction word. This measured value is compared with the upper and lower limit levels of the deciding standard. Thus the presence or absence of a fault can be monitored with high accuracy.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for monitoring the accuracy of a sampling period in a circuit device that takes in input information by sampling.

[Conventional technology]

Figure 3 shows a conventional example of this type of digital circuit device, where 1 is a crystal oscillation circuit that creates a master clock signal, and 2 is a crystal oscillation circuit that divides the master clock signal to create a sampling signal. 4 is a sample hold circuit that takes in analog input information in synchronization with the sampling signal, 5 is an A/D conversion circuit that operates in synchronization with the sampling signal, and 6 is a memory that stores the A/D converted information. ,
7 is a main processing unit.

In this circuit device, even if the crystal Q-oscillator circuit 1 operates normally and sends out a master clock signal, a deviation in the sampling period may occur due to a defect in the frequency divider circuit 2 or the like.

[Problem that the invention seeks to solve]

This sampling period deviation (accuracy) causes an error in the calculation results when the phase (time) relationship of input information is important, such as in digital filter calculations, so it is necessary to detect or monitor this. It is not easy to accurately detect periods at a micro level in terms of time, and the reality is that this type of monitoring is not performed.

This invention was made to solve the above problem.
It is an object of the present invention to provide a sampling period accuracy monitoring method that can easily detect sampling periods with high detection accuracy.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a program for specifying period accuracy monitoring, causes an arithmetic unit to execute it, measures the sampling period using the time calculated by the program's instruction execution time x the number of instruction executions, and measures the sampling period. The configuration is such that the deviation (accuracy) of the sampling period is determined based on the magnitude of the value.

[Operation] In this invention, the sampling period is measured using the instruction execution time and the number of instruction executions, which are uniquely determined by the master clock signal period, so that deviations in the sampling period can be detected easily and accurately. .

〔Example〕

FIG. 1 is a flowchart for explaining one embodiment of the present invention, and the monitoring program shown in this flowchart is stored in the program memory of the main processing unit 6 shown in FIG. This process is repeatedly executed every sampling period of the sampling signal, making use of the idle time for arithmetic processing, which is the original work of 6.

This monitoring program is a program that uses a master clock signal and executes instructions based on its cycle, including an increment instruction that counts up a certain variable, and a cycle deviation determination instruction that checks this count value (upper and lower limit values). ) and branch instructions that repeat these instructions. This monitoring programmer is activated by the first external interrupt signal synchronized with the sampling signal, and the main processing unit 6 executes the program according to the above flowchart.

That is, +11 When activated by the first external interrupt signal, the above variables are cleared to zero.

(2) Next, the variable is grounded by an increment instruction.

(3) When the sampling period elapses and the next external interrupt signal comes in, the count value is compared with the upper and lower limit values, and if there is a violation, an abnormality alarm process is performed and an alarm is issued. (4) If there is no conflict, clear the above variables to zero and proceed to (2) above.

The sampling period deviation determination operation is performed every sampling period, so if the sampling period is shorter than the correct sampling period TO in FIG. 2(a), the number of branches executed by the progera will be smaller than the count value decreases, and conversely, if the sampling period becomes longer, the count value increases.

By the way, the required execution time of a program is determined by the total product of the number of instructions and the execution time of the instruction word, and the execution time of an instruction word is a fixed time determined by the cycle of the master clock signal, and the execution time of an instruction word is Usually, it is extremely small compared to the sampling period.

In this embodiment, the time determined by the execution time and the number of branches (number of executions) is used as a sampling period measuring means, and the measured value is compared with the upper and lower limit values that are the judgment criteria. As mentioned above, the execution time is extremely small compared to the sampling period, and the monitoring program shown in the flowchart in Figure 1 can be a small-scale program with a small number of steps. The deviation can be monitored with high accuracy.

In addition, in the case where the original arithmetic processing of the main processing unit 6 is repeated at every sampling period, the same processing as shown in FIG.
), the fixed program for the calculation process (
The above-mentioned monitoring program may be added to a fixed program (with a fixed execution time); in this case, the sum of the required execution time of the fixed program and the required time of the above embodiment is compared with a determination criterion and monitored.

Note that in the above embodiment, the sample hold circuit, the A/D
Although the case where sampling information is supplied to the main processing unit through a converter has been described, it may also be supplied through a D/A converter, and the present invention can be applied to a device in which a program is processed based on the sampling period to achieve the same effect. Obtainable.

〔Effect of the invention〕

As explained above, this invention has a structure in which the length of the sampling period is determined by the execution time and the number of executions of program command words as a measuring means, and this measured value is compared with the judgment standard. It is now possible to monitor with high accuracy the presence or absence of abnormalities at the micro level in terms of time.Moreover, since the above program is based on software, the above program only needs to be small-scale, so the main calculation of the circuit device is Since the device and its program memory can be used, there is an advantage that the above effects can be obtained without adding any hardware for period accuracy monitoring.

[Brief explanation of drawings]

FIG. 2 is a time chart for explaining the determination operation of another embodiment of the present invention, and FIG. 3 is a block diagram showing an example of a digital device. In the figure, 1- crystal full circuit, 2- frequency divider circuit, 6-
Main processing unit. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (2)

[Claims] (1) In a circuit device in which information is sampled and input using a sampling signal created by frequency-dividing a master clock signal and processed by an arithmetic unit, a specific program whose instruction execution time is based on the master clock signal period is provided, The sampling period is measured as a means for measuring the time determined by the required execution time of a program instruction and the number of instruction executions in the sampling period, and the measured value is compared with a determination standard to monitor deviations in the sampling period. A method for monitoring the accuracy of the sampling period. (2) Claim 1, characterized in that the specific program is a small-scale program that includes an increment instruction for instructing to count up a certain variable, a judgment instruction for comparing the count value with a criterion, and a branch instruction. Method for monitoring the accuracy of the sampling period described.