JPS6111998A - Register - Google Patents

Abstract

PURPOSE:To show readable data quickly during shifting data of an FIFO by giving a flip-flop which is set by an output at the prescribed stage of a control register and reset when data is transferred from the prescribed stage by the output at a stage previous to the prescribed stage. CONSTITUTION:It is assumed that when all data registers 10-13 are filled with data, the data is sequentially read out. When the 3rd data is read out, a control register 22 shows that there is not data. At this time (a) only one datum remains. Afterward, when a read signal enters, both inputs of a NOR gate 40 go to a low level, and a flip-flop 30 is reset. Then, when the data is inputted and the readable state is attained, namely, when a control register 23 shows that there is data, the flip-flop 30 is reset again. While the value of the flip-flop is set, the data can be read out always, and the non-periodical delivery and receipt of data can be further facilitated.

Description

[Detailed Description of the Invention] ←Field of Industrial Application) The present invention relates to registers, particularly first-in-first-out registers (hereinafter referred to as FIF).
(denoted as O register).

(Prior Art) When data is transferred between asynchronous systems, data can be transferred without controlling individual data transfers by using a FIFO register as a buffer register. Such a FIFO register allows data to be accumulated up to the number of stages of the register by sequentially moving the data to the rear stage if there is no data in the previous stage of the register, and output is performed sequentially from the register at the rear stage.

Since high-speed operation is desired for such a FIFO for data transfer, a FIFO of a type in which data is shifted from a data input to a data output like a shift register is used.

FIG. 1 is a diagram explaining the prior art, in which a data register 10
, 11, 12.13 and control registers 20, 21
, 22, 23. The control registers 20 to 23 have a function of storing that data exists in that stage and a function of controlling data transfer based on the stored contents of the preceding and succeeding control registers.

The control registers 20, 21, 22, and 23 are connected in sequence and supply each other with a signal 1 necessary for shifting data.

A write signal is applied to the first control register 20. Further, a read signal is output to the control register 23 at the final stage.

A signal for data transfer control is applied from each control register to the data register at each stage.

Data registers 10, 11, 12, and 13 are connected in order, and the output of one stage becomes the data input of the next stage.

With this configuration, the input data is now in each data register to, 1
Consider an operation in which 16 pieces of data are read out when 1, 12, and 13 data are stored all at once.

FIG. 2 is a diagram showing the contents stored in the control register. If the storage contents of the control register indicate a high level when data is present, it can be seen that data is present in all register stages until time a.

Next, when a read signal is input, the data of the final stage is successively output and the control register 23 is reset, indicating that there is no data in the final stage. (This is K), data is transferred from the previous stage to the final stage, and in the same way, all data are transferred sequentially, and at the time, three data have been transferred to the data register 11,
12.13.

For example, when it is necessary to know whether there is valid data to be read next in Fl and FO with this configuration, even if the stored contents of the control register 23 at the final stage are referred to, there is no data available between time a and b. Cannot judge correctly.

(Problems to be Solved by the Invention) It is an object of the present invention to satisfy such a requirement (while the FIN "0" data is being shifted, there is data in the data register Ic in a predetermined stage that can be read immediately, or in a subsequent stage). This realizes a register that can indicate whether or not there is valid data.

(Means for Solving the Problems) According to the present invention, in a register in which a plurality of data registers, registers, and control registers corresponding thereto are connected in series, the output of a control register of a predetermined stage is set, and a predetermined value is set. To obtain a register having a clip-flop that is reset when data is transferred from a predetermined stage by the output of a control register at a previous stage of the stage.

(Example) Next, the present invention will be explained in more detail with reference to the drawings.

FIG. 3 shows an embodiment of the present invention, which includes four stages of data registers to, 11, 12, and 13, control registers 20, 21, 22, and 23, and a flip-flop 30.
and a non-gate 40. Data register 10. 11. 12゜13 and control register 2
0, 21, 22, and 23 have the same configuration as the conventional example shown in FIG.

In this embodiment, a 7-lip-flop 30 that indicates whether there is data is provided in the control register 23 of the data register 13 at the final stage.

A set signal for the flip-flop 30 is inputted from the storage circuit of the control register 23, and a reset signal for the 7-type flip-flop 30 is inputted from the NO&gate 40.

The read signal and the output of the storage circuit of the control register 22 are input to the NOR gate 4'0.

As shown in FIG. 4, it is assumed that data is sequentially read out when all data registers 10, 11, 12, and 13 contain data. When the third data is read, the control register 22 indicates that there is no data. At this time a, only one data remains, and when a read signal is input after that, both NOR gates 400A and 400A are at low level, and the shift flip and flop 30 are reset.

Next, the data is input and ready for reading.
Flip-flop 30 is set again when Citrol register 23 indicates data is present. While the value of this flip-flop is set, data can be read at all times, making aperiodic data exchange even easier.

(Effect of the invention) As described above, by adding a simple circuit, the FI has high utility value.
FO can be realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional example, and FIG. 6 is a timing chart of the output of a control register showing an example of the register contents. FIG. 3 is a block diagram showing one embodiment of the present invention, and FIG. 4 is a timing chart showing its operation. 10. Tools 1, 12, 13... Data register, 20.21. ．． 22, 23--Control register, 30--Flip-flop, 4
0...Inverter. Figure 1, 2 times, Figure 3, μ v = 4 @ Procedural amendment exported) 5゜59.10.30, 1979, Director General of the Patent Office, Mr. Sai 6゛1, Indication of the case, 1988 Patent application No. 132367 1. Name of the invention 3. Relationship with the person making the amendment Applicant: 5-33-1-4 Shiba, Minato-ku, Tokyo Agent: 5-37 Shiba, Minato-ku, Tokyo 108 No. 8: Seinari Mita Building In the "Detailed Description of the Invention" column of the specification to be amended, "0" on page 3, line 16 of the specification of contents of the amendment is input orally. ” is corrected.

Claims (2)

[Claims] (1) A multi-stage data register, which is connected to each stage and stores whether or not valid data exists in the data register of that stage, and if there is no data in the data register of the next stage based on the stored contents, A control register that controls the data transfer by transferring data to the next stage data register, and receiving the data if there is data in the previous stage data register when there is no data in this stage data register, and a control register of a predetermined stage. A stable state is achieved with an output indicating that there is valid data in the data register of that stage of the register, and when the data in the data register of that stage is transferred to the data register of the next stage, there is no data in the data register of the previous stage. A register characterized in that it has a flip-flop which is brought into another stable state under the condition that (2) The register according to claim 1, wherein the predetermined stage is a final stage.