JPS61118060A - Drive and control system for image sensor - Google Patents

Abstract

PURPOSE:To obtain always an output signal with an optimum level by obtaining a difference between the reference value and peak value of an output signal level over the scanning full picture elements at each end of main scanning corresponding to each line to change the main scanning period and the picture element read clock frequency. CONSTITUTION:Every time the main scanning corresponding to the line is finished, the peak value Vm of an output signal level over the entire picture elements at the scanning is compared with a reference voltage VR corresponding to the optimum output signal level by an analog comparator circuit 10. Through the result of comparison, an AND gate 7 or 8 is selected and a shift pulse phis front ridge detection signal is inputted to an up-down counter 6 from a timing circuit 11 via the selected AND gate 7 or 8. In case of Vm>VR, the count D of the counter 6 is incremented and when Vm<VR, the D is decremented. The period of the next main scanning and the picture read clock frequency are controlled by the count D.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention provides a method for controlling the light amount accumulation time for an image sensor so as to obtain an optimum output signal level.
& Image Seven sensor drive control method 2.

C Background of the Invention J For example, when detecting a circuit pattern, an image sensor that accumulates the amount of irradiation light is used as the detection means, but in this case, the image sensor outputs an output at an optimal level regardless of the incident illuminance Il'c. I need to get a signal.

The drive control system that has hitherto achieved the highest output signal level is disclosed in Japanese Patent Application Laid-open No. 58-17CN68. When using this method, the peak value of the output signal level common to all pixels in each main scan is captured, the difference between it and the reference value is calculated, and this difference is used as the error in the scanning speed. By adding to the period control circuit, the scanning period is controlled so that the peak value coincides with the reference value. However, although this method ultimately yields an optimal set meal cycle that matches the standard value, there is a restriction on the lower limit of the cycle, or control must be started from the lower limit, and furthermore, There are operational constraints such as having to calculate the difference between the value and the reference value using the scanning cycle control circuit.

[Purpose of the invention]

Therefore, an object of the present invention is to drive an image sensor that can obtain an optimal output signal level regardless of the incident illuminance without any operational restrictions! There is a K that provides the 111J method.

[Summary of the Invention J For this purpose, the present invention calculates the difference between the peak value of the output signal level over all #J elements in the Q-scan 3EIC every time the main scan for the line ends, and the reference value. The analog signal that controls the main scanning period and the frequency of the pixel readout clock is changed in steps according to the code. If the peak value does not meet the reference value KR, lower the frequency of the pixel successive clock and increase the main scanning period, and if the peak value exceeds the reference value, increase the frequency and increase the main scanning period. The idea is to control the analog signal in a stepwise manner at the end of the main scan in the direction of decreasing the value.

[Embodiments of the invention] The present invention will be explained below with reference to FIGS. 1 and 2.

First, before specifically explaining the present invention, an image sensor will be briefly explained. In principle, an image sensor consists of a photodiode array array and a shift register.The amount of photocharge accumulated in each photodiode by the shift pulse φS is transferred to the shift register, and the amount of photocharge is transferred in synchronization with the pixel readout clock CLK. is serially read out to the outside as an output signal corresponding to each pixel. Image sensors are classified into line type and area type depending on whether the photodiode array array is arranged one-dimensionally or two-dimensionally. The photoelectric charge amount is 5, which is read out in one column as an output signal corresponding to the pixel in synchronization with the pixel readout clock CLKK. Therefore, the output signal corresponding to the pixel that is currently being read out is the amount of photocharge due to the optical information accumulated before the shift pulse that transferred this output signal to the shift register, and the period of the shift pulse is small. In other words, as the main scanning speed increases, the output signal level corresponding to the pixel decreases, and as the main scanning speed decreases, the level increases.

Now, to explain the present invention in detail with reference to FIG.
A pulse output having a frequency corresponding to the control input voltage Vi++l is obtained from the F' converter 3. Based on this K, the drive pulse generation circuit 4 generates a shift pulse φS and a pixel successive tarlock CLK corresponding to the number of pixels. The sensor 1 is driven and controlled by these components. Depending on the pixel readout α clock CLK, an output signal 2 corresponding to the pixel can be obtained before the shift pulse, but on the other hand, the peak value vlI of this output signal 2 is detected and held by the peak value holding circuit 12. It looks like this. The peak value vll is obtained every time the main scanning for the line is completed, and is compared with the reference voltage vR corresponding to the optimum output signal level in the analog comparator circuit 10. Based on the comparison result, the up/down counter 6 is incremented by 1 or incremented by 1. It is now decremented.

That is, when v, > vR, the analog circuit 10 outputs its output and selects the AND gate 7, while v, <
If the output is vR, the AND gate 8 is selected via the inverter 9, and the φS leading edge detection signal from the timing circuit 11 is input to the up/down counter 6 via the selected AND gate. . In this case, F) V, > VR-c, and b-4, the count nLD of the up/down counter 6 is incremented, and v, <v
If it is H, the count value is decremented. Count f[Df'iD/ of up/down counter 6
Control human power Ef for the next main scan via A converter 5,
, Vtn to the V/F converter 3, the main scanning period (shift pulse φS period) and pixel successive clock CLK frequency are controlled. v, >
If it is VR, the light amount accumulation time in the image sensor 1 should be shortened (the output frequency of the V/F converter 3 is controlled by the button so that it becomes high, so that v is brought closer to vR). On the other hand, if v<vB, the light amount accumulation time should be increased.
The output frequency of the V/F converter 3 is controlled to be low, and (2) is brought closer to VRIc. If such control is performed every time the main scan is completed, the light amount accumulation time will be controlled every time the main scan is completed, and in the end, the voltage will have a peak of 1 V, which matches the reference voltage VR. The output signal level can be obtained. Note that the peak value holding circuit 12 is reset by φ from the timing circuit 11.
This is done by the S trailing edge detection signal.

FIG. 2 shows shift pulse φS% pixel read clock CL 5
This figure shows an example of the relationship between two levels of N output signals. In the case of the present invention, the period τφ of the shift pulse φS is controlled to optimize the light amount #integration time, and when the light amount accumulation time is optimally controlled, the peak t vm h of the output signal 2 matches the reference voltage vR. It becomes K to do.

The present invention is as described above, but when an output signal from an image sensor is processed by a computer, a peak value holding circuit, a timing circuit, an analog comparison circuit, an inverter,
AND gate, the up/down counter is replaced by a software program (replaceable D), D, the computer outputs the count value of the up/down counter based on shift pulses, etc.

〔Effect of the invention〕

As explained above, in the case of the present invention, no matter what the initial main scanning period is, the raw fixed period can be set as the optimum light amount accumulation time without any operational constraints within the performance range of the image sensor. This has the advantage that it can be controlled as much as possible, and an output signal with an optimal level can be obtained from the image sensor regardless of the incident illuminance.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of an example of an image sensor drive control circuit according to the present invention, and FIG. 2 is a diagram showing the relationship among an example of shift pulses, pixel readout clocks, and output signal levels according to the present invention. Deroru.

Claims (1)

[Claims] This method drives and controls an irradiation light accumulation type image sensor using a shift pulse and a pixel readout clock generated from a pulse signal from a voltage/frequency converter. After detecting and holding the peak value of the output signal level across the pixels, the difference between it and the reference value corresponding to the optimum output signal level is determined, and the control input voltage to the voltage/frequency converter is stepped in accordance with the sign of the difference. An image sensor drive control method characterized by the ability to change the image sensor.