JPS61117838A - Plasma chemical vapor deposition apparatus - Google Patents
Plasma chemical vapor deposition apparatusInfo
- Publication number
- JPS61117838A JPS61117838A JP23988384A JP23988384A JPS61117838A JP S61117838 A JPS61117838 A JP S61117838A JP 23988384 A JP23988384 A JP 23988384A JP 23988384 A JP23988384 A JP 23988384A JP S61117838 A JPS61117838 A JP S61117838A
- Authority
- JP
- Japan
- Prior art keywords
- recess
- wafer
- film
- electrode
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005229 chemical vapour deposition Methods 0.000 title description 4
- 239000012495 reaction gas Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims description 14
- 238000001947 vapour-phase growth Methods 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 3
- 238000007740 vapor deposition Methods 0.000 claims description 2
- 238000000927 vapour-phase epitaxy Methods 0.000 claims 2
- 238000000034 method Methods 0.000 abstract description 10
- 239000004065 semiconductor Substances 0.000 abstract description 8
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 235000012431 wafers Nutrition 0.000 description 37
- 239000007789 gas Substances 0.000 description 6
- 230000001681 protective effect Effects 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 241000257465 Echinoidea Species 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- RCJVRSBWZCNNQT-UHFFFAOYSA-N dichloridooxygen Chemical compound ClOCl RCJVRSBWZCNNQT-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910005091 Si3N Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
Abstract
Description
【発明の詳細な説明】
イ、産業上の利用分野
この発明は半導体基板（ウェハー）の表面に気相で膜を
成長させる平行電極型プラズマ気相成長装置の基板を支
持する下部電極の構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application This invention relates to the structure of a lower electrode that supports a substrate in a parallel electrode type plasma vapor phase growth apparatus for growing a film in the vapor phase on the surface of a semiconductor substrate (wafer). It is something.
口、従来技術
ＩＯ，ＬＳＩ等を製造する半導体のプロセスにおいては
半導体ウェハーの表面ｆこ窒化シリコン（ＳｉａＮ４）
、酸化シリコン（Ｓｉ０２）等の膜を形成し、この膜
を絶縁膜、パッシベーション膜、保護膜等として用いる
場合が非常に多い。この種の膜を形成するのにはウェハ
ーの温度が比較的低温で膜形成ができるプラズマＣＶ
Ｄ 法（ＰｌａｓｍａＣｈｅｍｉｃａｌ Ｖａｐｏｒ
Ｄｅｐｏｓｉｔｉｏｎ 、以下Ｐ−ＣＶＤ法という）が
一般的に用いられている。Ｐ−ＣＶＤ法の装置には円筒
型と平行平板電極型の２種類がある。平行平板電極型の
プラズマ気相成長装置は第３図に示すように真空室（１
）内に対向して上部電極（２）と下部電極（サセプター
）（３）をもうけ、サセプター（３）の上にウェハー（
５）を載せて、真空室内を真空パイプ（４）から排気し
て室内を真空にし、次ぎに反応ガス導入パイプ（６）か
ら反応ガスを送入して上部電極（２）の下面の孔（７）
から吹き出させる。上下電極の間に高周波電圧を印加し
て電極間の空間にプラズマを発生させてガスを反応させ
その生成物をウェハー（５）の上に堆積させて膜を形成
せしめるようになっている。In the semiconductor process for manufacturing IO, LSI, etc., the surface of the semiconductor wafer is made of silicon nitride (SiaN4).
In many cases, a film of silicon oxide (Si02) or the like is formed and used as an insulating film, a passivation film, a protective film, etc. To form this kind of film, plasma CV, which can form a film at a relatively low wafer temperature, is used.
D method (PlasmaChemical Vapor
(hereinafter referred to as P-CVD method) is commonly used. There are two types of P-CVD equipment: a cylindrical type and a parallel plate electrode type. The parallel plate electrode type plasma vapor phase growth apparatus has a vacuum chamber (1
) with an upper electrode (2) and a lower electrode (susceptor) (3) facing each other, and a wafer (
5), the vacuum chamber is evacuated from the vacuum pipe (4) to create a vacuum, and then a reaction gas is introduced from the reaction gas introduction pipe (6) to fill the hole ( 7)
Make it blow out. A high frequency voltage is applied between the upper and lower electrodes to generate plasma in the space between the electrodes, causing gases to react and depositing the products on the wafer (5) to form a film.
ハ０発明が解決しようとする問題点
ところがこの平行平板電極型の装置ではウニ／％−（５
）をサセプター（３）上に配置するので、膜を形成する
時ウェハー（５）の表面だけでなくサセプター（３）の
ウェハーに覆われない他の表面にも反応生成物が堆積す
る。即ち一回膜形成操作を行うとサセプター（３）の表
面が汚染され清浄でなくなる。従ってそのま・ま次ぎに
ウェハーの表面に膜の形成をしようとするとウェハーの
面がサセプターの汚染部分（堆積物のある部分）に直接
接融してウェハー自体の表面が汚染されたり傷がついた
りするのでプロセス上問題である。However, in this parallel plate electrode type device, sea urchin/%-(5
) is placed on the susceptor (3), so when forming a film, reaction products are deposited not only on the surface of the wafer (5) but also on other surfaces of the susceptor (3) that are not covered by the wafer. That is, when the film forming operation is performed once, the surface of the susceptor (3) becomes contaminated and becomes no longer clean. Therefore, if you try to form a film on the surface of the wafer one after another, the surface of the wafer will directly fuse to the contaminated part (part with deposits) of the susceptor, and the surface of the wafer itself will be contaminated or scratched. This is a process problem.
特に例えばＧ５Ａｓウェハーのようにアニール保護膜の
ように表裏の両面に膜を形成する必要がある場合（アニ
ールの際のＡｓの蒸発防止と保護膜として形成する主と
してＳ蓼の膜であり、蒸発防止と共に半導体ウェハーの
熱膨張率の差による基板の割れ、そり、保護膜の亀裂防
止等のため両面に必要である）にはウェハーを裏返しし
て膜形成するので裏面に形成した膜に汚れや傷がつく等
の問題があった。Especially when it is necessary to form a film on both the front and back surfaces such as an annealing protective film such as G5As wafer. At the same time, it is necessary on both sides to prevent cracks in the substrate, warping, cracks in the protective film, etc. due to differences in the thermal expansion coefficient of semiconductor wafers).Since the film is formed by turning the wafer over, there is no chance of dirt or scratches on the film formed on the back side. There were problems such as sticking.
これに対しては従来は毎回の処理毎にサセプターを交換
したり、Ｓｉ基板を下に敷いてその上に半導体ウェハー
を置き下敷きのＳｉ基板を処理毎に交換したりしている
。しかしながら何れの場合も多くの部品が必要でコスト
が掛かるし、前者の場合は交換の作業が繁雑であり時間
を要し、後者の場合には更にウェハーが滑り易い欠点が
ある。Conventionally, to deal with this, the susceptor has been replaced after each process, or a Si substrate has been placed underneath, a semiconductor wafer has been placed on top of the susceptor, and the underlying Si substrate has been replaced after each process. However, in either case, many parts are required and the cost is high; in the former case, replacement work is complicated and time-consuming; and in the latter case, there is a further drawback that the wafer is prone to slipping.
二０問題点を解決するための手段
この発明はプラズマ気相成長装置（Ｐ −ＣＶＤ装置）
のサセプターに２段の凹部をもうけ、上段の凹部と凹部
の肩部によってウエノ１−を固定し、凹部下段は真空室
とバルブを通して連結して同時に排気して真空とし、次
ぎにバルブを閉じて前記連結を遮断して該凹部下段を真
空に保持しつつ真空室に反応ガスを供給してＰ−ＯＶＤ
法によって膜形成を行う下部電極構造によって従来法の
欠点を解消したＰ−ＯＶＤ法を提供するものである。20 Means for Solving Problems This invention is a plasma vapor deposition apparatus (P-CVD apparatus)
A two-stage recess is formed in the susceptor, and the Ueno 1- is fixed by the upper recess and the shoulder of the recess.The lower recess is connected to a vacuum chamber through a valve and is simultaneously evacuated to create a vacuum.Then, the valve is closed. P-OVD is performed by cutting off the connection and supplying a reaction gas to the vacuum chamber while maintaining the lower part of the recess in a vacuum.
The present invention provides a P-OVD method that eliminates the drawbacks of the conventional method by using a lower electrode structure in which film formation is performed using the P-OVD method.
以下図面を用いて本発明を説明する。The present invention will be explained below using the drawings.
第１図に示すように、真空室（１）内に１部電極（２）
及び下部電極（３）がもうけられ、該室は真空パイプ（
４）を通して真空ポンプ０のにより真空に排気される。As shown in Figure 1, one electrode (2) is placed inside the vacuum chamber (1).
and a lower electrode (3), and the chamber is connected to a vacuum pipe (
4) is evacuated to vacuum by vacuum pump 0.
また上部電極から反応ガスを導入して電圧を印加しＰ−
（４Ｄ法による膜の形成を行うようになっていることは
従来構造と同じである。In addition, a reactive gas is introduced from the upper electrode and a voltage is applied to P-
(The structure is the same as the conventional structure in that the film is formed by the 4D method.
第２図にＡ部詳細断面を示すように、サセプター（３）
の上面に２段の凹部がもうけられているっ凹部上段（８
）の外形はウェハーを固定できる外形とし、深さはウェ
ハーの厚さより小さくしである。凹部下段（９）の大き
さは凹部上段（８）より小さく、凹部上段（８）と凹部
下段（９）との間には肩部が形成されている。一般に肩
部の幅は５Ｈ程度であり、ウエノ＼−を凹部上段に嵌め
込むと、ウェハーの直径にもよるが、ウェハーの外周が
肩部により２〜５羽の幅で支持されるようになっている
。凹部下段（９）の底部には真空引き用の孔路ａ０がも
うけられ、多数の凹部はその孔路で連結され更に孔路Ｑ
Ｏは集合してサセプター支持部の中を通って真空バルブ
０υを介して真空室の真空パイプ（４）に連結されてい
る。As shown in Fig. 2, the detailed cross section of section A, the susceptor (3)
There are two recesses on the top surface of the upper recess (8).
) has an external shape that allows the wafer to be fixed, and the depth is smaller than the thickness of the wafer. The size of the lower recess (9) is smaller than the upper recess (8), and a shoulder is formed between the upper recess (8) and the lower recess (9). Generally, the width of the shoulder is about 5H, and when the wafer is fitted into the upper part of the recess, the outer periphery of the wafer is supported by the shoulder with a width of 2 to 5, depending on the diameter of the wafer. ing. A hole passage a0 for vacuuming is provided at the bottom of the lower stage (9) of the recess, and a large number of recesses are connected through the hole passage Q.
0 collectively pass through the susceptor support and are connected to the vacuum pipe (4) of the vacuum chamber via the vacuum valve 0υ.
この装置を使用するには、サセプターの凹部上段（８）
に膜を形成すべき面を上にして嵌め込み固定する。次ぎ
に真空バルブαυを開放したまま真空ポンプ（２）によ
って真空室（１）内の真空引きを行うが同時に凹部下段
（９）も真空となる。真空度が充分に上がった時に真空
バルブαυを閉じて、反応ガスを上部電極（２）より導
入しプラズマを発生させてウェハー（５）の表面に膜を
形成する。膜が形成されると反応ガスの導入を止めて残
留反応ガスを真空排気し、次ぎに真空バルブαυを開放
し、その状態で空気或いは窒素等の不活性ガスを導入し
てウニ／−−（５）を取り出して膜の形成を完了する。To use this device, open the upper recess (8) of the susceptor.
Insert and fix with the side on which the film is to be formed facing up. Next, the vacuum chamber (1) is evacuated by the vacuum pump (2) while the vacuum valve αυ is left open, and at the same time, the lower part (9) of the recess is also evacuated. When the degree of vacuum is sufficiently increased, the vacuum valve αυ is closed, and a reaction gas is introduced from the upper electrode (2) to generate plasma and form a film on the surface of the wafer (5). When a film is formed, the introduction of the reaction gas is stopped and the residual reaction gas is evacuated. Next, the vacuum valve αυ is opened, and in this state, air or an inert gas such as nitrogen is introduced to remove the sea urchin/--( 5) is taken out to complete the film formation.
次ぎに必要な場合にはウェハー（５）を裏返しして前記
と同様の操作によってウェハー（５）の裏面に膜を形成
する。Next, if necessary, the wafer (5) is turned over and a film is formed on the back surface of the wafer (5) by the same operation as described above.
この装置によれば凹部の肩部が常にウェハーによって覆
われているので肩部に堆積物が生ずることはない。しか
し肩部にリング状の金属板等を置いておくと肩部がより
清浄に保持でき、あるいは安価な金属製のリングの交換
によりウェハーの汚染を防止することができる。According to this device, the shoulders of the recesses are always covered by the wafer, so that no deposits are formed on the shoulders. However, if a ring-shaped metal plate or the like is placed on the shoulder, the shoulder can be kept cleaner, or the wafer can be prevented from being contaminated by replacing the inexpensive metal ring.
一般に反応ガスを導入して反応を行わせる時の圧力はＩ
Ｔｏｒｒ以下であり、ウェハーを周囲のみで支持して
もウェハーの表裏の圧力差による変形を生ずることはな
い。しかし凹部下段の上部に格子状の枠やその他の支持
体をもうけると反応時にウェハーの表裏の圧力差が大で
あってもウェハーの変形を避けることができる。Generally, the pressure when introducing a reaction gas to carry out a reaction is I
Torr or less, and even if the wafer is supported only by its periphery, no deformation will occur due to the pressure difference between the front and back sides of the wafer. However, if a grid-like frame or other support is provided above the lower part of the recess, deformation of the wafer can be avoided even if there is a large pressure difference between the front and back sides of the wafer during reaction.
ホ、実施例
ＧａＡ、ｓ半導体のウェハーの両面に熱処理時の保護膜
として５ｉＮｌｊを平行電極型気相成長装置を用いてＰ
−ＣＶＤ法により形成した。その場合に従来の下部電極
及び本発明の下部電極の両者を用いて試料を作成し、熱
処理後の膜の状態を観察比較した。E. EXAMPLE 5iNlj was deposited on both sides of a GaA, s semiconductor wafer as a protective film during heat treatment using a parallel electrode type vapor phase growth apparatus.
- Formed by CVD method. In this case, samples were prepared using both the conventional lower electrode and the lower electrode of the present invention, and the state of the film after heat treatment was observed and compared.
即ち試料として市販の両面を鏡面に研磨したＧａＡｓ基
板を用い、これを硫酸系エツチングして真空室内の下部
電極に固定し、真空引きを行ったあと・５ｉＪ（４・Ｎ
Ｈ３、Ｎ２ガスを導入し、プラズマを発生させて、基板
の温度を約２８０’Ｃに保持しつつ基板表面に屈折率約
１．９の８ｉ３Ｎ４膜を約１２００人の厚さに形成した
。次ぎにウエノ１−を裏返しして同様の操作により裏面
ににも同じＳｉ３Ｎ４膜を形成した。That is, using a commercially available GaAs substrate with both sides mirror-polished as a sample, etching it with sulfuric acid and fixing it to the lower electrode in a vacuum chamber, and after evacuation,
H3 and N2 gases were introduced, plasma was generated, and an 8i3N4 film having a refractive index of about 1.9 and a thickness of about 1200 mm was formed on the surface of the substrate while maintaining the temperature of the substrate at about 280'C. Next, Ueno 1- was turned over and the same Si3N4 film was formed on the back side by the same operation.
このプロセスを前記のように従来の下部電極と本発明の
下部電極を用いて行い、２枚の試料を得た。This process was carried out as described above using a conventional bottom electrode and a bottom electrode of the present invention to obtain two samples.
この試料２枚をＮ２ ｉス雰囲気中で８２０°Ｃｌ２Ｏ
分間熱処理を施した。These two samples were heated at 820°Cl2O in a N2 gas atmosphere.
Heat treatment was performed for a minute.
熱処理後の膜の状態を顕微鏡によって観察したところ、
従来装置のものでは所々にキズや汚れによる膜のハガレ
が見い出されたが本発明の装置による試料の膜は完全で
変化が発見されなかった。When we observed the state of the film after heat treatment using a microscope, we found that
In the case of the conventional apparatus, peeling of the film due to scratches and dirt was found here and there, but the film of the sample using the apparatus of the present invention was intact and no change was found.
へ１発明の効果
以上にくわしく説明したように本発明の下部電極構造の
平行電極型気相成長装置によれば、ウェハーにＳｉ３Ｎ
４ 、５ｉ０２等の膜を形成する際、膜を形成する面と
反対側の面は反応中はガスに触れることなく且つ直接サ
セプターと接触せず又ウェハーの周囲でサセプターと接
触する表面部分は常にウェハーに覆われていて堆積物は
生ぜず、従って膜を形成する反対の面は常に清浄である
。従って片面を清浄に保ったまま他の面に膜を形成する
場合やウェハーを裏返しして両面に膜を形成する場合に
も表面及び膜にキズ、汚れがつくことがない。1. Effects of the Invention As explained in detail above, according to the parallel electrode type vapor phase growth apparatus with the lower electrode structure of the present invention, Si3N is deposited on the wafer.
When forming a film such as 4 or 5i02, the surface opposite to the surface on which the film is formed does not come into contact with gas or directly contact the susceptor during the reaction, and the surface area around the wafer that comes into contact with the susceptor is always Covered by the wafer, no deposits form, so the opposite side on which the film is formed is always clean. Therefore, even when a film is formed on one side while keeping it clean, or when a wafer is turned over and a film is formed on both sides, the surface and film will not be scratched or contaminated.
例えばＧａＡＳウェハーの場合に熱処理用保護膜（Ａｓ
の蒸発を防止するための）としてＳｉ３Ｎ４保護膜を両
面に形成する場合等には表面の汚れによる膜のハガレや
割れが発生することがない。即ち本発明の装置は半導体
ウェハーの表面にＰ−ＣＶＤ法により確実にキズのない
膜を形成できる非常に有効なものである。For example, in the case of GaAS wafers, a heat treatment protective film (As
When a Si3N4 protective film is formed on both sides (to prevent evaporation of the film), peeling or cracking of the film due to surface dirt will not occur. That is, the apparatus of the present invention is very effective in that it can reliably form a scratch-free film on the surface of a semiconductor wafer by the P-CVD method.
第１図は本発明のプラズマ気相成長装置の断面図、第２
図はその下部電極のＡ部詳細断面図、第３図は従来のプ
ラズマ気相成長装置の断面図である。
（１）・・・真空室、 （２）・・・上部電極
、（３）・・・下部電極、サセプター、
（４）・・・真空パイプ、（５）・・・ウェハー、基板
、（６）・・・ガス導入パイプ、 （７）・・・孔、（
８）・・・凹部上段、 （９）・・・凹部下段、
００・・・孔路、 ０υ・・・真空バルブ、
（６）・・・真空ポンプ。
代理人 弁理士 １）中 理 夫
第１図
↓
第２図
第３図Fig. 1 is a sectional view of the plasma vapor phase growth apparatus of the present invention, Fig.
The figure is a detailed sectional view of part A of the lower electrode, and FIG. 3 is a sectional view of a conventional plasma vapor phase growth apparatus. (1)...Vacuum chamber, (2)...Upper electrode, (3)...Lower electrode, susceptor, (4)...Vacuum pipe, (5)...Wafer, substrate, (6 )...Gas introduction pipe, (7)...hole, (
8)... Upper part of the recess, (9)... Lower part of the recess,
00...hole, 0υ...vacuum valve,
(6)...Vacuum pump. Agent Patent Attorney 1) Rio Naka Figure 1 ↓ Figure 2 Figure 3
Claims (3)
部電極（サセプター）に２段の凹部をもうけ、凹部上段
は基板（ウェハー）を固定する外形とし、凹部下段は電
極内を通る孔路により連結すると共に該孔路は真空バル
ブを通じて装置の真空パイプと連結してあり、基板を凹
部の肩部に支持して真空排気時には凹部下段の空気を排
気し膜形成時は真空バルブを閉じて反応ガスが基板の裏
面に回り込まないようにした構造を有することを特徴と
するプラズマ気相成長装置1. In a parallel plate electrode type plasma vapor phase epitaxy apparatus, a lower electrode (susceptor) has two recesses, the upper recess has an outer shape for fixing the substrate (wafer), and the lower recess is connected by a hole path passing through the electrode. The hole passage is connected to the vacuum pipe of the apparatus through a vacuum valve, and when the substrate is supported on the shoulder of the recess, the air from the lower part of the recess is evacuated during vacuum evacuation, and when the film is formed, the vacuum valve is closed and the reaction gas is released from the substrate. A plasma vapor phase epitaxy apparatus characterized by having a structure that prevents it from going around to the back side of the plasma vapor deposition apparatus.
リングを敷くことを特徴とする特許請求の範囲第１項記
載のプラズマ気相成長装置2. A plasma vapor phase growth apparatus according to claim 1, characterized in that a clean metal ring is placed between the shoulder of the recess of the lower electrode and the substrate.
もうけたことを特徴とする特許請求の範囲第１項もしく
は第２項記載のプラズマ気相成長装置3. A plasma vapor phase growth apparatus according to claim 1 or 2, characterized in that a lattice-shaped substrate support part is provided above the lower part of the recess of the lower electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23988384A JPS61117838A (en) | 1984-11-14 | 1984-11-14 | Plasma chemical vapor deposition apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23988384A JPS61117838A (en) | 1984-11-14 | 1984-11-14 | Plasma chemical vapor deposition apparatus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61117838A true JPS61117838A (en) | 1986-06-05 |
Family
ID=17051295
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23988384A Pending JPS61117838A (en) | 1984-11-14 | 1984-11-14 | Plasma chemical vapor deposition apparatus |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61117838A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2021170615A (en) * | 2020-04-17 | 2021-10-28 | 三菱電機株式会社 | Satellite and method for manufacturing silicon carbide semiconductor device |
-
1984
- 1984-11-14 JP JP23988384A patent/JPS61117838A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2021170615A (en) * | 2020-04-17 | 2021-10-28 | 三菱電機株式会社 | Satellite and method for manufacturing silicon carbide semiconductor device |
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