JPS61117653A - Data processor - Google Patents

Abstract

PURPOSE:To shorten the instruction execution time by providing an oscillator which generates a reference signal having a period of 1/(an integer) of that of the clock signal of a microprocessor, a frequency divider, etc. to extend the clock period. CONSTITUTION:An oscillated output signal 100 of an oscillator 1 is inputted to the shift pulse input of a shift register 2 and an input of an AND gate 4. The phase in the register 2 is shifted successively by a time equal to the period of the shift pulse of the signal 100, and signals 102 and 103 are outputted and are inputted to a NAND gate 3. An output signal 105 is inputted to a reset input terminal RS synchronized with the shift pulse. An output signal 104 of the gate 3 is inputted to the AND gate 4, and an output signal 106 of the gate 4 is inputted as a signal 107 to a microprocessor 6 through a frequency divider 5. In such a case, the signal 100 has a quarter period of the signal 107, and the clock period can be extended.Thus, the instruction execution time is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device that controls data acquisition timing of a microprocessor.

[Conventional technology]

2. Description of the Related Art Conventionally, as a data processing device using a microprocessor, there is one shown in FIG. 3, for example. In the figure, 20 is a microprocessor, 21 is a clock signal generation circuit, and 22
2 is a wait control, 23 is a memory, and 24 is an input/output interface. When it is necessary to adjust the access time of the memory 23 or the response time of the input/output ink 7ace 24 and the read timing of the microprocessor 20, a cycle for waiting (hereinafter simply referred to as a wait cycle) is used. A method has been used in which the data acquisition time is delayed by inserting one or more cycles.

[Problems to be solved]

In the conventional data processing device described above, the time of one wait cycle is equal to the period of the clock signal supplied to the microprocessor, and therefore the adjustment of the read timing of the microprocessor is limited to an integral multiple of the period. It had been. For this reason, the arrival time of data from the memory 23 or the input/output interface 24 to the data input terminal of the microprocessor 20 and the microprocessor 7? If the difference between the reading timing and the reading timing in 20 is extremely small compared to the clock cycle, the disadvantage is that inserting a wait cycle delays the reading timing by one clock cycle, increasing the instruction execution time. .

Solution to Problem C] The present invention solves the above-mentioned conventional problems, and expands the clock period by the minimum necessary time during the i-syncycle, when the microprocessor needs to adjust the timing at which data is read from the data bus. Therefore, it is an object of the present invention to provide a data processing device that can synchronize timing with memory or Ilo without inserting wait cycles, thereby shortening instruction execution time. The means for this purpose includes an oscillator that generates a basic S signal having a cycle that is an integer fraction of the clock signal of the microprocessor, and an output signal of the oscillator that is frequency-divided to a predetermined frequency to generate a microprocessor signal. The supply of the reference signal to the frequency divider and the reference signal to the frequency divider is stopped for one reference signal period or more in response to a clock period extension request signal output from the microprocessor. It is an object of the present invention to provide a data processing device having a clock supply means for extending a signal period by a time equivalent to one reference signal period or more.

[Actual development 1 Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a time chart showing the waveforms of each signal twin 100 to 107 in this embodiment.

In this embodiment, the oscillator 1. Shift register 2. N^ND gate 3. AND gate 49 divider 5. and a microprocessor 6.

In diagram K1, the oscillation output signal of oscillator l is 100 Fi,
Shift pulse input (CK) of shift register 2 and AND
There are 40 gate inputs. 77 Tresister VC Oite, Q person, QB, QO, QD, Qx, Qy,
Qa.

and QH are output terminals, and a signal whose phase is sequentially shifted by 77 times for a period equal to the period of the input shift pulse is obtained, and signals 102 and 103 from the Qa shift and Qa ratio output terminals are sent to the NAND gate 3. I am typing. Further, the signal from the Qg output terminal is input to the shift pulse synchronization reset input terminal (R8) of the input register. QG, Q) i Fi is a negative logic salt, and the old man is a positive logic.

The output signal 104 of the NAND gate 3 becomes one input of the AND gate 4, and the output signal 106 if of the armpit AND gate 4 is input to the frequency divider 5, and the output signal 107 of the frequency divider 5 is , are input to the clock signal input terminal (CK) of the microprocessor 6. The output signal 101 of the microprocessor 76 is input to the data input terminal (SD) of the shift register 2.

Here, the output signal 101 of the microprocessor 6 is an output signal representing the operation code 7 etching cycle during the instruction cycle. SD). However, the signal is arbitrary, and for example, a memory access request signal or an input/output request signal output from a microprocessor may be used without any problem. It is also assumed that the signal is a valid signal.

In this embodiment, the oscillation output signal 100 of the oscillator 10 is one quarter of the period of the clock signal 107 of the microprocessor 6.
The period is the frequency division of the frequency divider 5 *I divided by 4.

The second factor (in which the single-dot chain #J is the clock signal 10701
Representing periods, each period is 7'+, T2. The microprocessor 6 is expressed as Tl, 'h, Ti
The operation code 7 is formed in the TIFi next machine cycle (not necessarily the operation code fetch cycle) after Ts.
belongs to. In the microprocessor 6Fi and the operation code 7, it is assumed that data is read from the path when the clock signal that transitions from Tx to Ts makes a state transition from logic JIO to logic I.

Now, the operation of this embodiment will be explained.

Now, in 'J', if the signal 101 indicating that the microprocessor 6 has entered the operation code 7, has transitioned to the logic ff11 state as shown in the IEZ diagram, then the signal 101 indicates that the microprocessor 6 has entered the operation code 7 Since it is input to the shift data input terminal, the output signals 102 and 103 F of the output terminals Q1 and Qo of the shift register 2
i, the output is shifted by a specified phase, and as shown in FIG.
The signal 103 transitions from a logic 1 to a logic 0 after a time equal to one period of the signal 102, and the signal 103 transitions from a logic 1 to a logic 0 after a time equal to one period of the signal 100. Therefore, as mentioned above, signal 104 is the negation of the logical sum of signal 102 and signal 103, so signal 102 is logic 1.
When the signal 103 transitions to logic 0, it transitions to logic 0, and when signal 103 transitions to logic 0 with a delay, it becomes logic again! Transition to 1. Therefore, since the signal 104 is the other human signal of the AND gate 4 into which the output signal 100 of the oscillator 1 is input, the output signal 106 of the AND gate 4 is It becomes a logical 0 state.

Then, after signal 103, when signal 105 transitions to logic 0, since signal 105 is connected to the shift pulse synchronization reset terminal of shift register 2, all outputs of shift register 2 are activated. Then, the signal 100, which is a shift pulse, changes from logic 0 to logic l.
Condition to! It is reset in synchronization with 1 transition. Therefore (, A
The output signal 106 of the ND gate 4 is shown as shown in FIG. 2, and the clock input signal 107 of the microprocessor 6, which is obtained by dividing this signal by 1/4, is extended by one cycle of the output signal 100 of the oscillator 1 in the Tz interval. be done.

Therefore, the microprocessor 6 of this embodiment has T! The data loading timing will be delayed by the length of time the section is extended.

By the way, in this embodiment, the division ratio is set to 1/4 and NAND
The input signals 102 and 103 of the gate 3 are taken out from the shift registers Qy and Qo, but these can be set freely, and the resulting delay time is arbitrary.

〔Effect of the invention〕

As described above, according to the present invention, there is provided an excavator that generates a reference signal having a cycle that is an integer fraction of a clock signal of a microprocessor, and an output signal of the oscillator that is set at a predetermined ratio f1.
．． a frequency divider that generates a clock signal for the microprocessor, and in response to a clock cycle extension request signal output from the microprocessor, stops clock supply to the frequency divider for one reference signal cycle or more; Since the configuration includes a clock supply control means that extends the clock signal period of the microprocessor by more than the equivalent of one reference signal period, the data read timing of the microprocessor is not limited to the period of the clock signal input to the microprocessor. This has the effect of reducing the instruction execution time by delaying the execution time by the minimum amount of time required.

[Brief explanation of the drawing]

FIG. 111 is a block diagram showing one embodiment of the present invention.
The figure is a time chart showing the waveforms of each signal in this embodiment, and FIG. 3 is a block diagram showing a conventional data processing device using a microprocessor.

Claims (1)

[Claims] an oscillator that generates a reference signal having a cycle that is an integer fraction of a clock signal for a microprocessor; a frequency divider that divides the output signal of the oscillator into a predetermined ratio to generate a clock signal for the microprocessor; Clock supply control that stops clock supply to the frequency divider for one reference signal period or more in response to a clock period extension request signal output from the frequency divider, thereby extending the clock signal period of the microprocessor for one reference signal period or more. A data processing device having means.