JPS6111763Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sequence control circuit, and an object of the present invention is to provide a sequence control circuit that can perform sequence control with a relatively small number of components.

Generally, in a device such as an answering machine which is operated according to a predetermined order, the R-S flip-flops are set and reset one after another for sequence control operation. However, this circuit configuration has a large number of parts, which is disadvantageous in terms of assembly time, material cost, serviceability, etc.

The present invention eliminates the above drawbacks by using a shift register, and an embodiment thereof will be described below with reference to the drawings.

The figure shows a specific circuit diagram of one embodiment of the circuit of the present invention. In the figure, 1 is an R-S flip-flop whose output terminal is connected to the data input terminal D of the shift register 4 via an integrating circuit consisting of a resistor 2 and a capacitor 3, and the Q output terminal of the R-S flip-flop 1 is connected to the data input terminal D of the shift register 4. It is connected to one input terminal of a two-input NOR gate 7 via an integrating circuit consisting of a resistor 5 and a capacitor 6. The shift register 4 is a serial input parallel output type shift register, and its reset input terminal R is connected to the output terminal of the R-S flip-flop 1 together with the other input terminal of the NOR gate 7. The output terminal of the NOR gate 7 is connected to the clock input terminal C of the shift register 4 through a forward diode 8. Diode 9 is connected to the cathode of diode 8,
The cathodes 10 and 11 are commonly connected, and a resistor 12 is connected between the clock input terminal C and ground.

The operation of the circuit having the above configuration will be explained. Assuming that R-S flip-flop 1 is now in the reset state, its output is at H level, Q
The output is at L level. It is assumed that the capacitor 3 is charged to the value of the power supply voltage V _c by this output. Further, since the output is at H level, each output of _Q0 to _Q3 of shift register 4 is all at L level.

In this state, R-S flip-flop 1
When is set, the Q output becomes H level and the output becomes L level. Therefore, the NOR gate 7 has both inputs at the L level due to the integrating circuit consisting of the resistor 5 and the capacitor 6, so the above R-
A signal that changes from L level to H level when the S flip-flop 1 is set is applied to the clock input terminal C of the shift register 4 through the diode 8. The output of the 2-input NOR gate 7 is determined by the voltage of the capacitor 6 after a certain period of time determined by the charging time constant of the capacitor 6 from this set point.
Since the level goes from L level to H level for NOR gate 7, it changes from H level to L level.
The shift register 4 receives the output positive pulse from the NOR gate 7, and the terminal voltage of the capacitor 3 (at this time, H
(The discharge time constant of the capacitor 3 is selected so that the output voltage level is 0.05), and only the Q ₀ output of the shift register 4 changes from the L level to the H level.

The time T when the D input terminal is considered to be at H level is
The calculation for the case where C-MOSIC is used for the shift register 4 is as follows. As is well known, the terminal voltage Et of the capacitor 3 when it is discharged is given by the following equation, where C is the capacitance value of the capacitor 3, and R is the resistance value of the resistor 2.

In C-MOSIC, when Et is 1/2V _c or more, it is at H level, so the time T during which the D input of shift register 4 is at H level when capacitor 3 is discharged is: becomes.

Next, if the time required for the second clock pulse to be applied from the terminal 13 to the clock input terminal C of the shift register 4 via the diode 9 is _T1 , then the discharge time constant of the capacitor 3 is set so that _T1 >T. Select CR. As a result, when the second clock pulse is input, the shift register 4
The high level data of Q ₀ is shifted to Q ₁ output, and Q ₀
Since the terminal voltage of capacitor 3, which is the data input, is at L level, the output becomes L level.
Thereafter, when pulses sequentially enter the terminals 14 and 15 in the same manner, the Q ₂ output of the shift register 4 and the Q ₃ output
The outputs become H level one after another, and finally by resetting the R-S flip-flop 1, the output levels of _Q0 to _Q3 of the shift register 4 all become L level. Therefore, Q ₀ of shift register 4 ~
By using each output of _Q3 , sequence control operations can be performed.

For example, when the circuit of the above embodiment is applied to a many message recording (NMR) signal generation circuit of a remote-controlled answering machine, Q ₀ is set to H level by a predetermined control signal from the owner.
The answering side tape is rewound at the output, and when the _Q1 output is at H level after the above-mentioned time _T1 has passed, the answering side tape is set to recording state, and the owner of the answering machine can call the answering side of his own answering machine from outside via the telephone line. A new response message is dubbed onto the tape and a stop signal is recorded at the end of the recording. After that, when the _Q2 output automatically becomes H level after a certain period of delay, the responding tape is rewound and a pulse is applied to terminal 15 by a new control signal from the owner or by stopping the responding tape. Then, the _Q3 output becomes H level and the responding side tape is in a playback state so that the owner can confirm the recorded content of the newly dubbed responding side message.

It goes without saying that the circuit of the present invention can be applied not only to remote-controlled answering machines, but also to other cases requiring sequence control operations.

As described above, the sequence control circuit according to the present invention includes a flip-flop whose output is changed by a signal that starts sequence control, and an output signal outputted from the first output terminal of the flip-flop with a predetermined time delay. a first delay circuit that delays an output signal output from a second output terminal of the flip-flop by a predetermined time; a second delay circuit that delays the output signal output from the second output terminal of the flip-flop; a pulse forming circuit that is connected to the flip-flop and forms a pulse when the output of the flip-flop changes;
a serial input/parallel output type shift register which takes the output signal of the first delay circuit as the data input; The circuit sequentially applies the second clock pulse, and the first delay is such that the data input of the shift register changes between the generation of the first clock pulse and the generation of the second clock pulse. Since the delay time of the circuit is selected and the sequentially changing signals for the sequence control operation are obtained from the parallel outputs of the shift register, an independent clock signal generator is not required, and a sequence that does not occur at any time can be avoided. It is possible to reliably wait until the start of control, and the circuit can be configured with fewer parts than a sequence control circuit configured by cascading flip-flops, thereby improving the space factor. In addition, it is possible to shorten assembly time and reduce costs.
By increasing the number of output bits of the shift register, the number of control states can be increased, and in this case, the above-mentioned effects can be further enhanced.

[Brief explanation of the drawing]

The figure is a specific circuit diagram of one embodiment of the sequence control circuit according to the present invention. 1...R-S flip-flop, 4...Series input parallel output type shift register, 7...2 input NOR gate.

Claims (1)

[Scope of utility model registration request] A flip-flop whose output is changed by a signal that starts sequence control; a first delay circuit that delays an output signal outputted from a first output terminal of the flip-flop by a predetermined time; and a second delay circuit of the flip-flop. a second delay circuit that delays the output signal output from the output terminal for a predetermined time;
a pulse forming circuit connected to the first output terminal of the flip-flop and the first delay circuit and forming a pulse when the output of the flip-flop changes; an output pulse of the pulse forming circuit being a first clock pulse; A serial input/parallel output type shift register which receives the output signal of the first delay circuit as a data input, and a clock pulse from the second onward is applied to the clock input terminal of the shift register following the application of the output pulse of the pulse forming circuit. The delay time of the first delay circuit is configured such that the data input to the shift register changes between the generation of the first clock pulse and the generation of the second clock pulse. and a sequence control circuit configured to obtain sequentially changing signals for sequence control operations from the parallel outputs of the shift register.