JPS6111671Y2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to an alarm clock that clearly informs the user that an alarm has been set when an alarm is set, and also allows the user to check whether there is any abnormality in the alarm notification device. .

In conventional alarm watches, there are methods to indicate whether the alarm has been set reliably by displaying an alarm mark or by flashing the hours and minutes. However, this method has been an obstacle in clearly displaying the time after setting the alarm. Further, with these systems, even if an alarm sound generating device such as a speaker has an abnormality such as a disconnection, and is in a state where it is unable to generate an alarm sound, it is not possible to notify the user. Then the alarm set switch is turned off.
A method was devised in which the alarm sound generator emits a sound for a certain period of time when the alarm turns ON. FIG. 1 shows its block diagram. 1st
In the figure, an oscillator 2 is a circuit that generates a time reference signal, and a frequency divider 4 is a circuit that divides the frequency of the reference signal. The clock circuit 6 is a circuit that receives the signal from the frequency divider 4 and counts the current time. The current time signal counted by the clock circuit 6 is displayed on the display section 10 via the decoder 8.

On the other hand, the time limit circuit 18 is a monostable multivibrator or the like, and is a circuit that generates a signal that becomes H level for a certain period of time when the alarm set switch 20 is turned on from OFF. Therefore, when the alarm set switch 20 is turned from OFF to ON, the AND gate 24 remains open for a certain period of time. This allows the frequency divider 4
The frequency signal for the alarm sound from the AND gate 2
4. The signal is input to the amplifier circuit 28 via the OR gate 26, and a sound is generated by the sound generating section 30. If the alarm setting switch 20 is in the ON state and the alarm setting time signal stored in the alarm storage circuit 16 by the setting circuit 14 matches the current time signal in the coincidence circuit 12, the AND gate 32 is opened. Become. As a result, the frequency from the frequency divider 4 is input to the amplifier 28 via the AND gate 22 and the OR gate 26, and the sound generating section 30 generates an alarm sound.

This conventional method uses an alarm set switch 20.
It can be confirmed by sound that the gate is closed and the alarm is set, and the OR gate 26 and the amplifier circuit 2 are closed.
8. It is also possible to check whether there is any abnormality in the circuit leading to the sound generating section 30. However, with this conventional system, it is impossible to notify the user even if there is an abnormality in the matching circuit 12 or a break in the line 21. Therefore, in this conventional method, even if a sound is generated when the alarm set switch 20 is turned from OFF to ON, if there is a break in the line 21 or an abnormality in the matching circuit 12, the alarm sound will not be generated at the alarm setting time. It will happen. In other words, although this conventional method can confirm that the alarm has been set reliably, it is found that it is incomplete in detecting abnormalities in the circuit that generates the alarm sound.

Therefore, the present invention makes it possible to check by sound when setting an alarm whether there is any abnormality in the circuit that generates the alarm sound, including the matching circuit, and also to confirm that the alarm setting has been performed reliably.

The present invention will be explained below based on examples.

FIG. 2 is a block diagram showing an embodiment of the present invention. In FIG. 2, an oscillator 2, a frequency divider 4, a clock circuit 6, a decoder 8, a display section 10, a coincidence circuit 1
2. The setting circuit 14, alarm storage circuit 16, time limit circuit 18, alarm set switch 20, amplifier circuit 28, and sounding section 30 are the same as those shown in FIG.

In FIG. 2, alarm set switch 20 is input to time limit circuit 18 and AND gate 32. In FIG. The timer circuit 18 is input to the control circuit 34. The control circuit 34 also receives an alarm time signal from the alarm storage circuit 16 and a current time signal from the clock circuit 6. Control circuit 3
4 outputs the current time signal from the timer circuit 6 to the matching circuit 12 when the signal from the timer circuit 18 rises to H level, and outputs the alarm time signal from the alarm storage circuit 16 when the signal from the timer circuit 18 rises to L level. It is configured to output the signal to the matching circuit 12.

The output signal of the matching circuit 12 is input to an AND gate 32. A high frequency signal for generating an alarm sound from the frequency divider 4 is also input to the AND gate 32, and the output signal of the AND gate 32 is input to the amplifier circuit 28.

FIG. 3 is a circuit diagram of the control circuit 34 in FIG. 2. The control circuit 34 has 12 switching control circuits 34.
a, 34b...34k, 34l and inverter 46
It consists of Further, the switching control circuit 34a includes an OR gate 40a, AND gates 42a and 44a.
and other switching control circuits 34b, 34c,
...34k and 34l also have a similar configuration. And switching control circuits 34a, 34b,...34k, 34l
AND gates 42a, 42b,...42k, 42
The current time signal from the clock circuit 6 is input to l, and the AND gates 42a, 42b,...42k,
A signal from the timer circuit 18 is input to the other input terminal of 42l. On the other hand, switching control circuit 34a, 3
4b,...34k, 34l AND gate 44a,
The alarm time signal from the alarm storage circuit 16 is input to the AND gates 44a, 44b, . . . 44k, 44l.
A signal from the timer circuit 18 is inputted to the other input terminal of the inverter 46 via an inverter 46. The output signals of AND gates 42a and 44a are input to OR gate 40a, which in turn is input to matching circuit 12. Other AND gates 42b, 42
c,...42k, 42l, 44b, 44c,...44
k, 44l, or gate 40b, 40c,...40
k, 40l also have a similar configuration.

Next, the operation of this circuit will be explained.

Normally, AND gates 42a, 42b,...42
Since k, 42l are in a closed state, matching circuit 1
2 has AND gates 44a, 44b,...44k,
44l, or gate 40a, 40b,...40k,
An alarm time signal is input via 40l and compared with the current time signal. Here, when the alarm set switch 20 is turned on from OFF, the timer circuit 1
8 outputs a signal that remains at H level for a certain hour. Therefore, the AND gates 44a and 44 are connected only while the signal of the timer circuit 18 is at H level.
b,...44k, 44l are closed, and gate 42
a, 42b, . . . 42k, 42l are in an open state. As a result, the current time signal is output to the AND gate 42.
a, 42b,...42k, 42l, or gate 40
a, 40b, . . . 40k, 40l to the matching circuit 12. As a result, the current time signal from the clock circuit 6 and the same current time signal from the control circuit 34 are input to the matching circuit 12, so the matching circuit 12 outputs an H level signal to open the AND gate 32. . As a result, the frequency from the frequency divider 4 is input to the amplifier circuit 28, and the signal of the time limit circuit 18 becomes H.
The sound generation unit 30 generates sound only while the level is reached.

If the matching circuit 12, the amplifying circuit 28, the sounding section 3
If there is an abnormality in 0, no sound will be generated.

By generating this sound, the user can confirm that the alarm has been properly set.
Moreover, it can be confirmed that there is no abnormality in the matching circuit 12, the amplifier circuit 28, and the sound generating section 30.

In this way, the conventional alarm setting confirmation mechanism could only detect abnormalities such as disconnections in the amplifier circuit, sounding section, etc., but according to the present invention, the coincidence circuit 1
You can check whether there are any abnormalities up to 2 when setting the alarm. As a result, when setting an alarm, the user can confirm that the alarm sound will sound more reliably at the alarm setting time, and the alarm setting confirmation mechanism becomes more effective.

In this embodiment, the control circuit 12 is provided between the alarm storage circuit 16 and the coincidence circuit 12, but it can also be provided between the timer circuit 6 and the coincidence circuit 12.

On the other hand, in a timer that turns on or off another electrical device such as a connected radio at a set time, the present invention is used to turn on the other electrical device such as the radio for a certain period of time when the timer set switch is turned on. Of course, it is also possible to implement it.

As described above, according to the present invention, it is possible to provide a clock that can more reliably confirm that an alarm sound is generated at the alarm setting time when the alarm is set.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing a conventional embodiment, Figure 2 is a block diagram showing a conventional embodiment.
The figure is a block diagram showing an embodiment of the present invention, and FIG. 3 is a circuit diagram of its control circuit. 18... Time limit circuit, 20... Alarm set switch, 30... Sound generation section, 34... Control circuit, 3
4a, 34b,...34k, 34l...Switching control circuit.

Claims (1)

[Scope of utility model registration request] It has two inputs: an oscillator, a frequency divider that divides the signal from the oscillator, a clock circuit that measures the current time using the signal from the frequency divider, and an alarm storage circuit that stores the alarm time. A matching circuit that outputs a matching signal when the two times input to this input match, a sounding section that generates a sound based on the matching signal, an alarm set switch, and an alarm set switch that is opened and closed by turning the alarm set switch on and off. and a gate circuit that controls supply of the coincidence signal to the sound generation section, wherein the alarm set switch is controlled.
A time limit circuit outputs a signal for a certain period of time when turned from OFF to ON, and when the signal is output from the time limit circuit for a certain period, the same time signal is supplied to both inputs of the matching circuit. 1. An alarm setting confirmation mechanism for a watch, comprising: a control circuit for switching and selecting an alarm time signal to be inputted to one input of a matching circuit and a current time signal inputted to the other input.