CA1072747A - Electronic timepiece with automatic alarm shut off - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE

An alarm electronic timepiece in which an alarm signal is generated in accordance with coincidence between an actual time signal developed by time keeping circuitry in the timepiece and a chosen alarm time set in the timepiece. A delay signal is generated from the time keeping circuitry of a period equal to that of the desired alarm operation period, and the delay signal acts to inhibit alarm circuitry at the end of the period following operation of the alarm. Delay signal generating means includes a short pulse shaper for the delay signal in accordance with signals from the time keeping circuitry.

Description

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This invention relates to alarm electronic timepieces having particular reference to a timepiece with automatic alarm shut off.
In the pastl electronic alarm timepieces have been constructed in which alarm shut off can be effected either manually or automatically after a one-minute period after the start of the alarm condition. This latter depended upon the fact that coincidence between the actual time reading of the timepiece and the alarm setting time was then no longer present. Surh an auto-matic shut off mechanism has not been adopted in practlce for watches because it is particularly inconvenient for the user,and secondly because the life of the watch battery is severely shortened from the large consumption of current (of the order of lOmA) for the one-minute period. Other possible approaches are the use of a resistance capacitor circuit of suitable time constant in con~unction with a holding circuit quite separate from the time keeping system.
These are unsatisfactory because a largecapacitor is required together with additional discrete electronic parts. Such an arrangement is also subject to temperature variations which affect its accuracy.
In the present disclosure, circuitry is described which allows for a constant alarm period unaffected by temperature which does not need special holding circuitry and employs only semiconductor integrated circuitry in conjunction with the time keeping circuits already present in the watch.
A specific embodiment of the invention will now be described having reference to the accompanying drawings in which;
Figure 1 is a partly block diagram of a circuit for operating and shutting off an alarm, and, Figure 2 shows four waveforms associated with the circuit of Figure 1.
In Figure l an oscillator 1 feeds a dividing circuit 9 which produces a 1 Hz output signal i (Figure 2) for a divide-by-ten 10, and a waveform ~ ' shaping circuit 15. The divider 10 feeds a divide-by-six concerned with the minutes and hours counting circuitry for actual time indication, which will not be detailed further here. The divider 10 also feeds a signal ;

(Figure 2) to shaper 15. A /10 Hæ pulse signal is output from shaper 15 4~

of form shown at k (Figure 2) whlch is empoloyed as an alarm shut-off signal, detailed later.
A coincidence circuit 14 is fed wlth a first digital signal which is the actual time shown by the time keeping circuits of the time piece, and with a second digital signal which is the setting of an alarm time register.
When the two inputs are identlcal, an output is produced by circuit 14 7 iS
shaped by a shaper 16 and is fed to a memory 17 for application to an alarm buzzer 30.
With reference to Figure 2, the operation of the shaper 15 is as follows.
At time tl half a second before the onset of the tenth second from the start of a minute, the signals i and j have the form shown. The "0"
level signal i at tl results in the switching on of the transmission gate 32 and the switching off of gate 33. The m signal is at "0" level in consequence. This results in a "O" level and a "1" level input to NOR 34 so that signal k is at "0".
At time t2 gate 33 is swltched on and gate 32 switched off by signal i. This results in the signal m holding at "0", in spite of the change of state of signal ; to "O" at the input of gate 32. However, since the ; signal fed to NOR 34 and the m signal are "0", the signal k becomes "1".
At time t3, gate 32 is switched on and gate 33 switched off at which point the signal m is carried to "1" level (since j is now "0"~ at which it remains for subsequent switchings of gates 32 and 33. The m signal input to NAND 34 at "1" results in the return of the k signal to "0".
This arrangement permits the use of the comparatively high frequency ~1 Hz) output of divider 9, to be used as a control signal for shaper 15 so that its output k is a single pulse of the same width as those at i is produced, but with a delay of 10 seconds from the s~art of each minute.

.. .. . . . . .

The signal k is input to the r~?set terminal R of memory 17 through the OR circuit 20. Since the memory 17 is formed as an R-S flipflop, in the noxmal state, the input set terminal S of the NOR circuit 22 is "O" level and output Q of NOR circuit 22 is "1" level and output Q is thus "O". The buzzer alarm 30 i9 driven only when transistor 31 is turned on, that is only when both inputs to NAND 12 are "1". Q is one of these inputs.
When the actual time and alarm set time become identlcal that is "O" Hours "O" ~inutes and "00" Seconds di~ference,the output of the colnci-dence circuit 14 goes to "O" level from "l" level and this signal is shaped into a short width pulse by the shaping circuit 16. The shaping circuit 16 is formed as a latch circuit similar to circuit 15 described above, but the pulse width of this control signal which is to "1" level is made longer than that of signal i. When this single pulse control signal from shaping circuit 16 is input to the set-terminal S of NOR circuit 22, the output Q of the NOR 21 goes to "1" level from "O", and the alarm buzzer 30 is enabled to operate.
After a delay of 10 seconds, the single pulse signal k inputs to the reset terminal R of NOR circuit 21, which results in "O" a~ the output Q and alarm 30 is disabled. As mentioned, alarm 30 is driven only when both inputs ~0 to NAND 12 are "1". One input is connected to output Q. The other is fed from a NAND 13. Inputs for NAND 13 are taken from divider 9 which allows a driving frequency (32 Hz) output to NAND 12. Tbis driving frequency signal thus actuates the buzzer alarm, when Q is "1", and is suited to its proper efficient operation. If it is desired to stop alarm operation before the 10 seconds have elapsed, a single pulse signal may be produced manually from a switch 23, which inputs a "1" to the OR circuit 20. This passes to reset terminal R and the buzzer operation ceases.
This circuitry thus effectively achieves automatic alaxm shut-off action using simple structure with low current drain, and makes use of the signals ;
already present in tbe main time keeping circuits of a timepiece, without the need for complicated or bulky alarm holding and release e~uipment.

Claims (3)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE PROPERTY OR
PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. An alarm electronic timepiece including main time keeping circuitry which comprises;
a coincidence signal means for detecting coincidence between an actual time signal developed by the time keeping circuitry and a chosen alarm time set in said timepiece, means responsive to a coincidence signal generated by said coincidence signal generating means for actuating an alarm, a delay signal means connected to receive a signal from the time keeping circuitry for generating a delay signal of a period equal to that of a desired alarm operation period, and means feeding said delay signal to said responsive means for inhibiting actuating of said alarm.

2. An alarm electronic timepiece as defined in claim 1, the time keeping circuitry including a minutes counter, the coincidence signal gener-ating means being constructed for initiating generation of said coincidence signal at discrete minutes determined by the time keeping circuitry and the delay signal means generating said delay signal synchronized to the intervals between said discrete minutes.

3. An alarm electronic timepiece as defined in claim 1 or 2, the delay signal means including pulse shaping means for shaping said delay signal in accordance with the signal received from the time keeping circuitry.