JPS61116443A - Stuff bit inserting system for digital data transmission - Google Patents

Abstract

PURPOSE:To transmit data efficiently and securely by making an observed sample time range shorter than a set time in a block boundary so as to observe it. CONSTITUTION:When digital data is supplied through a transmission line, a separator circuit 20 establish the frame synchronization from the inputted signal, and separates a stuff flag and digital data, which are inputted to a stuff removal circuit 21. A stuff is removed from the digital data, which is outputted, when the stuff flag is '1', and input data is outputted as it is when the stuff flag is '0'. Namely, when the occurrence of '0' is detected by a short observation bit in the boundary of a block by the stuff, the detection can be made whether or not the separate stuff is necessary, by the block. Moreover '1' forcibly inserted into the top of the block can be used for some part of the multiframe synchronization. Thus stuffing efficient in terms of information volume can be realized comparatively easily and securely.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field to which the invention pertains) The present invention relates to a digital data transmission method for transmitting digital data consisting of a 0''II III bit sequence, in which a transmission line is provided that requires limitation to the input bit sequence. The present invention relates to a stuff bit insertion method for digital data transmission that allows reliable and easy transmission when used.

(Prior art) Conventionally, in a digital transmission line that transmits digital data consisting of a bit sequence of '0''' and '1', there is no limit to the occurrence of the bit sequence to be transmitted, and there is no A transmission line that can transmit even the "O", 61''' sequence (hereinafter referred to as a transmission line with BSI secured): BSI is Bjt 5 sequence Tndepe
For a specific bit sequence of “0” and “1” consisting of
There is a transmission line (hereinafter referred to as a transmission line for which BSI is not secured).

In a transmission path where BSI is not secured, for example, if the bit sequence to be transmitted has 15 or fewer consecutive occurrences of "0"', and any 24-bit sequence has 3 or more I
The condition is that I I II exists.

There is a stuffing method for transmitting data whose bit sequence is not restricted through such a transmission path where SI is not secured. This occurs when an input bit sequence is divided into blocks of a certain length, and when a sequence that does not satisfy the conditions occurs among the bit sequences in the divided blocks (hereinafter referred to as "when a violation occurs"). ), one bit for every n bits (n is an integer) in the input bit sequence 111 II
is forcibly inserted and transmitted, and at the same time code data (stuff flag) indicating that J''' has been forcibly inserted into the sequence is transmitted, and on the receiving side, if there is a stuff flag, KL arranged every n bits
It reproduces the input bit sequence by removing I II.

Here, since the occurrence of a violation is checked for each block, processing at the boundaries of blocks becomes a problem.

Conventionally, the leading bit of a block is fixedly set to ``1'' to increase the occurrence of 111'' at block boundaries, thereby performing a simple process that eliminates the need to check for the occurrence of violations across blocks. However, if 1'' is fixedly inserted, it cannot be used for transmitting input digital data, which has the disadvantage of lowering transmission efficiency.

(Objective of the Invention) In order to eliminate such drawbacks, the present invention strengthens the conditions for inspection of violations at the border, and at the same time reduces the fixed insertion of 1", thereby achieving efficient and reliable inspection. This invention attempts to provide a stuff bit insertion method for digital data transmission that enables data transmission, and will be described in detail below with reference to the drawings.

(Structure and operation of the invention) FIG. 1 is a block diagram of an embodiment showing the structure of the present invention, in which 100 is a digital data transmitting device, 200 is a digital data receiving device, 300 is a digital transmission path, and 1 is a digital data transmitting device. The input terminal and 2 are the output terminals.

In the digital data transmitter 100, 10 is a memory, 11 is a stuff control circuit, 12 is a memory, 13 is a selection circuit, 14 is a multiplexing circuit, and 15 is a pulse generation circuit.

The signal supplied from the input terminal 1 is digital data including images and sounds, and the bit sequence thereof is not subject to any restrictions. This signal is written into the memory 10, output from the memory 1 in response to a read clock output from the stuff control circuit 11, and supplied to the memory 12 and the stuff control circuit 11.

The stuff control circuit 11 is for detecting the presence or absence of a violation included in a bit sequence from data input via the memory 10. Therefore,
First, the pulse generating circuit 15 generates a pulse for a certain period. The pulses include block-width pulses that are the unit of stuff insertion, and pulses for the observation period for violation detection.For example, if the consecutive occurrences of HQ II are 15 bits or less, there are 3 pulses in any 24-bit sequence. There are more than 1".

In a transmission line having two conditions, two pulses with a width of 15 samples and a pulse with a width of 24 samples, and a pulse shorter than the above pulses at the beginning and end of the block,
For example, the pulse is 9 samples wide at the beginning and 8 samples wide at the end.

Next, the stuff control circuit 11 detects whether or not the violation occurs in the pulse period generated by the pulse generation circuit 15 in the digital data input via the memory 10. In other words, in the first 9 samples of the block, a violation is detected unless there are at least two 1s (I II), and in the last 8 samples of the block, a violation is detected unless there is at least one "1". do.

However, it is assumed here that 1'' is always placed in the first bit of the block, as will be described later.

Furthermore, in the middle of the block, a violation is detected except when there is at least one Lr 1 )H in 15 samples and at least three 111 II in 24 samples.

FIG. 2 is a diagram showing an example of the configuration of a violation detection circuit, and shows an example of detecting whether there are at least three "1"s among 24 samples.

Here, 30.31 is an input terminal, 32 is a counter, and 33
is a 24-sample delay circuit, 34 is a subtracter, and 35 is a comparison circuit.

Digital data is input to the counter 32 via the input terminal 30.
Also, a block pulse indicating the period of the block is inputted to the reset terminal of the counter 32 via the input terminal 31, and the counter is reset at the beginning of each block. After the reset, the number of digital data "1" input via the input terminal 30 is counted.

The output of the counter 32 is supplied to a subtracter 34 and a 24 sample delay circuit 33, and the counter output delayed by 24 samples is also input to the subtracter 34. Because of this configuration, the subtracter 34 outputs “1” in the 24 samples.
” is output.

The number of El l II output from the subtracter 34 is compared with the value 3 determined from the conditions in the comparator 35, and
If it is larger than that, it is assumed that a violation has been detected and a detection signal It Ill is outputted via the output terminal 36 .

It can be easily inferred that detection of other conditions can also be performed with a completely similar configuration.

When a violation is detected in the block formed by the following method, the stuffing control circuit 11 sends a stuffing selection signal to the selection circuit 13 and a read control signal to the memory 12. As a result, digital data is read out from the memory 12 for a 7-bit period, and is supplied to the multiplexing circuit 14 via the selection circuit 13. During the next 1-bit period, reading from the memory is prohibited, and at the same time, the selection circuit 13 selects stuffpid 1''' and supplies it to the multiplexing circuit 14. Therefore, if the consecutive occurrences of LL OII are 15 bits or less and there are three or more 111'' in any 24-bit sequence. This condition can be satisfied.

Additionally, a stuff flag 1'' indicating that the block has been stuffed is output to the multiplexing circuit 14.
Since the transmission speed of input data decreases due to stuffing, the stuffing control circuit 11 outputs a read speed control signal to the memory 10 to perform data speed matching.

The multiplexing circuit 14 multiplexes the digital data output from the selection circuit 13 and the stuff flag output from the stuff control circuit 11, and sends the multiplexed data to the transmission line 300.

Next, in the digital data receiving device 200, the 20
21 is a separation circuit, and 21 is a stuff removal circuit.

Digital data is transferred to the separation path 20 via the transmission path 300.
, the separation circuit 20 establishes frame synchronization from the input signal and separates it into a stuff flag and other digital data.

The digital data and the stuff flag are input to the stuff removal circuit 21, and when the stuff flag is Ill''' (stuff is inserted), the stuff is removed from the digital data and output. Also, the stuff flag is "0". In this case, the input data is output as is.

Next, block boundary processing from the perspective of frame configuration will be described.

Digital data output from the multiplexing circuit has a frame structure. Then, transmission synchronization patterns, control information, etc. necessary for transmission are arranged.

Figure 3 shows an example of the frame configuration, where:
One transmission frame consists of 193 bits, and one multiframe consists of 24 transmission frames.

Furthermore, three transmission frames constitute the above-mentioned stuff detection insertion unit block. Note that bit number O in the figure is a bit used for multiframe synchronization.

Here, we will focus on the bit at the beginning of the frame.

First, in order to make violations less likely to occur at block boundaries, the first bit of a block is forcibly set to "1". Therefore, "1" is inserted into the first bit of the frame every three transmission frames. Also, multi-frame synchronization is inserted every four frames.

Here, a synchronization pattern is arranged such that bits that are a common multiple of 3 transmission frames and 4 transmission frames are always 1''.

FIG. 4 shows an example of a multi-frame configuration, where ■ indicates a multi-frame number, ■ indicates multi-frame synchronization, ■ indicates J'' for stuffing countermeasures, and ■ indicates an empty bit.

As mentioned above, as a result of arranging a synchronization pattern that always makes it 1 n for bits that are a common multiple of 3 transmission frames and 4 transmission frames, It is possible to have two roles for the arrangement of "i I+" of the first bit of the block.

In addition, in the embodiment described in "-", for simplicity, the frame length,
Although the explanation is given with the number of multi-frames and the number of blocks as 193 bits and 24.3, respectively, it is clear that the invention can be applied to other numerical values as well.

(Effects) As explained below, the present invention detects the occurrence of 0''' using short observation bits at the boundaries of blocks, which are the units in which stuffing is performed, thereby eliminating the need for stuffing independently for each block. It is possible to detect whether or not the This method has the advantage of being able to perform quantitatively efficient stuffing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment showing the configuration of the present invention, FIG. 2 is a diagram showing an example of the configuration of a violation detection circuit, FIG. 3 is a diagram showing an example of a frame configuration, and FIG. 4 is a multi-frame diagram. It is a figure showing an example of composition. 100...Digital data transmitting device, 200...
Digital data receiving device, 300...Digital transmission line, 1...Input terminal, 2...Output terminal, 10.12
...Memory, 11...Staff control circuit, 13...
- Selection circuit, 14... Multiplexing circuit, 15... Pulse generation circuit, 20... Separation circuit, 21... Stuff removal circuit, 30.31... Input terminal, 32... Counter, 33...24 sample delay circuit, 34...subtracter, 35...comparison circuit, 36...output terminal. Patent applicant Nippon Telegraph and Telephone Public Corporation NEC Corporation

Claims (2)

[Claims] (1) Divide the bit sequence of input digital data into blocks at regular intervals, observe the bit sequence at a specified sampling time within this block, and add data to the bit sequence if the specified conditions are not satisfied. A digital data transmitting device that has a function of converting and transmitting data so as to satisfy conditions, and converting the converted data of the digital data transmitting device inputted via a transmission path, excluding added data. In the digital data receiving device having a function of reproducing a previous bit sequence, the digital data transmitting device is characterized in that at the boundary of the block, the observation sample time range is made shorter than the predetermined time. Stuff bit insertion method for digital data transmission. (2) In a digital data transmission device, a bit sequence of input digital data is divided into blocks at regular intervals, and a “1” is forcibly placed at the beginning of each block.
A part of the placed “1” is converted to “1” in the multi-frame period.
Claim No. 1 (
Stuff bit insertion method for digital data transmission described in section 1).