JP2006005862A - Staff synchronism control apparatus, repeater, data relay system and staff synchronism control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To maintain a transmission quality without omitting information to be transmitted, and to perform transmission using an independent asynchronous clock at the same transmission rate as a transmission rate of primary group interfaces. <P>SOLUTION: There are provided a primary group multiframe detection circuit 111 for performing multiframe synchronism detection; a sub-multiframe generation circuit 112 for allocating frame bits of the multiframe to frame synchronizing bits and generating a sub-multiframe at a bit rate lower than that of primary group interfaces; and a staff multiframe generation circuit 115 for multiplexing sub-multiframes to generate a staff multiframe. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to stuff synchronization control, and more particularly to a stuff synchronization control apparatus, a relay apparatus, a data relay system, and a stuff synchronization control method between primary group interfaces that transmit and relay primary group interfaces of a digital data transmission system using independent clocks. About.

  Conventionally, the stuff synchronization method is used in a data multiplexing apparatus, and performs synchronization at a bit rate higher than the bit rate of input low-order group data. In the stuff control, a stuff bit area for inserting extra dummy data is provided on the data side to be synchronized, or a stuff control area is secured. For this reason, the stuff synchronization cannot be performed unless the clock frequency to be synchronized is higher than the clock of the input low-order group data.

  As a technique for changing the clock frequency to be synchronized and the clock frequency of the input primary group interface with the same nominal value, a PCM synchronous multiplexing method is disclosed (for example, see Patent Document 1 below). This technique realizes stuff synchronization by allocating one of the 24 data channels of the primary group interface to stuff control, and enables asynchronous data communication.

JP-A-52-153317

  However, in digital transmission, when a primary group interface is transmitted by a transmission relay apparatus using an independent clock, in order to perform stuff control, a transmission relay apparatus having a transmission speed higher than 1.544 Mbit / s is required. Asynchronous communication cannot be performed with a relay device having a speed of 1.544 Mbit / s which is the same as that of the primary group interface.

  In the technique described in Patent Document 1, in order to perform stuff control at the same transmission rate, at least one of the 24 data channels is allocated for transmission of the stuff control signal. Is significantly reduced.

  In order to solve the above-described problems caused by the prior art, the present invention can maintain transmission quality without missing information to be transmitted, and can be transmitted by an independent asynchronous clock having the same transmission rate as that of the primary group interface. It is an object of the present invention to provide a staff synchronization control device, a relay device, a data relay system, and a staff synchronization control method capable of performing the above.

  In order to solve the above-described problems and achieve the object, a stuff synchronization control apparatus according to the present invention includes primary group multiframe detection means for detecting synchronization of a predetermined number of multiframes of an input primary group interface, and the primary group Sub-multiframe generation means for assigning frame bits of the multiframe detected by group multiframe detection means to frame synchronization bits, and generating a submultiframe at a bit rate lower than the bit rate of the primary group interface; Stuff multiframe generation means for generating a stuff multiframe by multiplexing the submultiframe generated by the submultiframe generation means, and transmission means for transmitting the stuff multiframe generated by the stuff multiframe generation means to a transmission line And be prepared The stuff multi-frame generating means allocates the bit of the frame synchronization information, the bit of the stuff control information, and the data insertion bit at the time of negative stuff of the stuff control to the frame bits of the stuff multi-frame, and the primary group The stuff multi-frame is generated with an independent asynchronous clock having the same bit rate as the interface.

  According to the present invention, it is possible to transmit all data channels of the input primary group interface at the same transmission rate as the primary group interface using an independent asynchronous clock, and the primary group input in the subsequent stage. The interface can be played back. Since the stuff control is performed by effectively using the limited frame bit area, a transmission relay having an independent asynchronous clock becomes possible. In particular, information such as CRC bits and game alarms can be transmitted together with actual data of all channels, and the quality of data transmission can be improved.

  According to the stuff synchronization control device, relay device, data relay system, and stuff synchronization control method according to the present invention, all input primary group interface data channels are asynchronously transmitted using independent clocks, and input at the subsequent stage. The primary group interface can be reproduced. In addition, since the stuff control is performed by effectively using the limited frame bit area, a transmission relay having an independent asynchronous clock becomes possible. In particular, information such as CRC bits and game alarms can be transmitted along with actual data of all channels, and the quality of data transmission can be improved.

  Exemplary embodiments of a staff synchronization control device, a relay device, a data relay system, and a staff synchronization control method according to the present invention will be explained below in detail with reference to the accompanying drawings.

(Embodiment 1)
FIG. 1 is a block diagram showing the configuration of the staff synchronization control apparatus of the present invention. The staff synchronization control device 100 includes a transmission stuff unit 102, a transmission relay device (transmission side) 103, a transmission relay device (reception side) 105, and a reception destuff unit 106. A transmission path 104 is provided between the transmission / reception transmission relay apparatuses 103 and 105. 101 is an input terminal of the transmission stuff unit 102, and 107 is an output terminal of the reception destuff unit 106.

  The transmission stuff unit 102 includes a primary group multiframe detection circuit 111, a submultiframe generation circuit 112, a memory 113, a stuff control circuit 114, and a stuff multiframe generation circuit 115. A signal supplied from the input terminal 101 is primary group interface (1.544 Mbit / s digital hierarchy interface) 24 multiframe data. The stuff control circuit 114 compares the amount of data input / output (written and read) with respect to the memory 113, performs stuff control described later, and controls the generation of the stuff multiframe in the stuff multiframe generation circuit 115.

  The transmission relay apparatus 103 on the transmission side amplifies and transmits the stuff multiframe data output from the transmission stuff unit 102 and a frequency (1) independent of the primary group interface (1.544 Mbit / s). ., 544 Mbit / s). The oscillation signal of the oscillation unit 132 is supplied to the stuff multiframe generation circuit 115.

  The transmission relay device 105 on the reception side includes a reception circuit 151 that receives stuff multiframe data received via the transmission path 104.

  The reception destuffing unit 106 includes a stuff multiframe detection circuit 161, a memory 162, a PLL circuit 163, a sub multiframe detection circuit 164, and a primary group multiframe reproduction circuit 165. The PLL circuit 163 compares the amount of data input to and output from the sub-multiframe detection circuit 164 and controls the generation of the primary group multiframe in the primary group multiframe reproduction circuit 165. At this time, the PLL circuit 163 controls the sub multiframe detection circuit 164 so that the sub multiframe reproduction clock is 1.544 Mbit / s. The sub-multiframe detection circuit 164 performs synchronization detection of the sub-multiframe read from the memory 162. The primary group multi-frame reproduction circuit 165 reproduces 24 multi-frames of the primary group interface (1.544 Mbit / s digital hierarchy interface) and outputs them from the output terminal 107.

  The primary group multiframe detection circuit 111 provided in the transmission stuff unit 102 performs 24 multiframe synchronization detection on the input signal, and outputs data and multiframe synchronization timing to the submultiframe generation circuit 112. .

  Here, signals handled by the stuff synchronization control apparatus will be described. FIG. 2-1 is a chart showing 24 multiframes of the primary group interface. The 24 multiframe 200 is a signal input from the input terminal 101, and the contents of MF1 among the multiframes (MF1 to 24) are shown in detail in the drawing. One frame MF1 is composed of control frame bits (F bits) 201 and time slot (TS1 to 24) bits. The TS1 bit is composed of 8 bits (B1 to B8). TS2 to 24 in one frame MF1 are payloads and store actual data.

  FIG. 2-2 is a chart showing a 24-multiframe format of the primary group interface. The F bit 201 of 24 multiframes (MF1 to MF24) is used for any one of the frame synchronization bit FAS201a, the game alert information bit DL201b, and the check bit CRC201c. For example, F bit 201 is used for DL 201b in MF1, F bit 201 is used for CRC 201c in MF2, and F bit 201 is used for FAS 201a in MF4.

  FIG. 3A is a chart illustrating sub-multiframes. The sub-multiframe 300 generated by the sub-multiframe generation circuit 112 is shown. As shown in the figure, the F bit 301a is not written to the memory 113 for odd multiframes (MF1, 3, 5,..., 23), and only F for even multiframes (MF2, 4, 6,..., 24). Write bit 301b to memory 113.

  FIG. 3-2 is a chart showing a sub-multiframe format. The sub-multiframe generation circuit 112 assigns the sub-multiframe synchronization signal and the game alert transfer bit S to the remaining 12 bits after removing 12 bits corresponding to 24 multiframe DL bits (4 Kbit / s). That is, in the sub-multiframe generation circuit 112, the game alarm information bit DL (the game of odd multiframes (MF1, 3, 5,..., 23 in the figure) in the F bit 201 of the 24 multiframe 200 shown in FIG. Each m bit of alarm information bit DL)) 201b is removed. For even multi-frames (MF2, 4, 6,..., 24), the frame synchronization bit FAS201a is assigned to 11 bits out of the total 12 bits of the F bit 301a, and the remaining 1 bit is assigned to the game alert transfer bit S. Assign as. In the example of FIG. 3B, the frame synchronization bit FAS 201a is set as “10001101110” using each 1 bit of MF2-22. The transfer bit S for game alarm is S = 0 at normal time, and changes to S = 1 at the game alarm.

  As a result, the sub-multiframe generation circuit 112 generates 24 multiframes (MF) as a submultiframe 300 at a slightly lower bit rate (1.540 Mbit / s) including the data channel of the payload. The game alarm transfer bit S is used to combine the inputted game alarm information bits DL201b in the 24 multiframe 200 of the primary group interface into one bit and transfer it to the opposite station (transmission relay device 105) via the transmission path 104. belongs to. Then, the sub-multiframe generation circuit 112 writes the data obtained by removing a part of the frame bits (F bit 301a) shown in FIG.

  The stuff control circuit 114 compares the amount of data written in the memory 113 with the amount of data obtained by removing a few bits of frame bits from the stuff multi-frame format (see FIG. 4A described later). Then, when there is a lot of data written in the memory 113, stuff control during negative stuffing is performed. At the time of negative stuffing, the data read from the memory 113 is read and inserted one extra clock into the data insertion bit J1 (see FIG. 4-2) prepared on the frame bit (F bit 401).

  On the other hand, when the amount of data written in the memory 113 is small, stuff control of the regular stuff is performed. At the time of positive stuffing, reading from the memory 113 is reduced by one clock, and dummy data is inserted into the stuff insertion bit J2 (see FIG. 4A) in the data. With the negative stuff and positive stuff control, the data amount in the memory 113 can be adjusted, and the read sub-multiframe data can be stuff-multiplexed in the stuff multi-frame format.

  In the stuff multi-frame generation circuit 115, the sub-multi-frame generation circuit 112 forms the stuff control signal using the number of bits removed from the 24 multi-frame bits. Then, a stuff multi-frame including the stuff control signal determined by the stuff control circuit 114 is generated at a speed of 1.544 Mbit / s using the clock of the oscillation unit 132 provided in the transmission relay device 103 on the transmission side. .

  FIG. 4A is a diagram illustrating an example of a stuff multiframe. In the sub-multiframe generation circuit 112, when the F bit 301b removed as described above is 12 bits, a stuff multiframe synchronization bit, a stuff control bit, and a bit for storing a data storage bit at the time of negative stuffing Is lacking. For this reason, as shown in FIG. 4A, one frame is set to 385 bits to form a 24-multiframe configuration. These 385 bits are the number of bits of the odd multiframe (MF1, 3, 5,..., 23) shown in FIG. 3-1, and the even number of multiframes (MF2, 4, 6,..., 24). The number of bits is obtained by adding 193 bits.

  Thereby, 24 bits can be secured as the number of frame bits (F bits) of the stuff multi-frame 400. Correspondingly, the multiframe period is 6 msec, which is twice 3 msec, the stuffable frequency deviation is changed from 333 Hz to 167 Hz, and the stuff ratio is lowered. In order to cope with this, in the stuff multi-frame 400, stuff control is performed twice in one multi-frame.

  In the illustrated stuff multi-frame 400, a total of 22 frames from MF 1 to 11 and MF 13 to 23 are composed of 1-bit F-bit 401 and 385-bit sub-multi-frame data 402a. As shown in the figure, a total of two frames of MF12 and MF24 are composed of 1-bit F bit 401, 384-bit sub-multiframe data 402b, and stuff insertion bit J2 (403). The stuff insertion bit J2 (403) is provided at two locations in the 24 multiframe, and is a position where a stuff (dummy data) insertion bit is inserted in the first stuff control and the second positive stuff.

  FIG. 4B is a diagram of an example of the stuff multiframe format. The setting contents of the control bits in the stuff multiframe 400 will be described. In the F bit 401, a data insertion bit J1 is provided. This data insertion bit J1 is provided at two locations of MF11 and MF23 in 24 multiframes. The surplus data at the first stuff control and the second negative stuff is inserted into the data insertion bit J1.

  In addition, a frame synchronization bit FAS 201a and a stuff control bit 410 (C11, C12, C21, C22, PC) are allocated to the 24-multiframe F bit 401. The frame synchronization bit FAS 201a is “10001101110” having a total of 11 bits as described above. D is an unused bit. The stuff control bits 410 (C11, C12, C21, C22, PC) correspond to the stuff control twice, and there are two locations in the 24 multiframes (the corresponding multiframe numbers are MF1, 3, 5, 7, 9 and MF 13, 15, 17, 19, 21), a total of 10 bits are set, and the first stuff control result 410 a and the second stuff control result 410 b are stored. In the illustrated example, stuff control is performed twice. By the stuff control twice, the stuffable frequency deviation can be 333 Hz. Although one-time staff control is possible, the frequency deviation in this case is 167 Hz, and the staff rate is reduced.

  FIG. 4C is a chart of an example of a staff control result assigned to the staff control bits. The example of use at the time of twice staff control is shown. The stuff control bit 410 is formed by C11, C12, C21, and C22. In the illustrated example, at the time of transmission, the same value is stored in C11, C12 and C21, C22. When C11, C12 (C21, C22) is "10", regular stuff control, when C11, C12 (C21, C22) is "01", no stuff control, C11, C12 (C21, C22) is "00" Indicates negative staff control. PC represents a parity calculation value with C11 and C12 (here, odd parity is assumed). By using such a stuff control bit 410, a majority decision can be made when an error of 1 bit or less occurs in the stuff control bit 410 on the receiving side, and a destuff error can be prevented.

  The signal input to the reception destuffing unit 106 is subjected to stuff multiframe synchronization detection by the stuff multiframe detection circuit 161, and the stuff control bit 410 is extracted. If the extracted stuff control bit 410 is negative stuff, the data stored in the stuff multi-frame 400 is written in the memory 162 by one extra clock. On the other hand, if it is positive stuff, the value of the stuff insertion bit J2 is discarded without being written to the memory 162.

  The PLL circuit 163 performs phase comparison based on the data amount of the sub multiframe data extracted by the control of the received stuff control bit 410 of positive stuff, negative stuff, and no stuff. Then, the clock of the primary group interface (1.544 Mbit / s digital hierarchy interface) input to the input terminal 101 of the transmission source is reproduced.

  The sub-multiframe detection circuit 164 reads data corresponding to the sub-multiframe data amount from the memory 162 with the reproduction clock. Thus, actual data (internal data channel and game alarm transfer bit S) is extracted from the payload of the sub-multiframe data. Thereafter, 24 multiframe frame bits of the primary group interface are added by the primary group multiframe reproduction circuit 165 and output from the output terminal 107.

  FIG. 5 is a flowchart showing processing on the transmission side according to the first embodiment. First, the primary group multiframe detection circuit 111 detects multiframe synchronization of 24 multiframes of the primary group interface (step S501). Next, the sub-multiframe generation circuit 112 removes some of the 24 multiframe bits (F bits), and forms sub-multiframe data at a slightly lower bit rate (1.540 Mbit / s) (step). S502). Thereafter, the sub-multiframe generation circuit 112 writes the sub-multiframe data to the memory 113 (step S503).

  Next, the stuff control circuit 114 compares the amount of write data in the memory 113 with the amount of read data (step S504). When the data amount of the write data matches the data amount of the read data (step S504: CASE 1), the staff control is not performed (step S505), and the process proceeds to step S508. If the amount of read data is larger than the amount of write data (step S504: CASE2), regular stuff control is performed (step S506), and the process proceeds to step S508. In the normal stuff control, dummy data is inserted into the stuff insertion bit J2 of the stuff multiframe. When the amount of write data is larger than the amount of read data (step S504: CASE3), negative stuff control is performed (step S507), and the process proceeds to step S508. In the negative stuff control, an extra one clock is read from the memory 113 and stored in the data insertion bit J1 of the stuff multiframe (step S507).

  Thereafter, the stuff multi-frame generation circuit 115 generates the stuff multi-frame 400 with the free-running clock of the oscillation unit 132 used for transmission relay, and the data read from the memory 113 is stored in the multi-frame payload as the stuff control circuit. The data is stored according to the staff control instruction 114. At the same time, the stuff control bit 410 in the bits of the stuff multiframe 400 is set (step S508). The generated stuff multiframe data is transmitted from the transmission circuit 131 to the transmission path 104 (step S509), and the processing on the transmission side ends. The bit rate of the stuffed multi-frame 400 to be transmitted has the same transmission speed (but asynchronous) as the primary group interface (1.544 Mbit / s).

  FIG. 6 is a flowchart showing processing on the receiving side according to the first embodiment. First, the reception circuit 151 receives stuff multiframe data transmitted via the transmission path 104 (step S601). Next, the stuff multi-frame detection circuit 164 performs synchronization detection of the stuff multi-frame 400 and extracts the stuff control bits 410 (step S602).

  Next, the stuff multi-frame detection circuit 164 determines the setting contents of the stuff control bit 410 and performs stuff control for each setting (step S603). When the detection result of the stuff control bit 410 indicates no stuff control (step S603: CASE1), the data excluding the stuff control bit 410 of the stuff multiframe 400 is written to the memory 162 (step S604), and the process proceeds to step S607. On the other hand, if the detection result of the stuff control bit 410 is the correct stuff control (step S603: CASE2), the correct stuff control is performed. In this case, the stuff insertion bit J2 in the data of the stuff multiframe 400 is discarded without being written in the memory 162 (step S605), and the process proceeds to step S607. If the detection result of the stuff control bit 410 is negative stuff control (step S603: CASE3), negative stuff control is performed. In this case, the data stored in the stuff multiframe 400 is written to the memory 162 by an extra one clock (step S606), and the process proceeds to step S607.

  Thereafter, the PLL circuit 163 reproduces the clock based on the amount of data written in the memory 162 (step S607). Then, the sub-multiframe detection circuit 164 reads out data corresponding to the data amount of the sub-multiframe from the memory 162 using the reproduction clock (1.544 Mbit / s) output from the PLL circuit 163, and outputs the sub-multiframe. Detection is performed (step S608). At this time, since the data written in the memory 162 is a payload (actual data), the clock rate is 1.540 Mbit / s. Accordingly, the sub-multiframe detection circuit 164 synchronously detects and reads the position of the time slot (TS1 to 24) while intermittently pausing data from the memory 164. Then, actual data (internal data channel and game alarm transfer bit S) is extracted from the sub-multiframe payload read from the memory 162. Thereafter, 24 multiframe bits of the primary group interface are added by the primary group multiframe reproduction circuit 165 and output from the output terminal 107 as the primary group interface (step S609).

  According to the configuration of the first embodiment described above, stuff control can be performed at the transmission rate (1.544 Mbit / s) of the primary group interface, and transmission relay using an independent asynchronous clock can be performed at the same transmission rate of 1.544 Mbit / s. The primary group interface can be played back later. At this time, the game alarm information can be transmitted simultaneously without losing the actual data included in the 24 channels. As a result, in xDSL transmission systems such as ADSL using a telephone line, data transfer at a primary group interface transmission rate (1.544 Mbit / s) is guaranteed over a long distance (for example, from a relay station to 7 km). can do.

(Embodiment 2)
The second embodiment of the present invention is a case where the signal supplied from the input terminal 101 is 12 multiframes of the primary group interface (1.544 Mbit / s digital hierarchy interface). The configuration of the staff synchronization control apparatus in the second embodiment is the same as that in the first embodiment (see FIG. 1).

  FIG. 7A is a chart of 12 multiframes of the primary group interface. The 12 multi-frame 700 is a signal input from the input terminal 101, and in the figure, the 12 multi-frame (MF1 to 12) data 701 and 702 and the contents of MF1 are shown in detail. One frame MF1 is composed of control bits (F bits) 201 and TS (1 to 24) bits. The TS1 bit is composed of 8 bits (B1 to B8). TS2 to 24 bits in one frame MF1 are a payload and actual data is stored.

  FIG. 7-2 is a chart showing a 12 multiframe format of the primary group interface. The F bit 201 of 12 multiframes (MF1 to MF12) is used for the frame synchronization bit FAS201a and the game alert transfer bit S201b.

  The 12 multiframes (MF1 to MF12) are input to the primary group multiframe receiving circuit 111 shown in FIG. 1, and 12 multiframe synchronization detection is performed. In this case, the reception timing of 12 multiframes is set to once every two times, and data and multiframe synchronization timing are output to the sub-multiframe generation circuit 112. As a result, the configuration described in Embodiment 1 (see FIG. 1) is used as it is, and sub-multiframe conversion is performed on 12 multiframes.

  In the reception destuffing unit 106, the primary group multiframe generation circuit 165 generates a signal of 12 multiframe configuration, thereby reproducing and outputting 12 multiframes of the primary group interface (1.544 Mbit / s digital hierarchy interface). Do.

  FIG. 8 is a flowchart showing processing on the transmission side according to the second embodiment. First, the primary group multiframe detection circuit 111 detects synchronization of 12 multiframes of the primary group interface (step S801). Next, the sub multi-frame generation circuit 112 removes some of the 24 F bits composed of two 12 multi-frame bits, and sub-frames at a slightly lower bit rate (1.540 Mbit / s). Multi-frame data is formed (step S802). Thereafter, the sub-multiframe generation circuit 112 writes the sub-multiframe data to the memory 113 (step S803).

  Next, the stuff control circuit 114 compares the amount of write data in the memory 113 with the amount of read data (step S804). When the data amount of the write data matches the data amount of the read data (step S804: CASE 1), the staff control is not performed (step S805), and the process proceeds to step S808. If the amount of read data is larger than the amount of write data (step S804: CASE2), regular stuff control is performed (step S806), and the process proceeds to step S808. In the normal stuff control, dummy data is inserted into the stuff insertion bit J2 of the stuff multiframe. When the amount of write data is larger than the amount of read data (step S804: CASE3), negative stuff control is performed (step S807), and the process proceeds to step S808. In the negative stuff control, an extra one clock is read from the memory 113 and stored in the data insertion bit J1 of the stuff multiframe.

  Thereafter, the stuff multi-frame generation circuit 115 generates the stuff multi-frame 400 with the free-running clock of the oscillation unit 132 used for transmission relay, and the data read from the memory 113 is stored in the multi-frame payload as the stuff control circuit. The data is stored according to the staff control instruction 114. At the same time, the stuff control bit 410 in the bits of the stuff multiframe 400 is set (step S808). The generated stuff multi-frame data is transmitted from the transmission circuit 131 to the transmission path 104 (step S809), and the processing on the transmission side ends. The bit rate of the stuffed multiframe 400 to be transmitted is the same transmission rate as that of the primary group interface (1.544 Mbit / s).

  FIG. 9 is a flowchart showing processing on the receiving side according to the second embodiment. First, the receiving circuit 151 receives stuff multiframe data transmitted via the transmission path 104 (step S901). Next, the stuff multi-frame detection circuit 164 detects the synchronization of the stuff multi-frame 400 and extracts the stuff control bit 410 (step S902).

  Next, the stuff multi-frame detection circuit 164 determines the setting contents of the stuff control bit 410 and performs stuff control for each setting (step S903). When the detection result of the stuff control bit 410 indicates no stuff control (step S903: CASE1), the data excluding the stuff control bit 410 of the stuff multiframe 400 is written into the memory 162 (step S904), and the process proceeds to step S907. On the other hand, if the detection result of the stuff control bit 410 is the correct stuff control (step S903: CASE2), the correct stuff control is performed. In this case, the stuff insertion bit J2 in the data of the stuff multiframe 400 is discarded without being written to the memory 162 (step S905), and the process proceeds to step S907. If the detection result of the stuff control bit 410 is negative stuff control (step S903: CASE 3), negative stuff control is performed. In this case, the data stored in the stuff multiframe 400 is written in the memory 162 by an extra one clock (step S906), and the process proceeds to step S907.

  Thereafter, the PLL circuit 163 regenerates the clock based on the data amount written in the memory 162 (step S907). Then, the sub-multiframe detection circuit 164 reads out data corresponding to the data amount of the sub-multiframe from the memory 162 using the reproduction clock (1.544 Mbit / s) output from the PLL circuit 163, and outputs the sub-multiframe. Detection is performed (step S908). At this time, since the data written in the memory 162 is a payload (actual data), the clock rate is 1.540 Mbit / s. Accordingly, the sub-multiframe detection circuit 164 synchronously detects and reads the positions of the two multiframe time slots (TS1 to 12) while intermittently pausing the data from the memory 164. Then, actual data (internal data channel and game alarm transfer bit S) is extracted from the payload of the sub-multiframe data read from the memory 162. Thereafter, 12 multiframe bits of the primary group interface are added by the primary group multiframe reproduction circuit 165 and output from the output terminal 107 as the primary group interface (step S909).

  As described above, according to the second embodiment, 12 multiframe inputs of the primary group interface (1.544 Mbit / s digital hierarchy interface) are transmitted as sub-multiframes, and are received and received. Output by the primary group interface (1.544 Mbit / s digital hierarchy interface) can be performed. Also in the second embodiment, quality assurance of data transfer can be performed using the game alert information bit DL201b.

(Embodiment 3)
Next, a third embodiment of the present invention will be described. In the third embodiment, transmission relay apparatuses are connected in multiple stages in order to increase the transmission distance. FIG. 10 is a block diagram showing a transmission relay apparatus that performs stuff control according to the present invention.

  The transmission relay apparatus 1000 includes a transmission relay apparatus 1001 on the reception side, a transmission destuff / stuff unit 1002, and a transmission relay apparatus 1003 on the transmission side. Reference numeral 1004 denotes an input terminal, and reference numeral 1005 denotes an output terminal. The transmission relay device 1001 includes a reception circuit 1011 that receives a signal input from the transmission path 104. The transmission destuff / stuff unit 1002 includes a stuff multiframe detection circuit 1021, a memory 1022, a stuff control circuit 1023, and a stuff multiframe generation circuit 1024. The transmission relay device 1003 on the transmission side includes a transmission circuit 1031 and an oscillation unit 1032 having an independent oscillation frequency (1.544 Mbit / s) unique to the transmission relay device 1003.

  A signal supplied from the transmission path 104 (see FIG. 1) to the input terminal 1004 is a stuff multi-frame signal transmitted from the transmission relay apparatus 103 (see FIG. 1) at the previous stage. This stuff multi-frame signal is received by the transmission relay device 1001 on the receiving side and is input to the transmission destuff / stuff unit 1002. The signal input to the transmission destuffing / stuffing unit 1002 is subjected to stuffing multiframe synchronization detection by the stuffing multiframe detection circuit 1021, and stuff control bits 410 are extracted. If the extracted stuff control bit 410 is negative stuff, the data stored in the data insertion bit J1 of the stuff multi-frame is written in the memory 1022 by one extra clock.

  On the other hand, if the stuff is positive, only the sub-multiframe data (actual data) can be written in the memory 1022 by discarding the stuff insertion bit J2 without writing it in the memory 1022.

  The stuff control circuit 1023 and the stuff multi-frame generation circuit 1024 compare the data amount written in the memory 1022 with the data amount obtained by omitting several bits of frame bits (F bits) from the stuff multi-frame format. If there is a lot of data written as a result of comparison, the stuff control is set as negative stuff, and an extra read from the memory 1022 is inserted into the data insertion bit J1 prepared on the frame bit (F bit). To do. On the other hand, when the amount of data written is small, the stuff control is set as the normal stuff, and the reading from the memory 1022 is reduced by one clock, and the stuff insertion bit J2 is inserted into the data. Thus, the memory amount of the memory 1022 can be adjusted, and the read sub-multiframe data can be stuff-multiplexed within the stuff multi-frame 400 format.

  In the stuff multi-frame generation circuit 1024, the stuff multi-frame 400 including the stuff control signal determined by the stuff control circuit 1023 is converted into a free-running clock (1.544 Mbit) of the oscillation unit 1032 provided in the transmission relay device 1003 on the transmission side. / S) and transmitted to the transmission path 104.

  As described above, according to the third embodiment, when the stuff multi-frame is relayed, the stuff control is executed again when switching to the original clock of the transmission relay device. By connecting transmission relay devices in multiple stages in this way, the transmission distance can be increased and the quality of data transmission can be improved. In addition, since the transmission relay apparatus 1000 does not need to use a PLL circuit, it is possible to relay stuff multiframes between asynchronous clocks while minimizing the hardware scale and minimizing the transmission delay time.

(Embodiment 4)
Next, the fourth embodiment of the present invention is a configuration for easily confirming the signal quality for each section of the transmission line relay in the first to third embodiments and the signal quality through all the sections. The sub-multiframe used in the fourth embodiment is the same as the sub-multiframe 300 (see FIG. 3A) described in the first embodiment, and a description thereof is omitted. The basic configuration of the staff synchronization control apparatus according to the fourth embodiment is the same as that of the first embodiment (see FIG. 1), and the characteristic configuration will be described with reference to FIG.

  FIG. 11A is a diagram illustrating an example of a sub-multiframe format in the fourth embodiment. The sub-multiframe generation circuit 112 illustrated in FIG. 1 has the format illustrated in FIG. 11A for the sub-multiframe 300 illustrated in FIG. As the frame bit (F bit) 301a, a 6-bit frame synchronization bit FAS1101 and a 6-bit CRC 1102 are allocated. The CRC 1102 stores, for example, all the bits one subframe before the submultiframe and a calculation result based on a predetermined error rate calculation formula (for example, CRC-6) when the F bit is set to “1”. A stuff multiframe 400 generated by the stuff multiframe generation circuit 115 shown in FIG. 1 is the same as that shown in FIG.

  FIG. 11-2 is a chart showing a format of a stuff multiframe 1110 according to the fourth embodiment. As shown in FIG. 11B, the stuff multiframe generation circuit 115 generates a stuff multiframe frame bit (F bit 1111) to be generated, a 6-bit frame synchronization signal FAS1111a, CRC1111c (error rate calculation result by CRC-6 or the like when all the bits before one multiframe of the stuff multiframe and the F bit are set to “1”) is assigned. The illustrated stuff control bit 1111b can be composed of a total of 12 bits of C11, C12, C21, C22, PC, and J1, as in the first embodiment. In addition, as shown in the figure, it may be constituted by C1, C2, P1, P2, J1 (P3), unused D, and a game alarm transfer bit S. In the configuration example of FIG. 11B, the stuff control is performed twice, and the control result 1112a of the first stuff control and the control result 1112b of the second stuff control are stored.

  In the stuff multi-frame format shown in FIG. 2-2 described in the first embodiment, the stuff control bit (C11, C12, C21, C22, PC) and the data insertion bit (J1) are used in one stuff control. A total of 6 frame bits (F bit 201) were used. However, as in the fourth embodiment, even when the function of using frame bits (F bit 1111) is increased in CRC 1102 and the like, it is necessary to secure the 1-bit area as the transfer bit S for game alarm. The control bit must be 5 bits or less.

  FIG. 12 is a table showing an example of setting of stuff control bits used in the fourth embodiment. The stuff control circuit 114 (see FIG. 1) on the transmission side uses C1 and C2 as stuff control bits 1111b. When C1 and C2 of the stuff control bits 1111b are “10”, positive stuff control is indicated, when “11” is indicated, stuffless control is indicated, and when “00” is indicated, negative stuff control is indicated. P1 represents an odd parity with C1 and C2. P2 represents the odd parity of C1. P3 represents the odd parity of C2. P3 is used as the data insertion bit J1 during negative stuffing. Thus, 5 bits can be used for the stuff control bits (C11, C12, C21, C22, PC) 1111b and the data insertion bit J1. The margin of 1 bit can be used as a game alarm transfer bit S, and the quality of data transfer can be maintained.

  FIG. 13 is a flowchart showing a stuff determination process using the stuff control bit shown in FIG. The processing contents of the staff control in the PLL circuit 163 on the receiving side are shown. On the receiving side, even if an error of 1 bit or less occurs in the stuff control bit 410, it is necessary to control the stuff control without error. In the following processing, there is a condition that there is no error of 2 bits or more in 5 bits.

  First, if P1 of the stuff control bit 410 is normal (step S1301: Yes), both C1 and C2 are determined to be normal (step S1302). When the values of C1 and C2 are “10”, it is determined as positive stuff control, when “11”, it is determined as no stuff control, and when “00”, it is determined as negative stuff control. If P1 is not normal (when abnormal) (step S1301: No), the process proceeds to step S1303, and the process is terminated.

  In step S1303, if P2 is normal (step S1303: Yes), C1 is determined to be normal (correct value) (step S1304), and the process proceeds to step S1306. If P2 is abnormal (step S1303: No), it is determined that C1 is incorrect, a value obtained by inverting the value of C1 is determined as C1 (step S1305), and the process proceeds to step S1306. In step S1306, if the value of C1 is “0” (step S1306: Yes), it is determined as negative stuff control (step S1307), and the process ends. If the value of C1 is “1” (step S1306: No), the process proceeds to step S1308.

  In step S1308, if P3 is normal (step S1308: Yes), C2 is determined to be normal (correct value) (step S1309), and the process proceeds to step S1311. If P3 is abnormal (step S1308: No), it is determined that C2 is incorrect, a value obtained by inverting the value of C2 is determined as C2 (step S1310), and the process proceeds to step S1311. In step S1311, if the value of C2 is “0” (step S1311: Yes), it is determined that the regular stuff control is performed (step S1312), and the process ends. If the value of C2 is not “0” (step S1311: No), it is determined that there is no stuffing control (step S1313), and the process ends.

  According to the fourth embodiment, by adding the CRC 1111c described above, the stuff multiframe detection circuit 161 (see FIG. 1) and the stuff multiframe detection circuit 1021 (see FIG. 10) in which transmission relay apparatuses are connected in multiple stages are used. The error rate can be calculated by calculation using the CRC 1102 value of the stuff multiframe 400. Thereby, the individual signal quality in each transmission section can be confirmed.

  In addition, the sub-multiframe detection circuit 164 (see FIG. 1) provided at the final stage of the transmission path 104 can calculate an error rate by calculating the CRC 1102 of the sub-multiframe 400. Thereby, the signal quality through all the relay sections of the transmission path 104 can be confirmed.

  In the fourth embodiment, the signal quality is confirmed using the CRC. However, in addition to using the CRC, an 11-bit frame synchronization signal and a 1-bit parity bit are added to the frame bit (F bit 1111). By assigning them, sub-multiframes and stuff multi-frames can be generated to check the signal quality.

(Configuration of data relay system)
FIG. 14 is a block diagram showing the overall configuration of a data relay system using the staff synchronization control device of the present invention. FIG. 14 shows a data relay system from a communication terminal to another communication terminal via a transmission relay terminal device, a transmission path, and a relay device.

  Data transmitted from the communication terminal A1401 is multiplexed on the primary group interface (1.544 MHz) by the terminal station multiplexer A1402. The terminal multiplexer A1402 transmits data to the partner communication terminal B1407 by sending and receiving data to and from the partner terminal multiplexer B1406 via the primary group interface. The terminal station multiplexer B 1406 outputs data to the communication terminal B in synchronization with the terminal station multiplexer A.

  When the terminal station multiplexer A1402 and the terminal station multiplexer B1406 are directly connected, a maximum of about 400 m is the limit for communication. The transmission path 104 is configured to extend the transmission distance that can be relayed to the section L of the transmission path 104 using optical communication, xDSL communication, or the like. Therefore, a transmission relay terminal device A 1403, a plurality of relay devices 1404 (1404a, 1404b, 1404c), and a transmission relay terminal device B 1405 are provided between the interfaces of the terminal station multiplexer A 1402 and the terminal station multiplexer B 1406. Build the deployed data relay system.

(About the transmission relay terminal equipment on the sending side)
A transmission relay terminal device A 1403 on the transmission side has the transmission stuff unit 102 (see FIG. 1) described above. The primary group multiframe detection circuit 111 receives the primary group interface (24 multiframes or 12 multiframes) from the terminal station multiplexer A1402. Then, according to a preset configuration, 24 multiframe multiframe synchronization timing or 12 multiframe 2 multiframe synchronization timing is output to the submultiframe generation circuit 112 together with data. Also, the game alarm information bits DL are detected from the respective formats, and the game alarm transfer bits S are output to the stuff multiframe generation circuit 115 in order to sequentially transfer them to the relay devices 1404 (1404a to 1404c) at the next stage. The 24-multiframe 200 of the primary group interface is similar to FIGS. 2-1 and 2-2, and the 12 multiframe 700 is similar to FIGS. 7-1 and 7-2.

  The sub-multiframe generation circuit 112 generates a frame synchronization signal (FAS) for sub-multiframe consisting of “001011”, which is 1 bit in 2 frames (12 bits in total) and 6 bits with respect to the F bits of the original multiframe. , 6 CRC bits (e1, e2, e3, e4, e5, e6) are allocated. Originally, the remaining 12 bits among the multiframe bits are not written to the next memory 113, so that a sub-multiframe of substantially 1.540 Mbit / s is configured. The sub-multiframe 300 generated by the sub-multiframe generation circuit 112 is the same as that shown in FIGS.

  The stuff multi-frame generation circuit 115 self-runs and generates a stuff multi-frame based on the clock of the oscillator 1403 b used in the line driver (LINE DRIVER) 1403 a. Here, a stuff multi-frame composed of 24 frame bits is formed by forming one frame with 385 bits and a 24-multi-frame configuration. The stuff multiframe 400 is the same as that shown in FIGS.

  As shown in FIG. 11B, the stuff multi-frame format is a stuff multi-frame frame synchronization bit FAS1111a composed of 6-bit “001011” and a 6-bit CRC (e1, e2, e3, e4, e5, e6). ) 1111c and stuff control bit 1111b (including game alarm transfer bit S) for performing stuff control twice in 24 multiframes (6 × 2 bits (C1, C2, P1, P2, P3 / J1)) The setting example of the stuff control bit 1111b is the same as that of Fig. 12. In particular, P3 represents the odd parity of C2, but in the case of negative stuffing, the data insertion bit J1 is assigned. 4-12, the 12th multiframe and the 24th multiframe are used. The first bit is used as a stuff insertion bit J2 for storing dummy data at the time of positive stuffing, and the unused D bit is used for any information between the transmission relay terminal device A 1403 and the relay device 1404. Can also be used to communicate.

  The stuff control circuit 114 compares the amount of data written in the memory 113 with the amount of data excluding the frame bits from the stuff multiframe format generated by the stuff multiframe generation circuit 115. If there is a large amount of written data, the stuff control is set as negative stuff, and one extra clock read from the memory 113 is read and inserted into the data insertion bit J1 prepared on the frame bit. On the other hand, when the amount of data written is small, the amount of memory 113 is adjusted by inserting the dummy data into the stuff insertion bit J2 in the data by reducing the number of clocks read from the memory 113 by setting the stuff control as the positive stuff, The read sub-multiframe data is stuff-multiplexed in the stuff multi-frame format.

  Since a signal in which sub-multiframe data is stuff-multiplexed by stuff multi-frame is operated by a clock used in LINE DRIVER 1403a, LINE DRIVER 1403a transmits input digital data over a long distance such as an optical signal or an xDSL signal. The signal can be modulated without any problem, and can be transmitted to the next-stage relay apparatus 1404a, 1404b, 1404c, or the transmission relay terminal apparatus B 1405.

(About relay device)
A description will be given using one relay device 1404a as the relay device 1404. This relay apparatus 1404a is arranged between a line receiver (LINE RECEIVER) 1410 arranged on the reception side, a line driver (LINE DRIVER) 1411 arranged on the transmission side, and between these line receivers 1410 and the line driver 1411. The transmission relay staff unit 1412 is configured. A line receiver (LINE RECEIVER) 1410 demodulates an optical signal received from the transmission path 104 or a modulated signal such as an xDSL signal into digital data, and together with the extracted clock, a stuff multiframe detection circuit 1413 of the transmission relay stuff unit 1412. Output to.

  A stuff multiframe detection circuit 1413 provided in the transmission relay stuff unit 1412 performs stuff multiframe synchronization detection and extracts stuff control bits. If the detected stuff control bit is negative stuff, the data stored in the stuff multi-frame bit is written in the memory 1414 by one extra clock. If it is positive stuff, the stuff insertion bit J2 is discarded without being written to the memory 1414, so that only the sub-multiframe data is written to the memory 1414. Further, CRC 1111c (see FIG. 11-2) in the stuff multi-frame bit performs CRC calculation of the stuff multi-frame data to calculate an error rate. When a predetermined threshold is exceeded, a signal quality alarm in the relay section is generated. . Further, the game alarm transfer bit S in the stuff multiframe bit is extracted and output to the stuff multiframe generation circuit 1416 for transfer to the relay device 1404b in the next stage.

  The configurations and operations of the memory 1414, the stuff control circuit 1415, and the stuff multiframe generation circuit 1416 provided in the transmission relay stuff unit 1412 are the same as the operations of the transmission relay terminal device A 1403.

  Since the signal in which the sub-multiframe data is stuff-multiplexed again by the stuff multi-frame by the transmission relay stuff unit 1412 operates at the clock (1.544 MHz) used in the LINE DRIVER 1411, the LINE DRIVER 1411 receives the input digital signal. Data can be modulated into a long-distance transmission signal such as an optical signal or an xDSL signal without any problem, and can be transmitted to the next-stage relay devices 1404b and 1404c and the transmission relay terminal device B 1405.

(Receiving side transmission relay terminal equipment)
The reception-side transmission relay terminal apparatus B 1405 includes a line receiver (LINE RECEIVER) 1421 on the reception side. The line receiver 1421 demodulates an optical signal received from the transmission path 104 or a modulated signal such as an xDSL signal into digital data, and outputs it to the reception destuff unit 106 together with the extracted clock. The configuration of the reception destuffing unit 106 is the same as that in FIG.

  The stuff multiframe detection circuit 161 provided in the reception destuffing unit 106 performs stuff multiframe synchronization detection and extracts stuff control bits. If the detected stuff control bit is negative stuff, the data stored in the stuff multi-frame bit is written in the memory 162 by one clock. If it is positive stuff, the stuff insertion bit J2 is discarded without being written to the memory 162. As a result, only the sub-multiframe data is written into the memory 162. Also, CRC calculation of stuff multi-frame data is performed by CRC 1111c (see FIG. 11-2) in the stuff multi-frame bit, an error rate is calculated, and a signal quality alarm in the relay section is generated when a predetermined threshold is exceeded. . Also, the game alarm transfer bit S in the stuff multi-frame bit is extracted and output to the primary group multiframe reproduction circuit 165 in order to transmit the game alarm transfer information to the terminal station multiplexer B 1406 through the primary group interface.

  The PLL circuit 163 extracts the received stuff control bits based on positive stuff, negative stuff, and no stuff control, performs phase comparison based on the data amount of the sub-multiframe data, and inputs it to the transmission relay terminal device A1403. The clock of the primary group interface (1.544 Mbit / s digital hierarchy interface) is regenerated.

  The sub-multiframe detection circuit 164 reads a signal from the memory 162 only by the amount corresponding to the sub-multiframe data amount with the above-described reproduction clock. The sub-multiframe data read from the memory 162 is extracted from the internal data channel by the sub-multiframe detection circuit 164, and the primary multi-frame reproduction circuit 165 outputs 24 multiframes or 12 multiframes according to a preset configuration. The frame bit is added and transmitted to the terminal station multiplexer B 1406.

  According to the data relay system described above, the relay device 1404 is arranged for each required distance according to the length of the transmission path 104, and these can be connected in multiple stages, thereby extending the transmission distance in the section L. It becomes like this. Further, since the CRC and the game alarm transfer bit S can be transferred together with the actual data, an alarm can be output immediately when a failure occurs, and the quality of data transmission can be improved.

  As described above, according to the stuff synchronization control device, the relay device, the data relay system, and the stuff synchronization control method, all the input primary group interface data is transmitted to the primary group interface using an independent asynchronous clock. Transmission can be performed at the same transmission speed as the speed of 1.544 Mbit / s, and the input primary group interface can be reproduced in the subsequent stage. Since the stuff control is performed by effectively using the limited frame bit area, a transmission relay having an independent asynchronous clock becomes possible. In particular, information such as game alerts can be transmitted together with actual data of all channels, and the quality of data transmission can be improved.

  The staff synchronization control method described in this embodiment can be realized by executing a program prepared in advance on a computer such as a personal computer or a workstation. This program is recorded on a computer-readable recording medium such as a hard disk, a flexible disk, a CD-ROM, an MO, and a DVD, and is executed by being read from the recording medium by the computer. Further, this program may be a transmission medium that can be distributed via a network such as the Internet.

(Supplementary Note 1) Primary group multiframe detection means for detecting synchronization of a predetermined number of multiframes of the input primary group interface;
Sub-multiframe generation means for assigning frame bits of the multiframe detected by the primary group multiframe detection means to frame synchronization bits and generating submultiframes at a bit rate lower than the bit rate of the primary group interface; ,
Stuff multiframe generation means for generating a stuff multiframe by multiplexing the submultiframe generated by the submultiframe generation means;
Transmission means for transmitting the stuff multi-frame generated by the stuff multi-frame generation means to a transmission line,
The stuff multi-frame generating means assigns the bit of the frame synchronization information, the bit of the stuff control information, and the data insertion bit at the time of negative stuff of the stuff control to the frame bits of the stuff multi-frame, and the primary group interface The stuff synchronization control apparatus is characterized in that the stuff multi-frame is generated with an independent asynchronous clock having the same bit rate as the above.

(Supplementary Note 2) Stuff multiframe detection means for performing synchronization detection of a stuff multiframe received via a transmission path and extracting a stuff control bit;
Sub-multiframe detection means for performing destuffing corresponding to the stuff control information indicated by the stuff control bits extracted by the stuff multi-frame detection means, detecting the sub-multiframe synchronously, and extracting the actual data of the sub-multiframe; ,
The primary group multiframe is reproduced by adding information on the position of a predetermined number of multiframe data channels of the primary group interface and game alert transfer information to the submultiframe detected by the submultiframe detection means. Primary group multi-frame reproduction means for
A staff synchronization control device comprising:

(Supplementary note 3) The stuff synchronization control apparatus according to supplementary note 1, wherein the primary group multi-frame detection unit receives 24 multi-frame signals of the primary group interface.

(Supplementary Note 4) The primary group multiframe detection means receives a 12 multiframe signal of the primary group interface,
The stuff synchronization control apparatus according to appendix 1, wherein the sub-multiframe generation unit generates a sub-multiframe using two frame bits of the 12 multiframes.

(Supplementary Note 5) Receiving means for receiving a stuff multi-frame via a transmission line;
Stuff multiframe detection means for extracting information of frame bits of a predetermined number of stuff multiframes received by the reception means;
Stuff multiframe generating means for re-stuffing the stuff multiframe detected by the stuff multiframe detection means based on an independent asynchronous clock at the same bit rate as the primary group interface;
Transmitting means for transmitting the stuff multi-frame generated by the stuff multi-frame generating means to a transmission line;
A relay apparatus comprising:

(Supplementary note 6) The relay device according to supplementary note 5, wherein a plurality of the relay devices are arranged for each predetermined distance of the transmission path.

(Supplementary note 7) In a data relay system including a transmission relay terminal device on a transmission side, a relay device provided on a transmission line, and a transmission relay terminal device on a reception side, and performing stuff synchronization control and transmitting a stuff multiframe ,
The transmission side relay terminal device on the transmission side is:
Primary group multiframe detection means for performing synchronization detection of a predetermined number of multiframes of the input primary group interface;
Sub-multiframe generation means for assigning frame bits of the multiframe detected by the primary group multiframe detection means to frame synchronization bits and generating submultiframes at a bit rate lower than the bit rate of the primary group interface; ,
Stuff multiframe generation means for generating a stuff multiframe by multiplexing the submultiframe generated by the submultiframe generation means;
Transmission means for transmitting the stuff multiframe generated by the stuff multiframe generation means to a transmission line,
The stuff multi-frame generating means assigns the bit of the frame synchronization information, the bit of the stuff control information, and the data insertion bit at the time of negative stuff of the stuff control to the frame bits of the stuff multi-frame, and the primary group interface And generating the stuff multi-frame with an independent asynchronous clock at the same bit rate,
The relay device is
Receiving means for receiving the stuff multi-frame transmitted from the transmission-side transmission relay terminal device via the transmission path;
Stuff multiframe detection means for extracting information of frame bits of a predetermined number of stuff multiframes received by the reception means;
Stuff multiframe generating means for re-stuffing the stuff multiframe detected by the stuff multiframe detection means based on an independent asynchronous clock at the same bit rate as the primary group interface;
Transmission means for transmitting the stuff multiframe generated by the stuff multiframe generation means to a transmission line,
The receiving side transmission relay terminal device is:
Stuff multi-frame detection means for receiving a stuff multi-frame signal transmitted from the relay device via the transmission path, performing synchronization detection of the stuff multi-frame, and extracting a stuff control bit;
Sub-multiframe detection means for performing destuffing corresponding to the stuff control information indicated by the stuff control bits extracted by the stuff multi-frame detection means, detecting the sub-multiframe synchronously, and extracting the actual data of the sub-multiframe; ,
The primary group multiframe is reproduced by adding information on the position of a predetermined number of multiframe data channels of the primary group interface and game alert transfer information to the submultiframe detected by the submultiframe detection means. Primary group multi-frame reproduction means for
A data relay system comprising:

(Supplementary Note 8) Transmission relay terminal devices provided on the transmission side and the reception side, and the relay device include error detection information in the frame bits of the multi-frames of the sub-multiframe and the stuff multi-frame. The data relay system according to appendix 7, wherein the data relay system is assigned.

(Additional remark 9) The transmission relay terminal apparatus provided in the said transmission side and the receiving side, and the said relay apparatus are a part of the said stuff control bits allocated to the said frame bit, when the result of the said stuff control is a negative stuff The data relay system according to appendix 8, wherein the data relay system is used as a data insertion bit.

(Supplementary Note 10) A primary group multiframe detection step for detecting synchronization of a predetermined number of multiframes of the input primary group interface;
A sub-multiframe generation step of assigning frame bits of the multiframe detected by the primary group multiframe detection step to frame synchronization bits, and generating a submultiframe at a bit rate lower than a bit rate of the primary group interface; ,
A stuff multiframe generation step of generating a stuff multiframe by multiplexing the submultiframe generated by the submultiframe generation step;
A transmission step of transmitting the stuff multi-frame generated by the stuff multi-frame generation step to a transmission line,
The stuff multi-frame generating step allocates a bit of the frame synchronization information, a bit of stuff control information, and a data insertion bit at the time of negative stuff of the stuff control to the frame bits of the stuff multi-frame, and the primary group interface The stuff synchronization control method is characterized in that the stuff multi-frame is generated with an independent asynchronous clock having the same bit rate as the above.

(Supplementary Note 11) A stuff multiframe detection step of performing synchronization detection of a stuff multiframe received via a transmission path and extracting a stuff control bit;
A sub-multiframe detection step of performing destuffing corresponding to the stuff control information indicated by the stuff control bits extracted by the stuff multi-frame detection step, synchronously detecting the sub-multiframe and extracting actual data of the sub-multiframe; ,
The primary group multiframe is reproduced by adding information on the position of a predetermined number of multiframe data channels of the primary group interface and game alert transfer information to the submultiframe detected in the submultiframe detection step. A primary group multi-frame reproduction process,
A staff synchronization control method comprising:

  As described above, the stuff synchronization control device, the relay device, the data relay system, and the stuff synchronization control method according to the present invention are useful for data transfer at the transmission rate of the primary group interface, and in particular, the stuff synchronization control device maintains the transmission rate. Information necessary for control can be transferred at the same time, and it is suitable for use as a transmission relay device on a transmission line such as xDSL that guarantees data transfer.

It is a block diagram which shows the structure of the staff synchronous control apparatus of this invention. It is a graph which shows 24 multi-frames of a primary group interface. It is a graph which shows the format of 24 multi-frames of a primary group interface. It is a chart which shows a sub multi-frame. It is a chart which shows a sub multi-frame format. It is a graph which shows an example of a staff multi-frame. It is a chart which shows an example of a staff multi-frame format. It is a graph which shows an example of the stuff control result allocated to a stuff control bit. 3 is a flowchart showing processing on the transmission side according to the first embodiment. 3 is a flowchart showing processing on the receiving side according to the first embodiment. It is a chart which shows 12 multiframes of a primary group interface. It is a graph which shows the format of 12 multiframes of a primary group interface. 10 is a flowchart showing processing on the transmission side according to the second embodiment. 10 is a flowchart illustrating processing on the reception side according to the second embodiment. It is a block diagram which shows the transmission relay apparatus which performs the staff control of this invention. 10 is a table showing an example of a sub-multiframe format in a fourth embodiment. 12 is a chart showing a stuff multi-frame format according to the fourth embodiment. 10 is a chart showing an example of setting stuff control bits used in the fourth embodiment. It is a flowchart which shows the staff determination process using the stuff control bit shown in FIG. It is a block diagram which shows the whole structure of the relay system using the staff synchronous control apparatus of this invention.

Explanation of symbols

101 Input terminal 102 Transmission staff 103 Transmission relay device (transmission side)
104 Transmission path 105 Transmission relay device (receiving side)
106 reception destuff unit 107 output terminal 111 primary group multiframe detection circuit 112 submultiframe generation circuit 113 memory 114 stuff control circuit 115 stuff multiframe generation circuit 161 stuff multiframe detection circuit 162 memory 163 PLL circuit 164 submultiframe detection circuit 165 Primary group multiframe reproduction circuit 1401 Communication terminal A
1402 Terminal Multiplexer A
1403 Transmission relay terminal equipment A
1403a, 1411 LINE DRIVER
1404 Relay device 1405 Transmission relay terminal device B
1406 Terminal station multiplexer B
1407 Communication terminal B
1410, 1421 LINE RECEIVER
1413 Stuff multi-frame detection circuit 1414 Memory 1415 Stuff control circuit 1416 Stuff multi-frame generation circuit

Claims (5)

Primary group multiframe detection means for performing synchronization detection of a predetermined number of multiframes of the input primary group interface;
Sub-multiframe generation means for assigning frame bits of the multiframe detected by the primary group multiframe detection means to frame synchronization bits and generating submultiframes at a bit rate lower than the bit rate of the primary group interface; ,
Stuff multiframe generation means for generating a stuff multiframe by multiplexing the submultiframe generated by the submultiframe generation means;
Transmission means for transmitting the stuff multi-frame generated by the stuff multi-frame generation means to a transmission line,
The stuff multi-frame generating means assigns the bit of the frame synchronization information, the bit of the stuff control information, and the data insertion bit at the time of negative stuff of the stuff control to the frame bits of the stuff multi-frame, and the primary group interface The stuff synchronization control apparatus is characterized in that the stuff multi-frame is generated with an independent asynchronous clock having the same bit rate as the above. Stuff multiframe detection means for performing synchronization detection of the stuff multiframe received via the transmission line and extracting the stuff control bit;
Sub-multiframe detection means for performing destuffing corresponding to the stuff control information indicated by the stuff control bits extracted by the stuff multi-frame detection means, detecting the sub-multiframe synchronously, and extracting the actual data of the sub-multiframe; ,
The primary group multiframe is reproduced by adding information on the position of a predetermined number of multiframe data channels of the primary group interface and game alert transfer information to the submultiframe detected by the submultiframe detection means. Primary group multi-frame reproduction means for
A staff synchronization control device comprising: Receiving means for receiving a stuff multi-frame via a transmission line;
Stuff multiframe detection means for extracting information of frame bits of a predetermined number of stuff multiframes received by the reception means;
Stuff multiframe generating means for re-stuffing the stuff multiframe detected by the stuff multiframe detection means based on an independent asynchronous clock at the same bit rate as the primary group interface;
Transmitting means for transmitting the stuff multi-frame generated by the stuff multi-frame generating means to a transmission line;
A relay apparatus comprising: In a data relay system that includes a transmission relay terminal device on the transmission side, a relay device provided on the transmission path, and a transmission relay terminal device on the reception side, performs stuff synchronization control and transmits a stuff multiframe,
The transmission side relay terminal device on the transmission side is:
Primary group multiframe detection means for performing synchronization detection of a predetermined number of multiframes of the input primary group interface;
Sub-multiframe generation means for assigning frame bits of the multiframe detected by the primary group multiframe detection means to frame synchronization bits and generating submultiframes at a bit rate lower than the bit rate of the primary group interface; ,
Stuff multiframe generation means for generating a stuff multiframe by multiplexing the submultiframe generated by the submultiframe generation means;
Transmission means for transmitting the stuff multiframe generated by the stuff multiframe generation means to a transmission line,
The stuff multi-frame generating means assigns the bit of the frame synchronization information, the bit of the stuff control information, and the data insertion bit at the time of negative stuff of the stuff control to the frame bits of the stuff multi-frame, and the primary group interface And generating the stuff multi-frame with an independent asynchronous clock at the same bit rate,
The relay device is
Receiving means for receiving the stuff multi-frame transmitted from the transmission-side transmission relay terminal device via the transmission path;
Stuff multiframe detection means for extracting information of frame bits of a predetermined number of stuff multiframes received by the reception means;
Stuff multiframe generating means for re-stuffing the stuff multiframe detected by the stuff multiframe detection means based on an independent asynchronous clock at the same bit rate as the primary group interface;
Transmission means for transmitting the stuff multiframe generated by the stuff multiframe generation means to a transmission line,
The receiving side transmission relay terminal device is:
Stuff multi-frame detection means for receiving a stuff multi-frame signal transmitted from the relay device via the transmission path, performing synchronization detection of the stuff multi-frame, and extracting a stuff control bit;
Sub-multiframe detection means for performing destuffing corresponding to the stuff control information indicated by the stuff control bits extracted by the stuff multi-frame detection means, detecting the sub-multiframe synchronously, and extracting the actual data of the sub-multiframe; ,
The primary group multiframe is reproduced by adding information on the position of a predetermined number of multiframe data channels of the primary group interface and game alert transfer information to the submultiframe detected by the submultiframe detection means. Primary group multi-frame reproduction means for
A data relay system comprising: A primary group multiframe detection step for detecting synchronization of a predetermined number of multiframes of the input primary group interface;
A sub-multiframe generation step of assigning frame bits of the multiframe detected by the primary group multiframe detection step to frame synchronization bits, and generating a submultiframe at a bit rate lower than a bit rate of the primary group interface; ,
A stuff multiframe generation step of generating a stuff multiframe by multiplexing the submultiframe generated by the submultiframe generation step;
A transmission step of transmitting the stuff multi-frame generated by the stuff multi-frame generation step to a transmission line,
The stuff multi-frame generating step allocates a bit of the frame synchronization information, a bit of stuff control information, and a data insertion bit at the time of negative stuff of the stuff control to the frame bits of the stuff multi-frame, and the primary group interface The stuff synchronization control method is characterized in that the stuff multi-frame is generated with an independent asynchronous clock having the same bit rate as the above.

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