JPS61113087A - Image signal processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] 1 chestnut top p1"I"L.

The present invention relates to an image signal processing apparatus, and more particularly to an image signal processing apparatus having a bitmap type image signal generating apparatus.

In general, CRT (Catl+ode Ray T
In character display devices using ``Ube'' and dot printers that print computer output, character information is communicated and stored in character code units, and when outputting, the stored character codes are read out sequentially and printed on each character hood. There is known a so-called character map type image signal generating device which refers to a 7-ont memory and obtains an image dot signal in synchronization with an image clock signal.

However, in recent years, with the development of post-processing devices such as personal computers, functions that are difficult to handle using the character map method, such as processing graphic image signals and controlling character writing positions, are now required on the output side. For this reason, display devices and printers are increasingly adopting a bitmap method that has a bit memory for one page of image data.

Although the bitmap method has the disadvantage of being more expensive than the character map method, it not only has the advantage of being compatible with graphic images, but also has the advantage of being able to handle character writing positions, etc. when used in a character signal generator. It has the advantage of being able to respond flexibly to future functional requests.

On the other hand, in the bitmap method, the storage device needs to have a storage area that corresponds to one page of dot data. In order to be able to print in any horizontal position, it is necessary to secure a storage area large enough to accommodate a square whose sides are the long sides of the paper being used, resulting in an unnecessarily large memory size. It had the inconvenience of being stored away.

Therefore, it is an object of the present invention to provide an image signal processing device that uses a memory corresponding to the size of the paper and can obtain print output in both the vertical and horizontal positions. It is something.

Specifically, the present invention uses N bits x M bytes (number of banks =
K) is a circuit for outputting an address signal when accessing the image memory, and is a column address counter that performs a counting operation based on an access timing clock, outputs a signal every M counts, and repeatedly performs the counting operation. and a row address counter that performs a counting operation based on the output of the column address counter and outputs a signal every time the count value reaches the number of rows in the bank.
The column address counter is divided into upper 91 bits and lower 92 bits, and the upper l is counted by the access timing clock.
A 1-bit counter is operated, a bank counter is operated by a signal outputted every predetermined number of counts from this upper 91-bit counter, and the row address counter is operated by a signal outputted every time the bank counter counts. and switching the count operation signal of each counter so that the lower 12-bit counter is operated by the signal output every time the row address counter reaches the number of rows in the bank. The count contents of the bit counter and the lower l2 pit counter are (l,
The image memory is characterized by having an access mode for the image memory in which data of +l□) bits and 2 bits is taken out and this is used as a column address signal.

Wari 1 broom Embodiments of the present invention will be described below with reference to the drawings.

Figure 1 shows a bitmap type image signal processing device (100
) is a block diagram schematically showing the system configuration of a dot printer (1) (for example, a laser beam recording device).
The signal processing procedure in the printer (1) including the printer (1) will now be briefly explained.

In addition, from the technical content of the present invention, printer (1)
Although illustration and explanation of the specific configuration will be omitted,
In the following, a laser beam is scanned and projected onto a photoreceptor surface by an optical system including a polygon mirror, etc., while being modulated by a modulator using an image signal to be described later, as described in, for example, Japanese Unexamined Patent Publication No. 48-49315. An example will be explained in which a print image is formed on recording paper using a known electrophotographic process.

The printing operation of the printer (1) is performed by the image signal processing device (
100), an image reading device (IF() (3)) or a sorter (4) for sorting printed recording paper, and is controlled by a device control unit (101) to be described later.A host computer ( The data signal including the character code transmitted from 2) is converted into the Pi1 map (hereinafter abbreviated as 87M) memory in the image signal generator (1,00) via the ink7ace. When the writing of the data for the print page is completed, the operation of the printer mechanism section (20) is started, and at an appropriate timing, the image data is sequentially read out from the B/M memory section (104) and output. 87M memory section (10
4) An image corresponding to the written bit pattern is formed on the photoreceptor, and a print image is formed on the recording paper that is synchronously conveyed.

FIG. 2 shows a specific example of the control system within the printer (1). In the figure, there is a printer (1) inside the printer (1).
) mechanical unit (20i, image reading device (3).

and a device control unit (1) that controls mechanical operations such as the sorter (4), captures data read by the image reading device (3), and outputs image dot data of the printer (1).
Based on commands transferred from the host computer (2) via the ink 7 bus circuit (105), data is written to the 87M memory (104) or data is read from the 87M memory (104). 87MC that selects modes such as data reading and outputs various commands
The PU section (102) and the B/M control section (which controls the input/output operation of the 87M memory in response to this command)
103), 87M memory (RAM) section (104), 7 ontome memory section (109), etc., 87M C
An operation panel (106) and a 7-ont selection display device (107) are connected to the PU unit.

Device control section (101), 87M CPU section (102)
The tB/M control section (103) and the 87M memory section (1,04) are each installed on the board (110), and can communicate with each other via a path line (not shown) on the board (110). . In addition, the B/M controller section (103) includes pass lines (112), (113).
) to connect the 7-ont cartridge mounting board (108) of the 7-ont memory section (109) and the pass line (114).
) is connected to the 87M CPU unit (102), and a pass line (115) is connected to the 87M memory unit (104,).

Next, regarding the signal processing procedure in the printer (1),
The control system diagram in Figure 2 and 70- in Figures 3 to 6
Explain with reference to the chart.

When the power is turned on to the printer (1), first, as shown in FIG.
A download process is executed to read data indicating the type of 7 onts. In this example, eight types of 7-ont cartridges, A to H, are removably mounted on the mounting board (108), and can be replaced with other types of cartridges as appropriate. The configuration of the 7-ont memory that stores data indicating the 7-ont type and the specific procedure for reading the same will be described later.

In Figure 3, when the power is turned on, 87M CP
A 7-ont read command is set from the CPU (87M CPt+) of the U section (102) to the command register (CMDR) of the B/M control section (103) via the interface (87M IF).
The 7-on ROM is accessed via the 7-on access controller (301) of the control section (103), and the program data is transferred to the B/M control section (10
3) is read to the status recorder (STSR), and written to the packet RAM (P-RAM) via the CPU of the B/MCPU unit (102). This operation is repeated until the data end is reached, at which point the next 7-on) ROM data is read. Through this process, the installed 7-ont type is read, which can be read out by the CPU (2), for example, to select the 7-ont type to be used when printing.

Figure 4 shows that when a print command is issued from the host CPU (2), data is written to the 87M memory section (104) according to the character code sent from the host CPU (2). The following processing is shown below.

When a character code is sent from the host CPU (2) while the RAM (P-RAM) is empty and can be written to, the host interface (105
), the Inter 7 Ace controller (I/F controller) of the 87M CPU section (102), and the 87M CPU
The hood and print position information is stored in the bucket) RAM
(P-RAM). Not printing and B/
If the MRAM is empty, the 87M CPU reads it and sets the character address and print position information (write position data) in the status register (STSR) of the B/M control section (103), and also sets the character address and print position information (write position data) in the command register ( CMI) R) Sets the data write command. Next, set data and con 1
1' l: Follow, 7 on) ROM (109-A) - (
109-H) is accessed, and the B/M control section (
87 via the 87M controller (302) of 103)
A dot pattern is written to the M memory for each character. This IJJ printing is executed repeatedly until the text for one page of print F is completed, and when the text is completed, the printing operation begins. Once the printing operation starts, writing to the 87M RAM is disabled, so the next text content is stored in the P-RAM.
It only enters. Immediately after printing is completed, this P-
The RAM is read by the CPU and the B/MR
A pattern is written to AM.

When all the characters for one page have been written into the 87M memory through the processing described above, the print processing shown in FIG. 5 is executed. In Figure 5, there are 8 print requests.
When judged by 7M CPU, 87M CPU is B/M
Command register (CMD) of control unit (103)
A print command is set in R), and the controller (302)l of B, 7M controller ll5 (103) switches to the print mode by a command, and is in a standby state until a data request signal is output.

On the other hand, the B/MCPU is the M/CC of the device control unit (101).
Sends a print operation request command to the PU and sends a print operation request command to the M/CCP [
In response to this, the driver (20) of the main body of the printer (1)
) outputs a print operation start signal. At this time,
If necessary, a control signal is outputted so that related equipment such as a sorter is also put into operation.

The recording paper is transported in accordance with the operation of the printer (1), and when it reaches a predetermined transport checkpoint, a detection signal is output from a vapor sensor (not shown), and the M/CCPU discriminates this and performs rasterization.・Start the clock generator (RCG). Along with this, the raster clock generator (RCG) generates a data request signal, and the above-mentioned 87M controller (
302) accesses the 87M memory section (104) and stores the first 8 bits of data as a raster clock.
The raster clock generator (RCG') serially converts this 8-bit data and sends it to the laser modulator (not shown) of the printer (1). Access to the 87M memory (104) is executed repeatedly in 8-bit units in this way, and when the page end is reached, the 87M controller (302) accesses the 87M memory (104).
A complete data output signal is output to the CPU, and this process is repeated until all print operations are completed. When all print operations are completed, the process proceeds to the next "end process."

Note that in the 87M memory unit (104), when a predetermined ERA command is executed, the ERASE signal becomes active and data (00) is written. Furthermore, when a print operation is executed with the ERASE signal active, the B/M address portion accessed for printing can be simultaneously erased.

FIG. 6 shows the print operation termination process. When the process shown in FIG.
It outputs processing signals such as stopping the output of the clock generator (RCG), cutting off the laser beam, starting sorter drive, and allowing IR operation. Also, M/CCPU is a printer (1)
This status signal is output to the 87MCPU, and the 87M CPU receives it and sends the host CPU a message indicating that the printing has been completed.

FIG. 7 shows an example of the configuration of the B/M memory section (104).

The memory unit (201) has a bank configuration in which, for example, 64 bits (8 bytes) of dynamic RAM are set in units of 8, and the number of banks depends on the paper size (as described later).
14 inches by 8.5 inches). In addition, in the figure, for simplification, bank No., 3 to No.
Only 6 is shown. Each bank has a RA S (RoulA address Stro
be), CAS (Column Address
5trobe) and WE (Write Enab)
le) signal is the long signal RASEN (RAS Ena
ble), CASEN (CASEnat+le) and W
It is designed to be input in response to the E N (Write Enable) signal, and each date is
The operation is controlled by an n (n=0 to 13) signal.

Also, the memory address signal (M
A Dn) (n=0-7) is input to each column (Rout) of the memory section (201) via the buffer y (203), thereby specifying the address of the RAM to be accessed. A corresponding address of a RAM in a corresponding bank is accessed by the signals R, A S n and MADn, and the RAS and CAS signals are inputted to access the bits of each RAM to write data and Perform reading.

In data writing, data outputted from the input latch (204) in synchronization with the clock signal is sent to the memory section (201) via the ORD (205) under the WE double signal input.
) is input to the data input (DI). Data is read from the accessed RA as described above.
Data at a predetermined address of M is output from the data output (Do) of the memory section (201), and under the condition that the output latch (206) is activated by the LETDO signal, the data is synchronized with the clock signal. and output to the data bus.

The data output (DO) is further inputted to the above-mentioned OR (205) via the DO (207), and
(207) is artificially closed by the ERASE signal, so
When a read operation is performed while the ERASE signal is active, the memory contents are erased.

FIG. 8 shows the configuration of the B/M control section (103) and the relationship of signal transmission and reception therein, FIG. 9 shows the details of the 87M controller (302) in it, and FIG. The details of the onto controller (301) are shown respectively.

In FIG. 8, the printer interface (303) receives laser dot data (303) via the input/output port (Pl).
LDDATAn: n = O-7) is sent out, and upon receiving the synchronization signal (LDREQ), the 87M controller (30
2) Sends the 87M access signal (MMREQ). The functions of the 7onto controller (301) are ■7
Write 7 tons to online RAM via 87 MCPU. ■Contents of 7ont RAM (109) ml/M
(Read with i PII. ■7 on FROM (
++19) contents as B,,' N+RAM(104
,)-\Transfer. ■+1/M CPT, I write data from 87M-\, etc. B/M
The controller (302) transmits two consecutive B/MRAM access signals (RA S E N , CA S
EN.

W E N , R A S n - and M A D
n etc.) to r3/MRAM part (1 (14,)
Transfer to.

As shown in the figure, various signals are exchanged between these three blocks, and the meanings and effects of each signal are summarized in Table 1. are summarized in

Table 1. -2 Table 1. -3 Zll- Table 1. -5 Table 1. -6 FIG. 9 shows details of the B/M controller (302).

The B/M controller Y roller (302) controls the B/M memory (10
4) D-RAM (see Figure 7) When writing data and reading data from D-RAN, D,
-RAN address signal (M A D n ), bank selection signal (RASn) and the above-mentioned control signal (
RASEN), (CASEN), (WEN) (LDDO
) occurs. Note that these signals are also generated when refreshing the D-RAM, but
Since the parts related to glue fresh are not directly related to the present invention, their explanation will be omitted.

The memory section (201) of the B/M memory (104) is
Bank configuration as explained in the figure (number of banks = 14
．． 64 bits/bank), and when expressed in terms of the number of dots, it corresponds to a rectangle of 2048 x 3584. If this is further applied to a printer with a dot density of 240 dots/inch, the paper size that can be handled by this memory is 8.53 inches by 14.93 inches. This state is schematically shown in FIG. Now, for a memory with such a matrix configuration, the horizontal columns in the figure are (R
oad).

The vertical column is called (Column), and each ROJ Co
lu+nn stores image data in 1-bit units, and for example, if the paper size is 8.5 inches x 14 inches, the number of columns is 2040. It can be expressed as a matrix of Rou+number 3360. Here, since the D-RAM access is performed in units of 8 bits, as mentioned above, in a memory with such a configuration, conventionally the width is 8.5 inches and the valve length is 1 inch.
For 4 inch paper, Col old on for each Road.
By sequentially specifying addresses 255 to 0, it is possible to access memory bits that correspond to the shape of the paper, but if a piece of paper of the same size is turned upside down, the memory bits that match the shape of the paper can be accessed. could not be accessed. Therefore, in order to accommodate such a paper size, in the conventional device, the memory needed to have a capacity sufficient to accommodate a 14-inch by 14-inch paper.

In the image signal processing device of the present invention, in order to solve such problems, in the B/M controller (302) shown in FIG.
By switching the operation mode of the counter regarding address designation, the memory shown in FIG.
It is now possible to handle both inch x 14 inch and 14 inch x 8.5 inch cases. That is, the 7ont access controller F roller (shown in FIG. 8 and Table 11)
The load signal and clock of each counter are switched by the LSCANi number from 301), thereby making it possible to access the memory in either direction "I" or "■" shown in the v511 diagram. In order to explain the operation of each counter in the $9 figure, the configurations of related parts are extracted and shown in FIGS. 12(A) and 12(B). In addition, Fig. 12 (A
), (B), the same components as in Figure 9 are indicated by the same symbols, and subscripts such as a, bs, c%d, etc. indicate that the components with that symbol are divided by function. .

In FIG. 12(A), first, the operation of accessing the memory shown in FIG. This is called short scan.) 8.5 inches x 11 inches corresponds to 2040 dots x 2640 dots, and the counters are 11 bits and 1
It can be expressed in 2 bits. Also, Ro@! Access in the direction is performed in byte units, so the Col0mn counter is 3.
The bits can be reduced to 8 bits (addresses are assigned in byte units in the Row direction).

These 8 bits are set in the column address register (CAR) (4, 18) in FIG.
The lower 4 bits are set in LO-CADR (4] 8b). The set value is 2040/8=255 (F
EH).

For the Column direction, among the 12 bits, the lower 8 bits are set to the row address register (RADC) (411), and the 1st 4 bits are set to the bank register (BNKR) (41
7). In RAr)C (411), the first 4 bits are set to I(I-RADC (411a)) and the lower 4 bits are set to LO-RADC (41lb).The set value is 264.0= As 10 (A in hexadecimal) x 256 + 80 (4.F in hexadecimal), the bank register (417) has “A H” and RADC (4.
111) becomes “4FH”. This state is shown in FIG. Note that these numerical values are set when the data bus (tlBUs) is input when each load (Lr)...) signal is input.
o to 7).

The above CADR (418) and BNCR (417) latch the set values and use the column address counter (CA
DC) (410) and bank counter (BNKC) (4
09) to output each set value. On the other hand, R.A.D.
When the set value of C(4,11) counts down once, it performs a full count operation from the next time.

For example, when a print command (see Figure 5) is issued, a memory read request signal (MMRQ) is output, and the CA
The DC (410) counts down each time the signal (MMRQ) is input, and when it reaches “0” it outputs the RC (ripple carry) signal, which causes the CADR (4
18) is loaded. Signal (MM
CADC (410
) count value is the multiplexer (MPX) (405)
is selectively output as the Co1u+on address of the memory.

The RC signal of the CADC (410) is input as the clock input of the RADC (411), and the RADC (411) counts down each time it is input, and when it reaches "0", the RC signal is input as the clock input of the RADC (411).
It outputs an RC signal similarly to the ADC (410). R.A.D.
C (411) initially has 4. F H
" is set, and the countdown starts from this value, and after reaching "0", an RC signal is output every time a full count of 8 bits (256 = FFH) is made. 80) is the bank number “AH
”.The count value of RADC (411), like CADC (410), is the fraction of multiplexer (
MPX) (405) selectively selects the memory Row
Output as an address.

BNKC (409) uses the RC signal of RADC (411) as a clock input to count down, and the count value is output as bank specification data via the bank selector. When BNKC (409) becomes "0", memory access is started. The operation ends.

Each counter (409
) to (411) and the scanning operation of the B/M memory (corresponding to the scanning of the photoreceptor surface by the laser beam during image formation) are shown in FIG.

In the figure, each time the RADC (411') outputs an address, the CADC (410) counts down from "FEH" to "OOH" and specifies a Column address, which becomes the scan direction. Also, BNKC
(409) for each bank specified output by RADC (
411) is “4FH” but “0011” and “FEH”
Counting down from “00I” to “OO”
The bank is switched each time the signal goes high.

As a result, overall dot output of "FEH" x 8 dots in the horizontal direction and iox "FFH" x "4FH" in the vertical direction can be recorded on the recording paper in the feeding direction as shown.

Next, in FIG. 12(B), the operation of accessing the memory shown in FIG. 11 in correspondence with the paper size of 11 inches x 8.5 inches (indicated by the arrow "■" in FIG. 11. This will be described below) (This is called a long scan.)

Short scan and long scan are switched by the signal (LSCAN) as described above, but the physical configuration of 87M memory (bank arrangement and Rou
(Access in 8-bit units in the + direction) cannot be changed, so in order to access the memory by scanning as shown in "■" in Figure 11 during long scan, the operation mode of the counter described above must be changed and the address signal must be taken out.

Therefore, during a long scan, as shown in FIG. 12 (+1), the HI-CADC (41,0)
10a) and the upper 1 bit of LO-CADC (41011) constitute a 5-bit counter (4, 10c), and the RC signal is used as the clock input of BNKC (409).
Furthermore, the RC signal of BNKC (409) is
1) as the clock input, and T? of RADC (411). C
Connect the signals sequentially to the clock input of the counter (410d) consisting of the lower 3 bits of the LO-CADC (410b), and connect the count values of the 5-bit counter (410c) and 3-bit counter (41 ('ld)) in parallel. The value of RADC (411) is taken out via MPX (405) with Rou+address.

When performing a long scan, assuming the paper size is 11 inches (horizontal direction) x 8.5 inches (vertical direction), the number of dots is 2640 dots x 204. They are 12 bits and 11 bits respectively as binary counters.
It can be expressed in bits. Since access in the ROL11 direction is performed in 8-bit units as described above, the Rou+address counter can be reduced by 3 bits to 9 bits.

Of these 9 bits, in FIG. 12(B), the lower 5 bits are set to the first 5 bits of CADR (4, 18), and the upper 4 bits are set to BNKR (417). On the other hand, of the 11 bits in the Column direction, the lower 8 bits are set to RADC (HI + LO) (411), and the upper 3 bits are set to the lower 3 bits of CADR (418). The set value is BNKR="AH",
CADR-“4FH”, R, ADC; “F7H”.

In this state, when the access request signal (MMRQ) is issued as in the case of the short scan described above, first the 5-bit counter (4, 10c) is set (01
．． When subtracting from the full set (11111), Hiiragi outputs the RC signal to BNKC (409), and the 5-bit counter (410c) continues subtracting from the full set (11111), and when BNKC (409) becomes 60'', When the RC signal has passed, the RC signal is passed through a 5-bit counter (410c).
), the upper 5 bits of CADR (418) in ``1'' are reloaded and the above operation is repeated. At this time, RADC (411) is set to the initial setting value “F7”.
H'' and the 3-bit counter (410d) is 111''
Therefore, the 5-bit counter (410c) repeats subtraction, and BNKC (409) becomes 0 from "AH"? 'The operation corresponds to the operation of scanning the line of RoI11 address "F7H" once in the fItJ16 diagram. Access in the ROtU direction is performed in units of 8 bits as described above, and this makes it possible to obtain a data output that is apparently equivalent to scanning one line of the D-RAM in the "■" direction.

The RC signal of BNKC (409) is clocked into RADC (411), thereby subtracting "1" from the ROI address. When RADC (4, 11) is subtracted and an RC signal is output, the 3 pin counter (4, 10d
) is subtracted and becomes "111" → "110", the scanning of the set of output "111" of the 3-bit counter (4, 10d) is completed, and the scanning of the next set of "110" begins. 16th As is clear from the figure, the 3-pint counter (410cl) during long scan functions like BNKC during short scan.

When the output of the 3-bit counter (410d) becomes “110°”, the RADC (/1.11) outputs the full set “
FFH", and after that, the same counting operation is performed and 3
The access ends when the bit counter (4, 1, 0cl) becomes "0". FIG. 16 shows the relationship between this scanning operation and the paper feeding direction.

As described above, when executing this long scan, the CADC (410) that counts access requests (M M RQ) during the show)
Divide the bit and the lower y into, for example, 3 bits and create a 1 bit 1 counter (410c) and a 2 bit 1 counter (4
10d), input the access request signal (MMRQ) and the RC signal of RADC (/1.i4) as clock signals, and connect the outputs of both counters in parallel 8 (yl+father,
) is extracted as a bit output and set as R, our address, while the R of the bit counter (410c)
The C-3 is the Talon Kui word of BNKC (4,09), and the RC signal of BNKC (4,09) is the RADC (4,1).
1, ), and the RC signal of BNKC (409)
The configuration is such that the initial value is loaded into the focus counter (410c), the output of BNKC (409) is used as bank select data, and the output of RADC (4, 11) is used as Co! umn
Address.

In this case, the number of bits of each counter can be changed as appropriate depending on the specific memory capacity, matrix configuration (N bits x M bytes), number of banks (K), etc. Also, the signal (LS
A person skilled in the art can easily think of a specific mechanism and method for switching the relationship between the counter and clock signal during a short scan to the relationship between the counter and clock signal during a long scan using the CAM). Although illustrations and explanations thereof will be omitted since they are not directly related to the gist of the present invention, for example, switching of input light for clock signals and load signals can be achieved by using appropriate date and selector circuits. The division of the counter can be accomplished by taking the output of the desired bit position of the binary counter.

Furthermore, the data in the 87M RAM (201) during long scanning does not correspond to the physical dot positions on the image actually output by a laser printer, etc.
This means that when writing data, the memory addresses that are processed in 8-bit parallel processing are distributed as appropriate.
As described above, data can be read out in the scanning direction shown by "■" in FIG. 7 apparently.

When writing data to an 87M memory, in particular, in the 7-ont = 35-bit method that corresponds to a specified character food, even if there was a request to track the write position, it could only be processed in bytes.

Therefore, in the present invention, a bitmap method is adopted and seven on-tone controls as shown in FIG. 8 can be performed, thereby providing flexibility as a character signal generating device.

FIG. 10 shows details of the 7-onto controller (301). In the figure, a signal that enables writing to the register (TAZTO) and a write signal to the register (MYWR) are shown.
) for generating a signal (TWπ), data for selecting one of a plurality of registers (TADO~
3) and a signal for enabling readout from the register (ding) is input from the 87M CPU section (1'02) to the decoder (501) of the 7 ont controller (301), and the decoder generates a signal as shown.

When writing 7-ont data, first, the first data (FAD) of the 7-ont address in the selected 7-ont column,
Font width data (WIDE), 7-ont height data (
HIT) and registers (FONTAD, R) and (
Load signal (LDFAD) to set to WI DTH, R), (HIGHT, R), (LDWIDER)
, (LDHITC) are output. The data loaded into each of these registers is sent from the B/MCPU section (102) and the 7-ont memory section (109) to the data bus and transmitted via the buffer (502). In addition, 7
Onto Address Registration (FONTADR) is in the top 8
Bit FONTAD(H)R and lower 8 bits FONT
It is divided into AD(L) and R.

After setting the 7-ont data to the register (counter) of the 7-ont controller (301), the data at the start address of the write position of the 87M memory is input to the B/M controller (302) described above as BNKR (
417), CADR (418), and RADC (411) to generate a character after write command, a write request signal (FMRQ) is output, and the clock signal output from the timing generator (503) is used. 7 ont data is written into the 87M memory (201) while each counter (renostar) is operated to perform a subtraction operation. The address signal when writing data to the 87M memory (201) is generated by the almost same counter operation as when reading the data mentioned above, and switching between short scan and long scan is performed as necessary. However, in character write mode, pIf
At the end of scanning the J1 line (J+Yarakuta pattern width bytes), a signal (FLAST) is output from the 7-ont controller (301), thereby moving to the next line of data.

On the other hand, the command register (CMDR) (504) has the following information:
Data (SFTO~2) for shifting the character data to be written into the 87M memory bit by bit is set in accordance with the shift presentation, and the signal is input to the timing generator (503). 503), two 8-bit shift registers (S
The write data is shifted by controlling the operations of R1) and (SR2).

Note that 8-bit data from the 7-ont memory is written into the shift register (SR1) via the data bus, and 8-bit parallel data for writing is output from the shift register (SR2). Next, a procedure for writing this character data to an arbitrary position on the 87M memory (201) will be explained. First, to simplify the explanation, 2-byte data as shown in FIG. 17 is extracted from the 7-ont memory, and
7. The operation of writing with the Col old IIn address=733 as the starting address will be described as an example.

First, the above-mentioned BN is
KR, RADC, CAI) The data to be sent to R is calculated. That is, (maximum R address) - (setting ROLI + address) =
2639-2537 =102-39= Therefore, if we express this in binary, it is (000001
100111), the upper 4 bits (=00■]) are set to BNKR, and the lower 8 bits (=678) are set to RADC. On the other hand, (maximum Co1u+on address) - (setting Column address) = 2039-7
33” 1306, so if we express this in binary numbers (110000
11010), and the upper 8 bits (=C3H) are CA
Set to DR and use the lower 3 bits as basic data of SFT. Here, since the maximum value of the shift control amount is "7", the shift data in this case is 7-2=5, 5
FT=5 is set simultaneously with the character write command when setting the command register (504).

When a command is executed in this state, ■(a) in Figure 18
), the shift register (SR2) is first cleared, and the first byte of 7-ont data is loaded into the shift register (SRI). Next, ■According to the seat clock from the timing generator (503), the SFT
The data is shifted from (SR1) to (S R2) by (5=3), and as shown in FIG.
The data of R2) is written into the 13/M memory. The addresses outside this are BNKC=OOH, CADC=C3
H, RADC=67H.

Next, the data is shifted to the left by 5FT=5 according to the shift clock from the timing generator, and after the shift operation is completed, the second byte of the 7 ont data is transferred to the shift register (S
R1). This state is shown in FIG. 18(C). From this state, further shift operation is performed by ■5FT (5=3) (Fig. 18(d)), and (S R2)
Write the book review data into 87M memory. The addresses outside this are BNKC=00H, CADC=C2H, RADC
=67H.

Furthermore, the data is shifted by (SFT=5)+(SFT=3)=8 (bits) and written into the 87M memory as the state shown in FIG. 18(e). The address at this time is BNKC=00H
, CADR=CIH, RADC=678, and ■～■
With this operation, 2 bytes of data in 7 ont memory are transferred to CA.
D C= 3-by-F shown by C3H ~ CI I-T
Inside i is written.

In actual operation, vertical (Co l u (BB force direction) X bits, horizontal (Rou + direction) Y bytes are transferred, but in this case, the value of (XtY) is the directory (D 1 directory) area (described later), and before the transfer process, the B/
This (
XIY) and 7ont controller (301)
Register (HTGT(
T, R) and (WTDTHoR), respectively. For example, when 7 characters are composed of 32×24 dots, X=32° and Y=3, and the movements of the respective registers (counters) are as shown in FIG. That is, during the write operation of the first line (WIDTH
oR) changes from "3" to "0" and data (Y = 3) is reloaded every time one line is written. Also CA
DC (410) is, for example, from “CC)-1” to “CC
H-4'' and the data (C
CH) is reloaded. On the other hand, (HI GHT, R
) and (BNKC+RA]') C: Data B RRH) are added to "1" every time one line is written, and (WIDTH, R) = O, CADC = "CCH-4"
.

(HIGHT, R)=0. (BNKC1RADC)=“
The command operation ends when it reaches "BRR-32".

Therefore, in this case, the shift operation shown in FIG.
After repeating the number of bytes (number of written bytes = 4), a signal (FEO
L), the process moves to the next line.

In this way, in the 7ont controller (301,), the command register (504,), timing generator (503), shift register (S R1), (S R2)
), and after loading 7 onts of 8-bit data into the shift register (S (n is an integer from 1 to 7), the data from the timing generator (503) is shifted by 1, and the shifted data is transferred to the 87M memory. The first process of reading from (SI'?, 2) as write data to b, the numerical value 7i (π = 8n), further shifts the data, and writes the next 8-bit data of 7 ont to (SR1). The second process of taking in the data is repeatedly executed in accordance with the number of bytes of data transferred from the 7 ont. (The loading of data into SRI before the final read from SR2 is omitted.) As a result, the command register (5
Character data can be written in any position according to the data set in 04).

7 on) Reading data from memory (109)
The data structure of the 7-on-1 memory will be explained next, although it is performed in two consecutive steps.

The 7-ont memory basically stores a binary image signal showing the character shape in a dot matrix, and the character data corresponding to the character hood is transferred from the host CPU, etc. Dots = 44 - The characters are read out in the order of the lines (Rou+ direction) of the matrix, and finally the characters expressed by dots are printed out.

In the conventional 7-ont memory, characters are arranged in 4 vertical formats, for example.
If the design is such that it fits within a matrix of 0 dots and 24 dots horizontally, 40 bits x 3 by F is applied to all characters regardless of their size and shape.
There was a lot of waste because the memory capacity of
The usage efficiency was poor.

Therefore, in the 7-ont memory used in the image signal generation device (100) of the present invention, the dot portion representing the actual character shape is divided by a minimum dot matrix (in byte units in the horizontal direction) surrounding the dot portion, and is stored. I made it. This increases the efficiency of using the 7-ont memory, but since the number of bytes required differs depending on the character, the 7-ont memory (109-A to 109-1-N) has a different file structure than the conventional one, as shown below. ing.

FIG. 20 schematically and comprehensively shows the file structure of the 7-on memory. In 7-ont memory, data is read in single bytes,
Four addresses are given in byte units. Address “0”
0■1”～”Fl(” is G 1 oval I nf
normal, ion section (general information section) (601). Information regarding the overall characteristics of this 7-ont is written here. Specifically, as shown in FIG. 21, the address “00I]” contains the code assigned to the font-2 stored in the 7t7) memory and “
Write the code (20) indicating "EmptyRAM". The 8 bits of address "011-(" are used as switch bits indicating the selection of variable setting items as shown in the figure. Addresses "02I]" to "07I4" are , 7 The abbreviation of the ont name is expressed as a 6-byte code.Address “
08I]" writes data indicating the maximum character size in this 7 ont. Address "091-r"
Write data indicating the number of dots in the width and height of the character to "A I-1" and "A I-1", respectively, and write data to the address "B
"Write data indicating the number of dots at the height of the baseline.

Data indicating the sequence ID of the character code, that is, the revision number of the character code, is written into the address "C11". Addresses “EII” and “F I-1” have
7) Write data indicating the total number of bytes of the file.

In FIG. 20, the address “10■” of the 7-ont memory
]'' ~ “3 F F H” is Characters D
1 directory section (602). Here, for each character, 8-byte data is used to write the 7-ont configuration and information serving as an index of actual bit data. The arrangement order is basically the character code order defined by ASCII (ASCII), but some characters are also included that are not defined by the ASCII code. This CI+aractorsD 1r
Specifically, as shown in FIG. 22 (,), the directory section is configured to set each of the Font D 1rectories for all characters indicated by the hoods "02H" to "FFH" (values smaller than these depending on the number of characters). For writing data, each F ont, D 1r
The directory has a data structure as shown in FIG. 22(b). To explain this with reference to the specific example of the character dot pattern "j" in FIG.
# O) is the number of vertical dots in the character's dot pattern, Pi) No, C# 1) is the number of horizontal bytes required for the character's dot pattern, byte NO, ($ 2)
), (# 3 ) is data indicating the start address in the 7-ont memory where this 7-ont bit pattern is written, pi) No., (ff 4 ) is the actual width of the character pattern (number of dots), pi) No, C#
5) indicates the number of dots from the baseline (BL) to the top line of the character pattern (P), and (#6) indicates the number of dots from the left end of the character pattern to the character pattern center position (P).
In the number of dots up to c), byte number ($7), write the number of dots from the baseline (BL) to the bottom line of the character pattern corresponding to the dot pattern of each character. The above baseline (BL) data is the second
G Ioval Informatio shown in Figure 1
The line address is set by the baseline height data of the address (BH) for the character height data of the address (AH) of the n part (601). Also,
The center (Pc) position of the character pattern is the baseline (BL) character size width data (
The dot position can be determined as 1/2 of #4).

At this time, if the width data of (#4) is an even number, the right one of the two central bits is set as the center position. Furthermore, in FIG. 20, the address "4" of the 7-ont memory is
After 00H'', the character bit data section (603)
Define as . Character bit data section (603)
As mentioned above, the number of memory bytes used varies depending on the dot pattern of the character, so the length is variable. Specifically, as shown in FIG. 23(a), bit data of each character is continuously written in byte units into the character bit data section (603). As long as each bit data is consecutive for each character, the start address of each character is (#2) and (#3) in FIG. 22(b).
Since bit data is read out based on this data at the time of access, there is no need to specify the order in which the characters are arranged.

A specific example of writing bit data is shown in FIG. 23 (11). This is taken as an example of the character pattern rAJ schematically shown in FIG. 23(c). The character rAJ is horizontal 2
0 dot 1. If it is expressed as a matrix of 20 dots in the vertical direction, 3 bytes are allocated in the horizontal direction, and the above D
1 directory part (602) (well 0) + this data data "20" is written (well 1) (this data data "3" is written, and the bit data of FIG. 23 (11) The array is written in the order of the first byte, the second byte, and the third byte for each Ro, starting from RoII+ at the upper end.

Using the example of "j" in Figure 24, the first
The bit data of the byte (ooonoooo) and the bit data of the second byte (01111100) are written in this order.

A 7-on IRoM (1°9-A
-109-11), G 1 oval I n
The formanion section (601) is read when the power is turned on to the printer (1) or when replacing the font cartridge, and is data for transmitting the type of installed font cartridge to the host CPU (2). used as. In other words, when the power is turned on or when the font cartridge 7
When replacing B/M CP [, 1 part (102), 8
The 7 MCPU outputs the 7 ont select data, sets it in the 7 ont select launch (FONTSL) (see Figure 10), and also outputs the 7 ont select data (FONTSL) (see Figure 10), and also outputs the counter (FONT A D (H), R,F
ONTAI) (L) and R) respectively. Next, B/MCPtJ writes B/M control section (103
), set the "7 on 1 read" command in the command register (CMDR) of the 7 on 1 memory, and start accessing the 7 on 1 memory from the address "'OOH".
Shift 8 bits 1 data read from ont memory)・
It is latched into a register, and the 87MCPU reads out the contents of the latch while incrementing the address.
Read the data of FH″ G 1 oval I nfo
rmation section (601) ends.

On the other hand, when reading the bit pattern of a character from the 7-ont memory and transferring it to the B/M memory according to the character code, the C
Haracters Directory Department (602
) data is used. That is, D1retory
Of the 8 bytes (see Figures 22 to 24), the information of Pi) No. (#O) to (#3) is the bit data of the bit data part (603) in the 7-on F memory. /
When writing to the M memory (201), the predetermined bit data is the data for reading from the 7-ont cartridge. This data is used by the 87 MCPU to calculate the location (address) when inputting the data into 201). Specifically, based on data such as height (number of dots relative to the baseline), number of dots from the baseline to the bottom line, character size width (number of dots), and number of dots from the left edge of the character pattern to the center (PC), etc. , the 87MCPU calculates the writing start address that matches the relationship with the bit pattern of the previously written character and the printing conditions such as whether the printing is proportional or monospaced, and the 87MCPU calculates the writing start address that matches the printing conditions such as the relationship with the bit pattern of the previously written character ) is used to set the address of the B/M controller (302); Mesta and counter (BNKR).

CADR, RADC). Also, the data of byte No. (#(1)) is (HIGHT
, R), the data of (#1) is (W T D T H, R
)i (I2), NF2) data FONTAD (H
), R).

(The FONTAD (L) and R are respectively set.

In this way, for a given character code, the first
The 7-ont controller (301,) in Figure 0 refers to the Directory of the corresponding character in the 7-ont memory and reads bit data from the start address of the read)
Read in units. At this time, the preset counter (505) is decremented every time one byte is read, and (FONT
AD, R,) increments and advances the address to "1", and the preset counter (505) outputs an RC signal (reading of one line of character pattern is completed) to the B/M controller (301). is a new line (Rou + address increment)
At the same time, (II I GHT, R) is subtracted to "1". Repeat this (I (I G
When the bit pattern of the character (HT, R) becomes "0", reading of the bit pattern of that character is completed. ), the transferred bit data is written to the B/M memo 1j (201) while specifying the address by operating a counter at the timing of the write synchronization clock.

At this time, the writing mode can also be executed in the two modes of short scan and long scan mentioned above, and the counter configuration etc. at that time is substantially shown in FIGS. 12(a) and (+1). It is the same as the one above.

As explained above, according to the present invention, for example, the same paper having the minimum necessary capacity corresponding to the printing surface of the paper can be used in both the vertical and horizontal positions of the paper to be printed. The printing operation can be executed using the image memory of 200 MHz, and the capacity of the memory can be reduced without impairing the high speed of access, which is an extremely advantageous feature when using a relatively expensive bitmap memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the system configuration of a printer to which the present invention is applied. FIG. 2 is a block diagram of a control system including the image signal processing device. 3 to 6 are 70-charts showing the signal processing procedure executed in this control system. FIG. 7 is a block diagram schematically showing the configuration of the bitmap RAM section. FIG. 48 is a block diagram schematically showing the configuration of the bitmap controller and the relationship between signal transmission and reception. FIG. 9 is a block circuit diagram showing the configuration of the bitmap controller. Figure vJ10 is a block circuit diagram showing the configuration of a 7-on-1 controller. FIG. 11 is a diagram showing the relative relationship between the matrix structure of the bitmap memory and printing paper. FIGS. 12(a) and 12(b) are diagrams showing a circuit for generating addresses for accessing the bitmap memory in two types of modes using the circuit of FIG. 9. FIG. 13 is a chart showing specific examples of numerical values set in each register in the operation mode shown in FIG. 12(,). FIG. 14 is a diagram showing the relationship between the movement of each counter and printing operation in the operation mode of FIG. 12(a). FIG. 15 is a chart showing specific examples of numerical values set in each register in the operation mode shown in FIG. 12 (1). FIG. 16 is a diagram showing the relationship between the movement of each counter and printing operation in the operation mode of FIG. 12(b). 17 shows the format of the data output from the 7-ont memory in order to explain the operation of the circuit shown in FIG. 10. FIG. 18(a) to (e) show the 7-ont data shown in FIG. 10 is a diagram sequentially showing the states of data in a shift register to show that the data is shifted and written into a bitmap memory using the circuit shown in FIG. 10. FIG. FIG. 19 is a chart showing the relationship between the operations of each register and counter in the circuit of FIG. 10, etc. FIG. 20 is a diagram generally showing the file structure of the 7-ont memory. Figure 21 shows C; Ioval Info
It is a figure specifically showing the contents of an r+nation part. 23(a) and 23(b) specifically show the contents of the character bit data section, and FIG. 23(c) is a diagram showing an example for explaining the contents. FIG. 24 is a diagram showing a relationship between a specific example of a character dot pattern and the contents of a 7-ont memory. 103...Bitmap control section 104...
Bitmap memory section 109... 7-on-1 memory section 201... Bitmap memory (RAM) 301...
7 Onto controller 302... Bit map controller 409... Bank counter (BNKC) 410... Column address counter (CADC) 411... Row address counter (RADC) 417... Bank register (BNKR)
)418...Column address register (CADR) 4
10c...5 pin counter 410d...3 bit counter 503...timing signal generator 504...command register SR1, SR2...shift register 601-7 *Int memory G 1 oval I nf
orLIlation section 1302 ・7ont memory C
F+aracters @ 1retory section 603
...7 Onto memory character bit data section FONTAD
(H, L) R...7 Onto Address Reno Star LSCAM...Short scan/long scan switching signal -O -, ノ 'N, ノ (-Q ＼) ゝ-'
-Fig. 22(d) "" ASCII Code θ2〃
Off picture 7/'onlDI, ettorl''
”01 byte)
” A4F2 ・ Cod31'/＼ Non-3 θO18 葎4 Font DnorectDry/
, 5 (8 bytes) A6 Figure 22 (b)

Claims (1)

[Claims] 1. A circuit for outputting an address signal when accessing an image memory of N bits x M bytes (number of banks = K), which performs a counting operation based on an access timing clock, and performs an M count. A column address counter that outputs a signal every time and performs a counting operation repeatedly, and a row address counter that performs a counting operation based on the output of the column address counter and outputs a signal every time the count value reaches the number of rows in the bank. and a bank counter that performs a counting operation based on the output of the row address counter.
The upper l_1-bit counter is operated by the access timing clock, and the bank counter is operated by a signal output every predetermined number of counts of the upper l_1-bit counter. The row address counter is operated by a signal output at each count, and the lower l_2 bit counter is operated by a signal output every time the row address counter reaches the number of rows in the bank. It is characterized by having an image memory access mode in which the count operation signal is switched, the count contents of the upper l_1 bit counter and the lower l_2 bit counter are extracted as (l_1+l_2) bit data, and this is used as a column address signal. Image signal processing device.