JPS61112409A - Power amplifier - Google Patents

Abstract

PURPOSE:To simplify the constitution by arranging a control system of a power supply circuit of an SEPP amplifier with one system activated by a larger signal in both input channels. CONSTITUTION:When right/left channel stereo signals are inputted from terminals 31R, 31L, one of the signals is inputted to drive circuits 34R, 34L of the SEPP amplifiers 32R, 32L, the other is inputted to a maximum value detection circuit 44 via absolute value circuits 33R, 33L, and a signal having larger absolute value in both the channel signals is outputted to a voltage comparator 42. One of the outputs of the voltage comparator 42 is inputted directly to a switching element 40R and the other is inputted to each gate of a switching element 40L via a phase inverter 43, and when a difference of the power supply voltage of the SEPP amplifiers 32R, 32L and the output of a maximum value detecting circuit 44 exceeds a prescribed value, the circuit 42 conducts the switching elements 40R, 40L to control the power supply voltage. Thus, the control system of the power supply is unified to simplify the constitution in this way.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an improvement in a power amplifier suitable for an audio amplifier.

[Technical background of the invention and its problems]

The applicant has previously developed a high-efficiency B with the configuration shown in Figure 92.
An application has been filed for a class stereo 3rd BPF power amplifier and it has already been published (Japanese Patent Laid-Open No. 57-212809).

That is, one end of each of the switching elements α3a) and (13b) is connected to DC power supplies (12a) and (I2b) having different polarities, and the other ends of each of the switching elements α7a) and (13b) are connected to the DC power supplies (12a) and (I2b) with different polarities.
SEPP amplifiers (24FL) and (2
The positive and negative power input terminals of 4I, ) are commonly connected. The signal input terminals of these 8EPF amplifiers are connected to input terminals (LIR) and (IIL) Ic, and the output terminals are connected to loads @TL) and (21L). or,
Among the input signal voltages applied to the input terminals (IIR) and (IIL), the DC power supply (12a),
Detection circuit G1 that detects a voltage closer to the voltage of 02b)
2A) and (22b ”) are connected, and furthermore, these detection circuits are connected to the output voltage of these detection circuits and the smoothing circuit α7.
The feedback voltage proportional to the output voltage of a) and α7b) is compared, and when the difference between the two exceeds a certain value, the switching element (13
It has a configuration in which voltage comparators (23a) and G23b) are connected, which respectively turn on a) and α3b).

In addition, the smoothing circuit (17a), α7b) Vi consists of choke coils (15a), (15b), and smoothing capacitors Q6a), α6b), respectively.
The SEPP amplifiers (H) and (H) are each drive circuit (2) R.
), (Z')L) and bias circuit m), C26
L) and transistors (20Ra), (20Rh
), (20La), (20Lb).

According to the class B stereo 8EPP power amplifier having the above configuration, a highly efficient amplifier with low power loss can be obtained.

However, two voltage comparators and two detection circuits are required, and the configuration is a little complicated.
It cannot be configured as a monaural power amplifier using L connections.

[Purpose of the invention]

The present invention has been made in view of the above aK, and an object of the present invention is to provide a class B stereo SEPP power amplifier with a simple configuration and high efficiency. Furthermore, another object of the present invention is to provide a highly efficient power amplifier regardless of whether the input signal is stereo or monaural. The detection circuit and the voltage comparator have only one path, and the other switching element is controlled by a signal obtained by inverting the output of the voltage comparator.

The second invention is based on the first invention, and when listening to a monaural signal, the phase of the signal input to one input terminal is inverted and used as the other signal.0 [Effects of the Invention] According to the present invention , one detection circuit, and one voltage comparator each, which simplifies the configuration. Further, according to the second aspect of the invention, a power amplifier for stereo/monaural use can be obtained which reduces power loss even during monaural listening.

[Embodiments of the invention]

Examples of the present invention will be described below.

Figure 1 shows the present invention as a class B stereo SEP with two positive and negative power supply systems.
The configuration of an embodiment applied to a P power amplifier is shown. C(I
R) and (31L) are input terminals into which stereo signals of both left and right channels are input, and the signals input from these terminals are each sent to a SEPP amplifier (3Za).

(3ZL) signal input terminal and absolute value circuit (33R)
, (33L).

SEPP amplifier (32R), (32L> is a drive circuit (34R) that amplifies the input signal to the signal input terminal.
), C,34L) and an NPN transistor (3
5Ra), (35L a) and a PNPN upper type resistor (35Rb), (35L b'').
The collector terminals of (35La) are commonly connected to the output terminal of the smoothing circuit (36R) as the positive power input terminal of the 5PPP amplifier (32B>, (321,), and similarly, the trunk Xta (35Rb), (35Lb). ) are commonly connected to the SEPP amplifier (32R), (
A smoothing circuit (36L) is used as the negative power input terminal of the
') is connected to the output end of the

Smoothing circuits (36L) and (36L) are respectively
Kucoil (37R).

(37L) and capacitor (38R), (3RL)
It consists of

On the other hand, the negative and positive electrodes of the DC power supplies (39R) and (39L) are grounded, and each positive and negative electrode is connected to the switching element (
For example, field effect transistor) (40R), (
40L) is grounded at one end, and the other end is a flywheel diode (41R), cathode and anode of (41L'), and a smoothing circuit (36B), (36L) to prevent adverse effects from the chiccoil on the switching elements. )
input end (i.e. check coil (37R'), C3
The switching elements (4OR) and (40L) connected to one end of (n) are controlled by the output of the voltage comparator (6) and a signal obtained by inverting this output signal by a phase inverter (c). be done.

The voltage comparator (6) is the absolute value circuit (31ER),
Compare the output voltage of the maximum value detection circuit (44) that outputs the larger voltage of the two power signal voltages of the C33L) and the feedback voltage proportional to the output voltage of the smoothing circuit (36R), and the difference between the two is constant. When the value exceeds the switching element C8
%) conductivity. The feedback voltage is obtained as the voltage at the connection point of the feedback resistors (45a) and (45b) connected in series between the output terminal of the smoothing circuit (36R) and the ground.

For the maximum value detection circuit I, for example, as shown in Fig. 3, the cathodes of two diodes (46R) and (46L) are commonly connected to form the output terminal, and this connection point is connected to the negative power supply ( -Vcc) can be used. Further, as the voltage comparator n3, for example, a circuit shown in FIG. 4 is used. That is, 61) is a terminal connected to the output terminal of the maximum value detection circuit (44), and 6a is a feedback resistor (
45a) and (45b) to which the feedback voltage Vf is applied. Eel is a bias adder that adds an appropriate DC bias as necessary to the voltage Va to the terminal 51), (B) is an inverting amplifier that inverts the input signal voltage Va, and (G) is an inverting amplifier (B). This is a summing amplifier that adds the output voltage and the feedback voltage Vf to the terminal 5. Also, @6
.eta. is a diode which becomes conductive when the output voltage of the summing amplifier exceeds the range of .+-..DELTA.V, inverting the potential at the output terminal and providing hysteresis characteristics. In addition, the summing amplifier (
The part consisting of the diode (5e, 67) may be replaced by a Schmitt trigger circuit or a window comparator consisting of two sets of comparators.

Next, the operation of the embodiment shown in FIG. 1 will be explained. Now, in Fig. 5(a), the curves (61R) and (61L)
Suppose that the stereo signals of the right and left channels as shown in the figure are input to the input terminals (31R) and (31L). At this time, the outputs of the absolute value circuits (33R) and (33L) have the waveforms shown in the curves (62 and (62L)) in FIG. 5(b), and the outputs of the maximum value detection circuits have the waveforms shown in FIG. C) dotted line (6
3), the output of the phase inverter (c) is shown by the dotted line (64
).

The terminal voltage of the loads (Ll) and (L2) (transistor emitter connection point voltage) is the solid line (65R) in Figure 5 CC).
), (65L), the trunk X is almost the same as the input signal voltage (35Ra), (35L1a).
The collector voltage of the transistors (3sRb), (35IJ)) changes similarly to the dotted line (63), and the collector voltage of the transistors (3sRb) and (35IJ) change similarly to the dotted line (64), so power loss can be reduced.

Next, an embodiment in which the present invention is applied to a stereo and monaural power amplifier will be described. FIG. 6 shows the configuration of this embodiment. As is clear from the figure, the first
The configuration shown in the figure is two VC switch circuits (71a) and (71b).
) and a second phase inverter (72) are added. In Fig. 6, the same parts as in Fig. 1 are indicated with the same numbers. For stereo playback, the switch circuit (
71a) and (71b) are terminals (733) and (74g), respectively.
) is connected to the output terminal, and has exactly the same configuration as in FIG. 1, and operates in the same manner. Also, during monaural playback, the switch circuits (71a) and (71b) are connected to terminals (73M),
(74M) is connected to the output terminal, and the input terminal (31M) is connected to the output terminal.
The input signal to R) is input to the signal input terminal of S]3PP amplifier (3za), and this input signal is inverted through a phase inverter (72) and applied to the signal input terminal of SEPP amplifier (3ZL). During monaural playback, the load (Ll),
(L2), one load (L3) is placed between both output terminals.
) is connected, but 8EPP amplifier (32R),
Signals with completely opposite phases enter the signal input terminals of (32I,), so SEPP amplifiers (32R) and (3ZL)
For example, voltages as shown by solid lines (75R) and (75L)K in FIG. 7 appear at the output end of the load (L3), that is, at both ends of the load (L3). On the other hand, 8EPP amplifier (32R).

(32L) old power supply end, that is, NPN type transistor (
A voltage as shown by the dotted line (76a) in FIG.
type transistor (35Rb).

A voltage as shown by the dotted line (76b) in FIG. 7 appears at the collector end of (35Lb), so that the power loss can be reduced.

Unfortunately, the present invention has a great effect of high efficiency when applied to a special KB class SEPP power multiplier.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of a conventional power increase device, and FIG. 3 is a diagram showing an example of a maximum value detection circuit in the embodiment of FIG. FIG. 4 is a diagram showing an example of the circuit of the voltage comparator in the embodiment of FIG. 1, and FIG.
6 is a diagram for explaining the operation of the embodiment of the present invention, FIG. 6 is a configuration diagram of another embodiment of the present invention, and FIG. 7 is a diagram for explaining the operation of the embodiment of the present invention shown in FIG. It is. 31R, 31L...input terminal, 3rd, 32L...
8EPP amplifier, 338.33L...absolute value circuit, 3
48μL...Drive circuit, 35Ra, 35I, i.
...NPN transistor, 35Rb, 35Lb...
PNP type transistor, 36R, 36L...smoothing circuit, crayon...chip coil, 38B, 38L...
Capacitor, 39 liters, 3%...DC power supply, 40R, 4
0L... switching element, 42... voltage comparator,
Core, 72... Phase inverter, 躬... Maximum value detection circuit, 71a, 71b... Switch circuit, Ia, Lz, L
ST...Load (speaker). Figure 1 Figure 2 @ 4 Figure A9 Figure 5 Figure 6 5Lb Figure 7

Claims (2)

[Claims] (1) First and second DC power supplies with different polarities, first and second switching elements whose respective ends are connected to these first and second DC power supplies, and these first and second switching elements First and second smoothing circuits each having an input terminal connected to each other end of the element, and respective positive and negative power supply input terminals commonly connected to each output terminal of these first and second smoothing circuits. , each signal input terminal is connected to the first and second input terminals, and each output terminal is connected to the first and second input terminals.
first and second SEPP amplifiers connected to a second load; first and second absolute value circuits that obtain absolute value waveforms of respective signals input to the first and second input terminals; , a maximum value detection circuit that detects the larger of the output voltages of these absolute value circuits, and the output voltage of this maximum value detection circuit or the voltage obtained by adding a constant DC bias to the output voltage of this maximum value detection circuit and the voltage of the first smoothing circuit. Compare each with the feedback voltage proportional to the output voltage,
a voltage comparator that makes the first switching element conductive when the difference between the two exceeds a certain value; and a phase inverter that inverts the phase of the output signal of the voltage comparator and controls the second switching element to be conductive using this signal. A power amplifier comprising: (2) First and second DC power supplies with different polarities, first and second switching elements each having one end connected to these DC power supplies, and each input terminal connected to each other end of these switching elements. The connected first and second smoothing circuits, the respective positive and negative power input terminals are commonly connected to each output terminal of these smoothing circuits, and each output terminal is connected to the first and second loads. First,
a second SEPP amplifier; a first switch circuit that is selectively connected to the first input terminal or the second input terminal connected to the signal input terminal of the first SEPP amplifier and outputs one of the signals; a first phase inverter connected to the output end of the first switch circuit, and a signal of the second SEPP amplifier that selectively outputs the output of the phase inverter or the output of the first switch circuit; a second switch circuit input to the input terminal; a first switch circuit for obtaining the absolute value output of each of the signal input to the first input terminal and the output signal of the first switch circuit;
a second absolute value circuit; a maximum value detection circuit that detects the larger of the output voltages of these absolute value circuits; A voltage comparator that compares a feedback voltage proportional to the output voltage of the first smoothing circuit and makes the first switching element conductive when the difference between the two exceeds a certain value; A power amplifier comprising: a second phase inverter that controls conduction of two switching elements.