JPS611107A - Low-pass filter circuit - Google Patents
Low-pass filter circuitInfo
- Publication number
- JPS611107A JPS611107A JP59124094A JP12409484A JPS611107A JP S611107 A JPS611107 A JP S611107A JP 59124094 A JP59124094 A JP 59124094A JP 12409484 A JP12409484 A JP 12409484A JP S611107 A JPS611107 A JP S611107A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- low
- pass filter
- diode
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/04—Frequency selective two-port networks
- H03H11/12—Frequency selective two-port networks using amplifiers with feedback
Landscapes
- Networks Using Active Elements (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【発明の詳細な説明】
[発明の技術分野l
この発明は、たとえばP L L (Phase Lo
ckedLoop)回路を用いて選局回路をコントロー
ルするシステムに使用されるローパスフィルタ回路に関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention l This invention is applicable to, for example, P L L (Phase Lo
This invention relates to a low-pass filter circuit used in a system that controls a channel selection circuit using a ckedLoop) circuit.
[従来技術]
第3図はこのようなシステムの一般的な回路構成を示し
ている。図において、(1)は受信゛アンテナ、(2)
は高周波増幅器、(3)は局部発振器、(4)はローパ
スフィルタ回路、(5)は位相比較器、(6)はCPU
、(7)はプログラマブルデバイダ、(8)はプリスケ
ーラ、(9)はテレビ信号処理回路、(10)は受像管
、 (11)は基準周波数入力端子、(12)はパリキ
ャップである。[Prior Art] FIG. 3 shows a general circuit configuration of such a system. In the figure, (1) is the receiving antenna, (2)
is a high frequency amplifier, (3) is a local oscillator, (4) is a low-pass filter circuit, (5) is a phase comparator, and (6) is a CPU.
, (7) is a programmable divider, (8) is a prescaler, (9) is a television signal processing circuit, (10) is a picture tube, (11) is a reference frequency input terminal, and (12) is a Paris cap.
局部発振器(3)から発振された発振波は、まずプリス
ケーラ(8)で分周されて、プログラマブルデバイダ(
7)に入力される。プログラマブルデバイダ(7)はC
P U (8)が指定するデータによって分周比を変化
させ、その入力波を分周する。位相比較器(5)はプロ
グラマブルデバイダ(7)からの分周波と、基準周波数
入力端子(11)からの基準周波数との位相の比較を行
ない、その差分パルスをローパスフィルタ回路(4)に
入力する。ローパスフィルタ回路(4)の出力すなわち
チューニング電圧は局部発振器(3)のハリキャップ(
12)に加えられ1局部発振器(3)の発振周波数がC
P U (8)からのデータによって指定された値にな
るように制御される。The oscillation wave oscillated from the local oscillator (3) is first divided by the prescaler (8) and sent to the programmable divider (
7). Programmable divider (7) is C
The frequency division ratio is changed according to the data specified by P U (8), and the input wave is frequency-divided. The phase comparator (5) compares the phase of the frequency-divided wave from the programmable divider (7) and the reference frequency from the reference frequency input terminal (11), and inputs the difference pulse to the low-pass filter circuit (4). . The output of the low-pass filter circuit (4), that is, the tuning voltage, is the haricap (
12) and the oscillation frequency of 1 local oscillator (3) is C
It is controlled to a specified value by data from P U (8).
第2図は第3図の回路におけるローパスフィルタ回路(
4)の1例を示している。(13)および(14)はロ
ーパスフィルタを構成する抵抗およびコンデンサ、(1
5)はスイッチングが可能でかつ高入力インピーダンス
の位相反転増幅回路、(IC)は位相反転#a幅回路(
15)の入出力間に接続された帰還回路、(17)は負
荷抵抗、Eiは入力電圧、Eoは出力電圧である。Figure 2 shows the low-pass filter circuit (
An example of 4) is shown. (13) and (14) are the resistors and capacitors that constitute the low-pass filter, and (1
5) is a phase inversion amplifier circuit that can switch and has high input impedance, and (IC) is a phase inversion #a width circuit (
15) is a feedback circuit connected between the input and output, (17) is a load resistance, Ei is an input voltage, and Eo is an output voltage.
」1記構成において、出力電圧EOか第3図のCP U
(8)からダ4えられるデータによって、低い電圧か
ら高い電圧に切換わるときの応答は、はぼ帰還回路(1
B)の時定数によって決まる。この場合、応答を速くす
ると出力電圧のりプルが大きくなり、受信定常時に悪影
響を与える。一方、応答を遅くすれば、出力電圧のりプ
ルは小さくなるが、受信過渡状態時に有害である。” In the configuration described in item 1, the output voltage EO or the CPU shown in FIG.
Depending on the data received from (8), the response when switching from a low voltage to a high voltage is determined by the feedback circuit (1
It is determined by the time constant of B). In this case, if the response is made faster, the output voltage ripple will increase, which will have an adverse effect on steady reception. On the other hand, if the response is delayed, the output voltage ripple will be reduced, but this will be harmful during reception transient conditions.
したがって、」1記従来のものでは両者の場合の折衷的
な時定数にて使用せざるをえず、応答を速くすることと
りプルを少なくすることにはおのずと限界があった。Therefore, in the conventional device described in item 1, a compromise time constant must be used in both cases, and there is a natural limit to speeding up the response and reducing pull.
[発明の概要1
この発明は上記のような従来のものの欠点を除去するた
めになされたもので、帰還回路の電荷を放電させるため
のダイオードを設けることにより、リプルを少なくして
も高速応答の可能なローパスフィルタ回路を提供するこ
とを目的としている。[Summary of the Invention 1 This invention was made to eliminate the drawbacks of the conventional ones as described above. By providing a diode for discharging the charge in the feedback circuit, it is possible to reduce ripple and achieve high-speed response. The purpose is to provide a possible low-pass filter circuit.
[発明の実施例] 以下、この発明の実施例を図面にしたがって説明する。[Embodiments of the invention] Embodiments of the present invention will be described below with reference to the drawings.
第1図はこの発明によるローパスフィルタ回路の実施例
を示している。図において、(18)、(20)は抵抗
、(21)はコンデンサで、これらによってローパスフ
ィルタが構成される。(18)は抵抗(18)の両端に
接続されたダイオード、 (22)はスイッチングが可
能でかつ高入力インピーダンスの位相反転増幅回路、(
23)は位相反転#!I4@1回路〔22)の入出力間
に接続された帰還回路、(24)は負荷抵抗、E
“iは入力電圧、EOは出力電圧である。FIG. 1 shows an embodiment of a low-pass filter circuit according to the invention. In the figure, (18) and (20) are resistors, and (21) is a capacitor, which constitute a low-pass filter. (18) is a diode connected to both ends of resistor (18), (22) is a phase inversion amplifier circuit that can switch and has high input impedance, (
23) is phase inversion #! The feedback circuit connected between the input and output of the I4@1 circuit [22], (24) is the load resistance, and E
“i is the input voltage and EO is the output voltage.
上記構成において、帰還回路(23)の時定数は定常受
信状態に出力電圧Eoのリプルか少なくなるように設定
しである。ここで、位相反転増幅回路(22)の入力回
路にはダイオード(18)が接続されて時定数の小さい
放電回路が形成されているので、帰還回路(23)の電
荷をこのダイオード(19)を通して瞬特に放電させる
ことができる。したがって、リプルが少なくなるように
したにもかがわらず、出力電圧Eoが高くなる方向に変
化する場合の応答を高速化することができる。In the above configuration, the time constant of the feedback circuit (23) is set so that the ripple of the output voltage Eo is reduced in the steady reception state. Here, since a diode (18) is connected to the input circuit of the phase inversion amplifier circuit (22) to form a discharge circuit with a small time constant, the charge of the feedback circuit (23) is passed through this diode (19). It can be discharged instantaneously. Therefore, although the ripple is reduced, it is possible to speed up the response when the output voltage Eo changes in the higher direction.
第4図は、応答特性を示している。実線がこの発明によ
るもの、破線は従来のものの特性である。これからもわ
かるように、応答特性は帰還回路(23)の放電回路を
設けたこの発明のほうがはるかに優れている。FIG. 4 shows the response characteristics. The solid line is the characteristic according to the present invention, and the broken line is the characteristic of the conventional one. As can be seen from this, the response characteristics of the present invention, which includes a discharge circuit for the feedback circuit (23), are far superior.
[e明の効果]
以」二のように、この発明によれば、位相反転増幅回路
の入力回路に帰還回路の電荷を放電させるため・のダイ
オードを設けたので、帰還回路の時定数を定常受信状態
に出力電圧のりプルが少なくなるように設定しても高速
応答が可能なローパスフィルタ回路を提供することがで
きる。[Effect of e-light] As described in Part 2, according to the present invention, a diode for discharging the charge of the feedback circuit is provided in the input circuit of the phase inversion amplifier circuit, so that the time constant of the feedback circuit can be kept constant. It is possible to provide a low-pass filter circuit that is capable of high-speed response even if it is set so that the output voltage ripple is small in the receiving state.
11図はこの発明によるローパスフィルタ回路の実施例
を示す回路図、第2図は従来のローパスフィルタ回路の
回路図、第3図はPLL回路を用いて選局回路をコント
ロールするシステムの例を示すブロック回路図、第4図
はローパスフィルタ回路の応答特性を示す図である。
(18)・・・抵抗、(18)・・・ダイオード、(2
0)・・・抵抗、(21)・・・コンデンサ、(22)
・・・位相反転増幅回路、(23)・・・帰還回路。
なお、図中、同一符号は同一または相当部分を示す。Figure 11 is a circuit diagram showing an embodiment of a low-pass filter circuit according to the present invention, Figure 2 is a circuit diagram of a conventional low-pass filter circuit, and Figure 3 is an example of a system that uses a PLL circuit to control a channel selection circuit. The block circuit diagram, FIG. 4, is a diagram showing the response characteristics of the low-pass filter circuit. (18)...Resistor, (18)...Diode, (2
0)...Resistor, (21)...Capacitor, (22)
... Phase inversion amplifier circuit, (23) ... Feedback circuit. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
グが可能でかつ高入力インピーダンスの位相反転増幅回
路と、この位相反転増幅回路の入出力間に接続された帰
還回路と、上記位相反転増幅回路の入力回路に設けられ
、上記帰還回路の電荷を放電させるためのダイオードと
を有することを特徴とするローパスフィルタ回路。(1) A phase inverting amplifier circuit with a low-pass filter connected to its input and capable of switching and having high input impedance, a feedback circuit connected between the input and output of this phase inverting amplifier circuit, and an input of the phase inverting amplifier circuit. A low-pass filter circuit comprising: a diode provided in the circuit for discharging the charge of the feedback circuit.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59124094A JPS611107A (en) | 1984-06-13 | 1984-06-13 | Low-pass filter circuit |
US06/736,751 US4749951A (en) | 1984-06-13 | 1985-05-21 | Low-pass filter circuit with variable time constant |
CA000482319A CA1241711A (en) | 1984-06-13 | 1985-05-24 | Low-pass filter circuit |
CA000548540A CA1245309A (en) | 1984-06-13 | 1987-10-02 | Low pass filter circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59124094A JPS611107A (en) | 1984-06-13 | 1984-06-13 | Low-pass filter circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS611107A true JPS611107A (en) | 1986-01-07 |
Family
ID=14876772
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59124094A Pending JPS611107A (en) | 1984-06-13 | 1984-06-13 | Low-pass filter circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS611107A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1991011685A1 (en) * | 1990-01-31 | 1991-08-08 | Kabushiki Kaisha Komatsu Seisakusho | Position detector |
-
1984
- 1984-06-13 JP JP59124094A patent/JPS611107A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1991011685A1 (en) * | 1990-01-31 | 1991-08-08 | Kabushiki Kaisha Komatsu Seisakusho | Position detector |
US5327078A (en) * | 1990-01-31 | 1994-07-05 | Kabushiki Kaisha Komatsu Speisakusho | Position detecting apparstus having a mean value calculating circuit including a low pass filter |
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