JPS6111068B2 - - Google Patents

Description

[Detailed description of the invention]

TECHNICAL FIELD This invention relates generally to ignition circuits for thyristor type power converters, and more particularly to improved circuits for controlling the operation of power converters feeding electrical loads from polyphase alternating current sources. Numerous circuits and schemes are available today for selectively conducting controlled rectifiers of various types of converters to supply power to loads from polyphase alternating current sources. Of course, the type of rectifier used will to some extent determine the type of control used, but by far the most commonly used controlled rectifiers are silicon controlled rectifier type thyristors. A thyristor conducts when a forward bias voltage is applied and a signal is applied to its gate electrode, and remains in a conductive state until the voltage between its anode and cathode becomes zero or negative. circle. There are various problems in controlling power converters. Among the problems is that the magnitude of the gate signal required to make the thyristor conductive is not large;
In order to prevent false ignition of the thyristor, it is necessary to provide suitable protection against both line and other noise. Furthermore, especially in the case of reversing converters, it is highly desirable to be able to vary and optimize the firing sequence in order to ensure smooth and continuous operation of the device. others,
If for some reason the thyristor is conducting at an incorrect time, it is necessary to provide a means to recover the device. The most common reason for incorrect conduction is that the thyristor fails to commutate (turn off) at the correct time, and the usual countermeasure is to switch off the thyristor that is next scheduled to conduct. It fires earlier than normal to force erroneously conducting thyristors into a non-conducting state. This is usually called forced ignition. Another problem particularly relevant to polyphase converter circuits is the need to properly synchronize the firing of the thyristors in each phase. Typically, this is done by closely balancing the firing circuits of each phase to ensure uniform operation. Aging of components and temperature fluctuations make it difficult to maintain proper synchronization and balance. All of the problems mentioned above have been recognized in the past and numerous solutions have been proposed, many of which involve relatively large costs. Usually, it's a compromise between cost and performance. Accordingly, it is an object of the invention to provide an improved ignition circuit for a power converter. The present invention achieves these and other objects by first determining a predetermined relationship between the voltages to the neutral point of two adjacent phases of an alternating current source. In response to sensing this point, a digital count representing the time-phase relationship for that point is generated, and this count is used as an address;
Recall the contents of a storage location in storage. The contents of the memory device thus addressed have data specifying or representing the time and firing order for the rectifier of the power converter, and in response thereto a signal is generated and used to perform the power converter. Make the individual rectifiers of the device conductive. The present invention will be more easily understood from the following description of preferred embodiments with reference to the drawings. FIG. 1 shows a typical power converter for supplying power to a motor load, in the case shown a reversible DC motor. As shown in FIG. 1, the AC source has three phases as shown by lines L1, L2, and L3, and the bridge itself consists of 12 thyristors. These thyristors are controlled by the thyristor firing control device of the present invention. The actual power conversion bridge is
It includes six forward thyristors 1F to 6F and six reverse thyristors 1R to 6R. source, line L
1, L2, L3 and the bridge are conventional as shown, with the output of the bridge being supplied to the motor. During forward motor operation, forward thyristors 1F to 6F are fired, and for reverse motor operation, thyristors 1R to 6R are made conductive. A thyristor firing control system, in accordance with the present invention, receives input from two of the three lines of the source, shown in FIG. 1 as lines L1 and L3. The output of the thyristor firing control device goes out on 12 lines. These lines are connected to the gate electrodes of the 12 thyristors of the bridge via suitable isolation means. For simplicity, the actual connections to the gates are not shown in the diagram. FIG. 2 shows in block diagram form a preferred embodiment of the invention. As shown in Figure 2, lines L3 and L1
is applied to a detector 10, which detects a particular phase relationship between the voltages appearing on these two lines. As will be explained further below, the voltage relationship chosen for this example is when L1 becomes positive with respect to L3. The output of detector 10 is a DC level signal, which is the input to digital angle synthesizer 12. The synthesizer 12, in this embodiment,
A digital count, 9 bits in this embodiment, is generated representing the phase angle measured from the point detected by the detector. Combiner 12-9
The output of all bits is provided as an address input to storage 14. A storage device 14 stores the output of the combiner 12, the signal 1RROT (which specifies which group of thyristors is used) and the synchronization signal 1.
In response to FIRE, it outputs a signal that defines the sinusoidal waveform as well as the selection of cells to fire. further 60° or
There is an output representing any angular displacement of 120°. This is used to perform forced firing of certain cells when required under abnormal conditions, allowing time sharing of the sine wave. Line current detection circuit 16 senses the presence of current in the AC feed line and produces an output signal I _A representative of the magnitude of this signal. An inversion fault detection circuit 18 is provided which outputs a signal InF when a DC fault occurs within the device. A DC fault is essentially the presence of two thyristors conducting simultaneously in the same phase of the bridge, thereby effectively shorting the bridge and the load. Usually this results from commutation failure of one thyristor. Line current detection circuit 16 and reverse fault detection circuit 18 send their output signals to forced firing circuit 20. This circuit also receives as inputs a 3-bit input from digital angle synthesizer 12 and a 2-bit input from storage 14. The forced firing circuit 20 outputs a signal 1FF which is applied to the firing logic circuit 22 when conditions within the device require forced firing of a certain thyristor to correct a fault. Firing logic 22 also receives an 8-bit input from memory 14. This input instantaneously represents the instantaneous value of a sine wave, in this case a cosine wave. Firing logic circuit 22
Another input to comes from the reference. This standard is
Signal 1PD, which may be adjustable by the operator to specify a desired level of operation for the entire converter, is another input, taken from storage 14. The output of the firing logic circuit 22 is the signal 1FIRE, which is the basic signal used to initiate the signal applied to the gate circuits of the bridge rectifiers (cells) of the converter to cause them to conduct. A signal 1FIRE is applied to the cell selection and firing circuit 24. This circuit also receives a 4-bit input from memory 14 which selects which cell of the bridge to fire, and another signal 1IA 28 taken from inversion logic circuit 26. In response to these signals, a cell selection and firing circuit selectively produces outputs on the twelve output lines. These output lines are connected through suitable isolation circuits to the individual gate electrodes of the bridge's 12 thyristors, serving to make them conductive at the proper times. To enable reverse operation, signal 1FIRE,
An inverting logic circuit 26 is provided which receives signals from the digital angle synthesizer 12 labeled I _A and 15°/8. Furthermore, a signal 1PD is input from the storage device 14. This reversal logic circuit controls the direction of rotation and together with the previously mentioned signal 1IA28 the previously mentioned signal 1
Output RROT. The above is a general description of the device of this invention, and the basic idea of this device is to detect a specific point in the phase relationship of the line voltage and to generate a digital count representing the time-phase relationship thereto. It turns out that this happens. This digital count accesses a location in memory from which an indication is output specifying the next cell to fire as well as the current phase angle of that cell relative to the normal firing range. Additionally, means are provided to allow bidirectional operation and to force firing of the bridge thyristor under certain or selected conditions, as will be explained in more detail below. FIGS. 3 to 6, together with FIGS. 7 to 9, show in detail the operation of the apparatus of the present invention.
Referring first to FIG. 3, it can be seen that the signals from lines L3 and L1 are applied to operational amplifier 30 via two input resistors 32,34. L
The signal from L1 is applied to the inverting input of amplifier 30, and the signal from L1 is applied through resistor 34 to the non-inverting input. This non-inverting input is also connected to ground via a resistor 36. A feedback resistor 38 is connected between the output and the inverting input of operational amplifier 30. Amplifier 30 acts as a differential amplifier;
The output is shown in graph B of FIG. In Figure 7,
Graph A shows the line condition of a three-phase source with three phases indicated by L1, L2, and L3 with respect to the neutral line. As shown in graph B of FIG. 7, the output of amplifier 30 is a sine wave, which is essentially the same as the difference between L1 and L3, apart from being multiplied by a certain factor. . Note that the method described above for extracting this signal is necessary because a neutral point is not available in standard three-phase sources. The output of amplifier 30 is applied to a -90° phase shift circuit 40. The main purpose of this circuit is to
, but in this particular case it also produces a 90° phase shift. The output C of wave generator 40 is shown in graph C of FIG. 7, which is the same as sine wave B except for a 90 degree phase shift. The output of wave generator 40 is applied to the non-inverting input of comparator 42, the inverting input of which is coupled to ground. Therefore, the level signal D output from the comparator 42 increases when the signal C crosses the zero axis, and decreases when the output signal C crosses the zero axis again.
Therefore, as shown in graph D in FIG. 7, a signal exists at the output of the comparator 42 for an electrical angle of 180 degrees. The signal from comparator 42 is the input to a D-type or triggered flip-flop 44 within digital angle synthesizer 12. This type of flip-flop usually has a trigger terminal shown by an arrow, a D input terminal, and a break terminal C.
Sometimes there aren't any. The output is a "1" and/or "0" terminal. In this type of flip-flop operation, output 1 is equal to the input at terminal D when the trigger signal or clock signal is applied to the trigger terminal. In the present case, the output of comparator 42, signal D, is applied to the trigger input of flip-flop 44, whose D terminal is connected to the voltage on the line designated +V. As seen in graph E in Figure 7,
The output of flip-flop 44, signal E, is in this case a small voltage spike. A count terminal of flip-flop 44 receives input from AND gate 46. This AND gate receives signal E from flip-flop 44 as one input.
Another input to AND gate 46 comes from the output of second flip-flop 48. The D terminal of this flip-flop is connected to the voltage +V, and the signal F is supplied to the trigger terminal. This signal is shown in graph F of FIG. 7 and is a DC level that exists for 180 degrees. How to extract signal F will be explained later. The output of AND gate 46 is connected to the count terminals of two flip-flops 44, 48 to reset them at the proper time. The output of flip-flop 48 is shown in graph G of FIG. 7 and is shown to be a pulse that occurs for a relatively short period of time when first occurring. The outputs of the two flip-flops 44, 48 are provided as inputs to an operational amplifier 50. This amplifier, together with associated circuitry, acts as a low pass filter with limited integration capability. To this end, signal E from flip-flop 44 is passed through input resistor 52 to the non-inverting input of amplifier 50, the same terminal being connected to ground through a series connection of resistor 54 and capacitor 56. flipflop 48
The signal G output from the amplifier 5 passes through a resistor 58.
0 is applied to the inverting input of resistor 6, and this inverting input is applied to the resistor 6
0 and the output of amplifier 50 via a series connected feedback path including capacitor 62 . The output of the amplifier 50 can be regarded as an error signal,
As will be seen from the description below and from graph H in FIG. 7, some drift in the frequency of the power supply voltage is compensated for. As shown in FIG. 3, signal H, which is the output of operational amplifier 50, is applied to voltage controlled oscillator 64. This acts to output a signal whose frequency is controlled to be a multiple of the instantaneous line frequency. That is, since the output of the voltage controlled oscillator 64 is a function of the input signal H, and since the signal H may change temporarily from its steady state value in response to small variations in line frequency, the output of the voltage controlled oscillator 64 also It can be seen from Figure 7 that this changes. In the particular embodiment of the invention described herein, voltage controlled oscillator 64 outputs a frequency of 768 times the line frequency. The actual frequency chosen is somewhat arbitrary, but should be large enough to divide the 360° period of the line frequency into a reasonable number of parts to provide good resolution. As will be seen below, the particular frequency chosen will cause the line to divide the 360° period of the line frequency into 15/16 degree segments. The output of voltage controlled oscillator 64 is applied to a trigger terminal of digital (eg, binary) counter 66 . Binary counter 66 is shown having nine outputs. These are represented by numerical values equal to ²⁰ to ²⁸ , respectively. These outputs are 15/16 degrees
It is also expressed as a power of . That is, the output ranges from 15/16 degrees to 240 degrees. In reality, the binary counter 66 is a 10-bit counter, with the least significant bit being a dummy, so that the least significant output shown will be in one of its states for 15/16 degrees of time. You can get a pulse that stays in place. binary counter 66
The 240 degree and 120 degree outputs become the inputs of an AND gate 48 whose output is sent to the reset terminal of the binary counter, so that every 360 degrees of line frequency the binary counter is reset and the voltage controlled oscillator is reset. Counting resumes when a pulse from 64 occurs. As shown in Figure 3, 30°, 60°, 120° and 240°
The outputs corresponding to the degrees are sent to two blocks 70 and 72 labeled 90 degrees and 270 degrees, respectively. These blocks represent simple logic trees and act to output a signal when the count from the counter corresponds to the angle entered. That is, when the 60° and 30° lines are high and the 120° and 24° lines are low, the block labeled 90° will output a signal. Similarly,
When the 240° and 30° lines are high and the 120° and 60° lines are low, the block marked 270° outputs a signal. 90° block 70 and 270° block 72
The signals from the flip-flop 74 are applied to the set and count terminals of the flip-flop 74, respectively, and the output thereof becomes the signal F described above. It is therefore seen that signal F appears or exists for 180°. The way the error signal is generated, which was briefly explained earlier, is
Next, it will be explained in more detail. In the graph of Figure 7,
It was assumed that there was a slight frequency shift in the supply voltage, as shown by signal F, and that during the previous cycle shown the voltage controlled oscillator was operating at a slightly faster rate than in the case shown in FIG. Therefore, signal F is signal C
goes high shortly before the zero crossing of G, thus generating signal G for a short period of time. When a zero crossing of signal C occurs, signal D is applied to flip-flop 44 and AND gate 64 resets both flip-flops 44, 48 as previously described. By thus generating signal G, error signal H is generated. In the graph of Figure 7, the oscillator 64 is on the right side.
The effect is shown when the output frequency of is lowered, but this case is similar. Of course, what is shown in FIG. 7 is greatly exaggerated for illustrative purposes; the frequency drift is typically very small, and therefore the amount of correction is also very small. The nine outputs of binary counter 66 are the inputs to the storage shown in FIG. Storage 14 includes control storage 76 and sine wave storage 78 . In the embodiment of the invention actually used, these two storage devices are read-only storage devices (ROM), but it should be noted that any form of storage device whose reading is not destructive may be used. Nor. Turning first to control memory 76, this memory has a plurality of individually addressed locations as will be explained below. In the particular embodiment of the invention actually constructed, the control memory 76 is
Has hexadecimal positions up to 3FF. Each location is an 8-bit word that is divided into two 4-bit bytes. As an example, the eighth
The figure shows the contents of the storage location expressed in hexadecimal 2A. The three least significant bits of the lower byte contain an indication of the next cell to fire. As is the case with other figures, in Figure 8 this display is 1NA,
It is represented by the signals or indications 1NB and 1NC. The most significant bit of this byte is 1
It has a display called PTL (Pulse Train Limit), which will be explained in more detail later. The upper byte has an indication in its least significant bit, which is not used in the embodiment described here, but is reserved for the indication of logic faults. The second bit from the bottom of this byte indicates whether or not the inhibit signal is enabled, as will be explained in more detail later, and the two upper bits are each 60 bits.
The selected displacement angles of SA60° and SA120° of 120° and 120° are expressed in ascending order, which means that when it is appropriate to shift the phase with the bridge thyristor for different phases, as will become clear from the later explanation, validate. A complete storage map showing the entire contents of the control storage for one embodiment of the invention is shown in Table A. In FIG. 4, it can be seen that control memory 76 outputs signals 1NA, 1NB, and 1NC to the D terminals of three flip-flops or latches 80, 82, and 84, respectively. As previously mentioned, in the embodiment described here, these three signals determine which of the six thyristors in the forward or reverse power conversion bridge are to fire next. Select. Signal 1RROT is applied to the D input of the fourth latch 86.
is applied, which in the case of a motor load represents the direction of the torque and thus, broadly speaking, an indication of whether the forward or reverse thyristor is fired in the bridge. For this reason, 1PA, 1
The outputs of these four latches, labeled PB, 1PC, and 1PD, select the currently fired thyristor within the bridge. Latches 80-86 change state when signal 1FIRE is applied. This signal is generated as explained below. FIG. 9 is a decoding truth table showing how signals 1PA through 1PD represent combinations of individual cells that are fired at any particular time. Of course, those listed here are selected for the embodiment currently being described. Without intending to explain this truth table in its entirety, it can be seen that when 1PA equals 1 and the remaining signals equal 0, cells 1F and 2F (FIG. 1) are rendered conductive. Signals 1PA to 1PD are signal 1
Together with RROT and the five most significant bits of the output of binary counter 66, it serves as an address signal for control storage 76. The storage device 76 stores output signals 1NA, 1NB, 1
Besides NC, as a function of the addressed position,
The signals previously described with respect to FIG.
PLT, Prohibited, generates SA120° and SA160°.
The latter three signals are combined with the lower six bit output of binary counter 66 to address sine wave storage 78. The storage device 78 has successive values of the 180 degree cosine wave at each location in 15/16 degree increments or steps. For this reason, the storage device 78 uses 193 storage locations for the cosine wave. Note that in the actual case, the actual contents of sine wave storage 78 are the cosine plus one to avoid negative numbers. A storage map for each location of storage device 78 is shown in Table B. In this map, the hexadecimal positions 000 to 000 for the cosine wave are
It turns out that 0C0 is used. Since a 9-bit address is used, all other available positions (0C1-1FF) are encoded as binary 1's to prevent the converter thyristor from firing. In FIG. 5, it can be seen that an inversion fault detection circuit 18 is provided which outputs InF to the forced ignition circuit 20. Although the inverting fault detection circuit is not shown in detail, the specific nature of which is not important to this invention, it is intended to generate an output signal in the event of what is commonly referred to as a DC fault or shoot-through. This is because any known circuit may be used. Line detection circuit 16 is also shown outputting signal I _A to forced firing circuit 20 . As mentioned earlier, the signal I _A represents the magnitude of the current flowing in the lines of the power supply, and in the figure three current transformers 8 are coupled to the three lines L1, L2, L3 respectively.
8,90,92. The outputs of these three current transformers are fed to a suitable rectifier bridge 94, the output of which is a DC signal proportional to the magnitude of the current flowing in the three lines. The signal I _A is applied to a suitable analog-to-digital converter 96 in the forced ignition circuit 20, the output of which provides a digital signal on five lines representative of the magnitude of the signal I _A. It has been shown that That is, the signals on these lines define the commutation angle required to commutate the sensed magnitude of current. Typically, the higher the current, the longer the commutation time required. These five lines from converter 96 are the inputs to switch 98. Switch 98 also has five wires as inputs labeled strap input @90°. These inputs can be taken from switches that can be set by the operator to convey a display proportional to the 90° angle.
If an inversion fault exists, as indicated by the signal InF from circuit 18 being high, these straps are provided by switch 98 as the output of the five output lines from the switch.
If there is no reversing fault, switch 98 will
The signal from digital converter 96 is output. Five output lines from switch 98 carry a binary representation of the angular limit, which is transmitted to comparator 10.
0. The comparator 100 receives three signals from the digital angle synthesizer 12 (signal 15°/2,
15° and 30°) and the signals SA60° and SA120° from control memory 76 are also provided as inputs. As shown in FIG. 5, the output from switch 98 can be considered as word A, and the input from the storage device and digital angle synthesizer can be considered as word B. Comparator 100 compares these two digital signals.
Simply compare the numerical values of the words and when word A is greater than or equal to word B, output 1FF
(forced ignition) occurs. Therefore, the signal 1FF is generated to ignite a rectifier in case of a reversal fault or other than normal times to ensure commutation of the current conducting rectifier of the bridge. It turns out that there are other times when it is necessary. Continuing with FIG. 5, the sine wave storage 78 signal output is connected to the firing logic circuit 22, specifically to the digital-to-analog converter 10 within the logic circuit.
2 as an input. This converter outputs a cosine wave in response to sequential inputs from storage device 78. As mentioned above, this is offset by 1 to prevent it from being negative. The output of converter 102 is applied to the inverting input of comparator 104, and the output of amplifier 106 is applied to its non-inverting input. Amplifier 106 has a resistor 10 at its inverting input.
8 and at its non-inverting input a resistor 11
A reference signal is applied via 8. It is schematically shown that this reference signal is taken from a potentiometer 110 connected between a positive voltage source (+V) and ground. This is a reference that can be set by the operator and is a DC level reference that is proportional to the desired output of the converter of FIG. Feedback resistor 112 is connected between the inverting input of amplifier 106 and its output. Amplifier 106 has a gain of ±1
and outputs a positive or negative value proportional to the reference from potentiometer 110 to comparator 104 . The sign of this signal is a function of the previously mentioned signal 1PD. In Figure 5, signal 1PD is normally open contact 1
16 is shown applied to the coil 114 of the relay. 1PD is the value of “1”,
Contact 11 indicates that operation in the opposite direction is desired.
6 is closed and the non-inverting input of amplifier 106 is connected to ground. When 1PD is equal to "0", switch 116 remains open. For this reason, the amplifier 10
It can be seen that the output of 6 is an analog signal equal to either a positive or negative value as determined by the criteria established by potentiometer 110, as previously discussed. Comparator 104, in response to its two inputs,
The value of the signal from the digital-to-analog converter 102 (the value of the biased cosine wave) is transferred to the amplifier 106.
generates a logic 1 signal at its output when it is less than or equal to the reference signal applied from the .
Conversely, when the reference is less than the cosine signal from converter 102, comparator 104 outputs a logic 0 signal. In the firing logic circuit 22 of FIG. 5, it can be seen that there are six input signals labeled inhibit inputs. Although these inputs are not directly related to this invention, in a practical device, there is a safety feature that prohibits the operation of the converter of this device when there is some malfunction such as overcurrent, overvoltage, etc. It is an input from another part of the device that serves as an element. 6 prohibited inputs are 3 each
are shown applied to a pair of OR gates 120, 124, respectively. The outputs of these gates are supplied to inverting circuits 126 and 128. 2
The outputs of the two inverting circuits 126, 128 are at a high binary level when there is no inhibiting action from other parts of the circuit, and at a low level when there is a reason to inhibit operation of the device.・Gate 130,
132 is prohibited. The second input to AND gate 130 is the logic level of comparator 104. The second input to AND gate 132 is the aforementioned signal 1FF. The outputs of these two AND gates are the inputs of OR gate 134, whose output is signal 1FIRE. Therefore,
Signal 1FIRE is generated when there is no inhibit input and forced firing signal 1FF is present, or when the value of the biased cosine wave extracted by digital-to-analog converter 102 is greater than the reference signal supplied from potentiometer 110. It can be seen that it occurs when it is large. As seen in FIG. 6, the signal 1FIRE output from the firing logic circuit 22 of FIG. 5 is applied to a pulse train generator 136 which outputs a pulse train to effect the well-known pulse train firing operation. This pulse train is applied to one input of OR gate 138. Its other input is signal 1 from storage device 22.
PTL and signal 1IA generated as explained later
It is 28. The output of OR gate 138 is applied to the inactive terminal of decode logic tree circuit 140.
Another input to logic tree circuit 140 is signal 1 taken from memory latches 82-86.
PA, 1PB, 1PC, 1PD. In response to these input signals, circuit 140 outputs GD1F through GD6.
Select two of the 12 output lines labeled F and GD1R to GD6R (see Figure 9). The signals appearing on these lines are sent to the gate terminals (or gate circuits) of the thyristors (FIG. 1), each represented by the same symbol, of the bridge and serve as the ignition signal. Therefore, when the signal 1PTL or the signal 1IA28 from the storage device is not present, the input lines 1PA to 1
It can be seen that a pulse train having the same frequency as the pulse train generator 36 appears at the output of the tree circuit 140 selected by PD. That is, in that the signals 1PD to 1PD normally hold the selected line high and the pulse train generator 136 applies a pulse train that disables the circuit 140, its output is equal to the off time of the pulse train from the generator 136. have the same frequency according to Therefore, the signals appearing on lines GD1F to GD6F and GD1R to GD6R control the operating or firing order of the bridge thyristors and thereby control the power delivered to the load. The portion that remains to be explained in FIG. 2 is the inversion logic circuit 26 shown in FIG. This generates the aforementioned signal 1RROT which determines which package of thyristors (forward or reverse) is used. In the illustrated example, a logical 0 represents a forward package and a logical 1 represents a reverse package. 6th
As shown, inversion logic circuit 26 includes a pair of switches 142,144. These switches are controlled by the operator and allow selection of either forward only or reverse only operation. A signal 1SFD obtained by closing the switch 142 is applied to the inverter 146,
Its output is applied to AND gate 148.
The signal 1SF produced when switch 144 is closed is applied via inverter 150 to the second input of AND gate 148. When neither switch is closed, AND gate 148 is enabled and the output of this gate is connected to OR gate 152.
This gate outputs a signal 1RROT. Therefore, only reverse operation can be achieved if both switches are closed. That is,
Signal 1RROT becomes logic 1. If signal 1SFD is high (switch 142 is open), signal 1RROT
The value of is a function of the signals 1FIRE and 0IA28, as will be explained. In FIG. 6, the signal I from the line current detection circuit 16
It can be seen that _A is applied to the non-inverting input of comparator 154. Its inverting input is connected to a positive reference voltage indicated by battery 155. The output 1IA of comparator 154 is the input to the D terminal of flip-flop 156, and its 1 output is signal 1IA 28, which is the input to OR gate 138 of cell selection and firing circuit 24. The 15°/8 signal from digital angle synthesizer 12 acts as a clock and is applied as a trigger input to a 4-bit binary counter 158. The enable terminal of counter 158 receives input from the "1" output of flip-flop 160. The D terminal of this flip-flop is connected to ground, and its trigger terminal is connected to the carry output of counter 158. flipflop 16
The 0 set terminal receives the aforementioned signal 1FIRE as an input signal. Therefore, each time address 1FIRE occurs, flip-flop 160 is set and enables a 4-bit binary counter, which counts the 15°/8 signals from the memory. In that this is a 4-bit counter, the carry terminal will have a high level signal once every time the signal 1FIRE occurs, but this carry signal will exist for a period equal to 15°/8. The process ends 30 degrees (16 x 15/8) in electrical angle after the signal 1FIRE is generated. Counter 15
The output from the carry terminal of 8 is flip-flop 1.
Serves as a trigger input for 56. The fail terminal of flip-flop 156 is connected to receive signal 1FIRE. flip flop 156
The "1" output of is the aforementioned signal 1IA28, and assuming that a power supply current is present, this signal exists for a period of approximately 28 degrees from the time the signal 1FIRE occurs until the next occurrence of 1FIRE. I understand that. This signal is applied to the OR gate 138 of the cell selection and firing logic circuit 24, disabling the circuit. The other part of FIG. 6 shows that the "0" output of flip-flop 156 is
This shows that one input of 2 is 0IA28, and the other input is 1PD. Therefore, when only one, but not both, of the inputs to exclusive OR gate 162 are present, a high level signal is output from this, which is
It can be seen that this is one input to gate 164. The second input to this AND gate is the aforementioned signal 1SFD. This is in that the output of AND gate 164 becomes the second input to OR gate 152, as shown in the signal 1.
This is the second means by which RROT is generated.
Therefore, the output of AND gate 148 is low and 1.
If SFD is high, then the value of 1RROT is high (“1”) when either 1PD or 0IA28 (but not both) are high. From the above description, we describe a device that allows the use of a single comparator circuit to generate multiple-trigger signals that can be used in power conversion bridges, eliminating the need for multiple circuits and eliminating the associated errors. I hope you understand what happened. Due to the binary nature of the circuit, noise rejection is excellent and the contents of the storage device,
Alternatively, when ROM is used, it is easy to change the contents of a plurality of storage devices, so it is obvious that the firing order can be changed easily. Due to the nature of this device, the firing sequence can be optimized and during the reversal operation,
This is especially true when switching from readily available digital inputs to forced ignition, and overall the performance of the ignition control circuit can be increased at a moderate cost.

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【table】 [Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing one type of power converter to which the present invention can be applied, and shows the overall relationship between the present invention and the power converter. FIG. 2 is a block diagram of an embodiment of this invention, FIGS. 3 to 6 are circuit diagrams showing the individual components of this invention shown as blocks in FIG. 2, and FIG. 7 shows the operation of this invention. FIG. 8 is a waveform diagram for explanation, FIG. 8 is a diagram showing a matrix of one type of word stored in a storage device, and FIG. 9 is a decoding truth table useful for understanding the operation of a part of the present invention. Description of main symbols: 10: Detector, 12: Digital angle synthesizer, 14: Storage device, 22: Firing logic circuit, 24: Cell selection and firing circuit.

Claims (1)

[Claims] 1. In an ignition circuit that generates a signal that conducts a control rectifier of a power converter in order to control the power supplied to a load from an alternating voltage source, selection during a voltage cycle of a voltage source. means for sensing a selected point and providing an output signal in response; and means for generating a multi-bit address signal representative of a time-phase relationship for the selected point in response to the output signal; a plurality of selectively addressable storage locations addressed by the address signal, each storage location containing predetermined data representative of a firing order and time of a rectifier of the power converter; An ignition circuit having a memory device and means for generating a signal that selectively conducts individual rectifiers in response to the contents of the addressed locations. 2. The ignition circuit according to claim 1, wherein the means for generating the address signal generates a digital count. 3. The firing circuit as claimed in claim 1, wherein the storage device has two separate areas, the first area having data regarding the cell firing order;
The second area has a ignition circuit with values corresponding to a sinusoidal waveform. 4. In the ignition circuit according to claim 3, the address for the first area of the storage device is
an address for a second area of the storage device comprising a portion of the address signal and a portion of the contents of a previously addressed location of the first area; 1st
An ignition circuit consisting of another part of the contents of the last addressed position of the area. 5. The ignition circuit according to claim 4, including means for generating another signal representing one of the two types of operation of the converter, the other signal being a first one of the storage device. Ignition circuit contained within the address of the area. 6. The ignition circuit according to claim 5, wherein when the power converter is used to supply power to a motor load, the another signal represents a desired direction of motor torque. 7. The ignition circuit according to claim 3, wherein the storage device has first and second read-only storage devices as the first and second areas. 8. An ignition circuit as claimed in claim 1, having a manual trigger for altering the generation of said signal to conduct the rectifier in response to a signal representative of a predetermined operating condition of the device. 9. In the ignition circuit according to any one of claims 1 to 8, the power converter supplies power from a multiphase AC source to a DC load, and the sensing means detects a voltage between two phase voltages of the source. and means for ascertaining a predetermined relationship between and outputting a signal representing the relationship, wherein the means for generating the address signal generates a digital count representing a phase shift with respect to the predetermined relationship in response to the signal. An ignition circuit with generating synthesis means. 10. The ignition circuit of claim 9, wherein said combining means includes means for generating a series of pulses at a rate that is a multiple of the frequency of said alternating current source, and generating said count in response to said pulses. ignition circuit containing a digital counter and a digital counter. 11. The ignition circuit as claimed in claim 2, wherein the storage device comprises a first storage means having a plurality of selectively addressable storage locations, the contents of which are then a controlled rectifier of the power converter to be fired, and a desired angle of displacement for firing of the controlled rectifier, the first storage means being addressed in response to an applied address signal; a first memory having a first portion comprising a selected portion of said digital count and a second portion retrieved from said latching means, said memory further selecting a controlled rectifier to fire next; in response to a selected input signal comprising a portion of the contents of the last addressed position of the means, a signal representative of the firing order of the controlled rectifier, and a firing control signal representative of the proper time to fire the controlled rectifier. latching means for generating said second portion; and second storage means having a plurality of selectively addressable storage locations, the contents of each storage location of said second storage means being sinusoidal. The second storage means represents the individual points of the waveform, the second storage means representing the second portion of the digital count, as well as the currently addressed position of the first storage means representing the displacement angle of the controlled rectifier to fire next. means for receiving an address signal comprising an output obtained from the control rectifier and further generating a signal for selectively conducting said control rectifier; a digital-to-analog converter for generating an output signal representative of at least a portion of the wave; and means for generating a reference signal representative of the desired output of the converter;
comparator means for generating an output signal indicative of a time to fire a controlled rectifier in the converter in response to the reference signal and the contents of a then addressed location of the second storage means; an ignition circuit having means for outputting a signal responsive to the output to cause ignition of a control rectifier of the converter.