JPS61109496A - Drive circuit for stepping motor - Google Patents

Abstract

PURPOSE:To stably rotate a stepping by providing a signal memory, sequentially storing signals in the order to be transmitted, and reading out in the transmitting order at a time interval to follow to the motor. CONSTITUTION:A step pulse signal and a rotating direction signal transmitted from an upper controller 1' are stored in a step pulse signal memory 4 and a rotating direction signal memory 5 in the transmitting order. The signals are sequentially read out from the step pulse signal memory and the rotating direction signal memory by a timing signal of the shortest pulse signal interval or larger determined by the characteristics of the motor from a timing signal generator 7 to supply the two signals to an exciter 6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement in a drive circuit for a step motor used as a control motor for electronic equipment.

2. Description of the Related Art Step motors are widely used as mechanical drive elements of electronic devices that require precise movement, such as being used as control motors for controlling the positioning of heads of flexible disk drives.

[Conventional technology]

In order to explain a conventional driving method for driving a step motor, a two-phase excitation step motor is taken as an example, and a block diagram thereof is shown in FIG. When the step pulse signal and rotation direction signal are transmitted from the upper control unit, the step motor drive circuit sends excitation signals Fl, F2 . F3. Supply F4. 6th
FXJ shows the waveform and timing diagram of a conventional example.

If the current state of the step motor is (N), then by transmitting the step pulse signal, (N) - (N+ 1') -
(N+ 2) -(N+3)→(N+4)→(N+3)
→(N+2)→(N+1)-(N)→(N+1)-(N
) indicates the state of rotation. The rotation angle driven by one step pulse signal is determined by the structure of the step motor, and the shortest pulse time interval that can follow sequentially transmitted step pulse signals is determined by the characteristics of the step motor. Therefore, the host controller creates a signal suitable for the step motor to be driven.
Supplied to the step motor drive circuit.

[Problem that the invention seeks to solve]

In the above explanation, if the step pulse signal transmitted from the host controller becomes shorter than the shortest pulse time interval determined by the characteristics of the step motor, the step motor will not rotate even if the step motor drive circuit can follow it electrically. can't keep up and loses synchronization or becomes unable to rotate. The upper control unit is required to perform time processing to maintain the shortest pulse time interval, and there is a problem in that the addition of complicated functions cannot be avoided.

[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention provides respective signal storage units for the step pulse signal and rotation direction signal transmitted from the upper control unit, and stores them in the order in which they are transmitted. The two signals are read out in the order in which they were transmitted using a readout timing signal at a time interval that can be followed by the step motor, and the two signals are supplied to the excitation circuit.

[Effect]

According to the present invention, even if the time interval of the signal transmitted from the host control section may be disturbed, the signal is converted into a time interval that allows stable rotation at all times and is supplied to the excitation circuit.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram, and the step pulse signal and rotation direction signal of the upper control unit 1 are respectively stored in the step pulse signal storage unit 4.
is stored in the rotational direction signal storage section 5, read out using a pulse signal from the timing signal generation section 7, and supplied to the excitation circuit 6.

FIG. 2 is a waveform and timing diagram of the embodiment of FIG. 1. For example, even if the step pulse signal of FIG. 6 is disrupted or shortened in time interval as shown in FIG. Since the two supplied signals are changed to the interval of the pulse signals output from the timing generator, the step motor drive signal is changed to the same signal as in FIG. 6.

Furthermore, the operation of each part will be explained using the detailed block diagram of the embodiment shown in FIG. 3, and the flow of signals will be explained in detail.

Multiplexer MPI An element that switches two input signals using a pulse signal and outputs either signal.When the step pulse signal SS is input, it outputs a signal "1", and when there is no input, it outputs a signal "0". The step pulse signal is transmitted to the step pulse signal storage unit MEM1.

Input run C1 A counter that is incremented by 1 every time a pulse signal is input, and incremented by 1 every time a step pulse signal SS is input, and the output is sent to the step pulse signal storage unit MEM1 and the rotation direction via multiplexer MP2. Specify the address of the signal storage unit MEM2.

C2 A counter that increments by 1 every time a pulse signal is input.1 is incremented each time a pulse signal from the timing signal generator TG is input, and the output is stored as a step pulse signal via multiplexer MP2. The addresses of the section MEM1 and the rotation direction signal storage section MEM2 are specified.

Multiplexer MP2 is an element that switches between two input signals using a pulse signal and outputs either signal.When the step pulse signal SS is input, it sets the address of the write counter C1, and when it is not input, it sets the address of the read power counter C2. Output.

■ [The input is the step pulse signal SS and the timing generator TG.
Outputs one of the input signals using the timing signal.

Staple Pulse Recorder MEM 1 An element that writes an input signal to a specified address using a pulse signal, and outputs a signal at the specified address except when writing. In the figure, the address is specified by the multiplexer MP2, The input signal during writing is the output of the multiplexer MPI, and the pulse signal is the output of the OR circuit OR.

-n interbone- (l standing MEM2 An element that writes an input signal to a specified address using a pulse signal, and outputs a signal at the specified address except when writing. In the figure, the address is specified by multiplexer MP2, The input signal during writing is a rotation direction signal DS, and the pulse signal is a step pulse signal SS.

Steps L±1 and L2 are elements in which a human power signal is converted into an output signal by a pulse signal and is held until the next pulse signal. The output signals and the pulse signals are all pulse signals of the timing signal generator TG.

timing zero, a timer T that generates a TG pulse signal, an AND circuit A1,
Consisting of a knot circuit N and a step pulse signal S
When S is not input, a pulse signal generated by timer T is output as a timing signal, and the signal is read from step pulse signal storage section MEM1 and rotation direction signal storage section MEM2.

An excitation signal is generated based on the signals read from the step pulse signal storage section MEM1 and the rotational direction signal storage section MEM2. However, if the signal "1" is not read out from the step pulse signal storage unit MEM1, the excitation circuit maintains the same excitation state, does not output a signal, and the step motor does not rotate.

1 song is read out from the step pulse signal storage unit MEM1,
The signal held in latch L1 is shaped into a pulse.

Next, the state of each part during operation will be explained with reference to the waveform and timing diagram of the detailed embodiment of FIG. 3 shown in FIG.

The initial state of each part, ie, the state before a signal is input, is indicated by "n".

SSI, in the order in which the pulses of the step pulse signal are transmitted,
SS2. SS3.334. If the state in which S81 is transmitted is state (b), 0 indicated by the write counter C1 is designated as address O to the step pulse signal storage unit MEM1 via the multiplexer MP2, and a signal "1" is stored there. The rotational direction signal DS has a forward direction as a signal "1" and a reverse direction as a signal "O". In the case of the example, since it is the forward direction, the signal "1" is stored at address 0 of the rotation direction storage units MF and M2.

In the state diagram of the multiplexer MP2 in the figure, the upper stage shows the count name output, and the lower stage shows the values indicated by the counter output, that is, the addresses of the two storage units.

Status! @(c) Pulse signals of the timing signal generator TG are Tl in the order of generation.
, T2. T3. Let it be T4. If the state in which TI occurs is defined as state (c), 0 indicated by the read counter C2 is transferred to the step pulse signal storage unit ME via the multiplexer MP2.
Since the address O is specified in M1, the signal at this address is output from the step pulse signal storage unit MEM1. In this case, a signal "1" is read out to the latch L1 and supplied to the excitation circuit. Rotation direction signal storage section ME
Address O is also specified for M2, and the signal “1” is sent to latch L2.
The signal is read out and supplied to the excitation circuit. At the same time, the pulse signal T1 passes through the OR circuit OR and enters the step pulse signal storage section as a write clock. The address of the step pulse signal storage unit MEM1 is the read counter C2.
is O, and the step pulse signal SS does not exist, so the signal is "O". Therefore, the step pulse signal storage unit MEM1
Address 0 of is changed from signal "1" to signal "0". That is, once the step pulse signal storage section MEM1 is read out, its contents are cleared.

When the step pulse signal SS2 is transmitted, the write counter C1 indicates 1, so a signal "1" is stored at address 1 in the step pulse signal storage section. In addition, the positive direction signal “1” of the 9 rotation direction borrow sign DS is in the rotation direction storage unit ME.
It is stored at address 1 of M2.

When the step pulse signal SS3 is immediately transmitted, the write counter C1 indicates 2, so the step pulse signal storage section stores the signal "1" at address 2. In addition, the reverse direction signal "O" for the one-rotation direction DS is sent to the rotation direction storage unit ME.
It is stored at address 2 of M2.

When the pulse signal T2 of the timing signal generator TG is generated, 1 indicated by the read counter C2 is output from the multiplexer M.
Since the step pulse signal storage unit MEM1 is designated as address 1 via P2, the signal at this address is output from the step pulse signal storage unit MEM1. In this case, the signal "1" is held in the latch L1 and supplied to the excitation circuit. Address 1 is also specified for the rotational direction signal storage unit MEM2, and a signal "1" is read out to the latch L2.
Supplied to the excitation circuit. At the same time, the pulse signal T1 passes through the OR circuit OR and enters the step pulse signal storage section as a write clock, and its address 1 is cleared from signal "1" to signal "0".

1 friend" 1→- When the step pulse signal SS4 is transmitted, since the write counter C1 indicates 3, the signal "1" is stored at address 3 in the step pulse signal storage section. In addition, the one-rotation inter-rotation code DS is the reverse inter-rotation code “O” in the rotation direction storage unit M.
It is stored at address 3 of EM2.

When the pulse signal T3 of the timing signal generator TG is generated, 2 indicated by the read counter C2 is output from the multiplexer M.
Since it is specified as address 2 to the step pulse signal storage unit MEM1 via P2, the signal at this address is output from the step pulse signal storage unit MEMI. In this case, the signal "1" is held in the latch L1 and supplied to the excitation circuit.Address 2 is also specified for the rotational direction signal storage unit MEM2, and the signal "O" is read out to the latch L2, and the excitation circuit is supplied. At the same time, the pulse signal T3 passes through the OR circuit OR and enters the step pulse signal storage section as a write clock, and its address 2 is set to the signal "1".
The signal is cleared to "0".

When the pulse signal T4 of the timing signal generator TG is generated, 3 indicated by the read counter C2 is output from the multiplexer M.
Since the step pulse signal storage unit MEM1 is designated as address 3 via P2, the signal at this address is output from the step pulse signal storage unit MEMI. In this case, the signal "1" is held in the latch L1 and supplied to the excitation circuit. Address 3 is also specified in the rotational direction signal storage unit MEM2, and a signal "0" is read out to the latch L2 and supplied to the excitation circuit. At the same time, pulse signal T4
passes through the OR circuit OR and enters the step pulse signal storage unit as a write clock, and its address 3 is the signal “1”.
” is cleared to the signal “0”.

In the above embodiment, in order to simplify the explanation, the maximum number of steps of the two counters is set to 4, and the number of addresses of the two storage units is set to 4, but the capacity of the storage unit is determined by the step pulse signal SS to be transmitted. It is determined by the speed of the pulse signal from the timing signal generator TG.

〔Effect of the invention〕

According to the present invention, the timing read out from the step pulse signal storage section MEMI and the rotational direction signal storage section MEM2 is determined by the pulse signal of the timing signal generation section TG, and is unrelated to the timing of the transmitted signal, so it depends on the characteristics of the step motor. The pulse signal interval of the timing signal generator TG is longer than the determined shortest pulse signal interval,
That is, by determining the oscillation frequency of timer T, the step motor can rotate stably. Furthermore, since the host control section does not need to consider the characteristics of the step motor, the control function is reduced and the step motor can be used more effectively.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention Fig. 2 is a waveform and timing diagram of Fig. 1 Fig. 3 is a detailed block diagram of the embodiment Fig. 4 is a waveform and timing diagram of Fig. 3 Fig. 5 Conventional Example block diagram Figure 6 Waveform and timing diagram of conventional example In Figure 1, 1' is the upper control section, 2' is the step motor drive circuit, 3 is the step motor, 4 is the step pulse signal storage section, 5 6 is a rotational direction storage unit, 6 is a timing signal generator, and 7 is an excitation circuit. In FIG. 5, 1 is a host control unit, 2 is a step motor drive circuit, and 3 is a step motor.

Claims (1)

[Claims] In a step motor drive circuit having an excitation circuit section that creates an excitation signal to be given to a driven step motor in accordance with a step pulse signal and a rotation direction signal transmitted from a higher-level control section, a step pulse signal storage section and a rotation direction signal are provided. It is equipped with a signal storage section and a read timing signal generation section, and stores the step pulse signal and rotation direction signal transmitted from the upper control section in the respective storage sections in the order in which they are transmitted, and the read timing signal outputted from the read timing signal generation section. A step motor drive circuit characterized in that the step motor is driven by applying two signals read out in the order transmitted from the respective storage sections to the excitation circuit section according to the signals.