JPS61108153A - Electronic parts and manufacture thereof - Google Patents

Electronic parts and manufacture thereof

Info

Publication number
JPS61108153A
JPS61108153A JP23165684A JP23165684A JPS61108153A JP S61108153 A JPS61108153 A JP S61108153A JP 23165684 A JP23165684 A JP 23165684A JP 23165684 A JP23165684 A JP 23165684A JP S61108153 A JPS61108153 A JP S61108153A
Authority
JP
Japan
Prior art keywords
ceramic
electronic component
conductive film
sheet
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23165684A
Other languages
Japanese (ja)
Inventor
Kenzo Senba
仙波 謙三
Satoshi Kobayashi
小林 悟志
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Original Assignee
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Semiconductor Manufacturing Co Ltd, Kansai Nippon Electric Co Ltd filed Critical Renesas Semiconductor Manufacturing Co Ltd
Priority to JP23165684A priority Critical patent/JPS61108153A/en
Publication of JPS61108153A publication Critical patent/JPS61108153A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/13Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

PURPOSE:To miniaturize an electronic part and to curb the scattering of products by a method wherein a package is constituted of a lamination of ceramic sheets, the main body of the electronic part is accommodated in a recess formed inside the lamination, and external electrodes are provided to be connected to the electrodes of the electronic part accommodated in the recess. CONSTITUTION:On a first lamination 6 of ceramic sheets 6a-6c, a second lamination 8 of ceramic sheets 8a-83 is deposited, provided with a through-hole 9. An electronic part (diode pellet) with electrodes 10a, 10b installed on its both sides is accommodated in a recess that is the through-hole 9 so that the electrode 10a may be in contact with a first conductive film 7. Thereon, a ceramic sheet 8' provided with a smaller through-hole 9' is deposited, an conductive material 11 is injected into the through hole 9' to electrically contact the electrode 10b, and then a second conductive film 12 is formed to be in electrical contact with an end of the conductive material 11. On the second conductive film 12, a 3-layer ceramic lamination 13 is deposited to occlude the smaller through-hole 9'. Interlayer conductive films 14a, 14b formed between layers at both ends of the ceramic laminations 6, 8, 13 are connected to external electrodes 15a, 15b.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は超小型の電子部品及びその製造方法に関する。[Detailed description of the invention] Industrial applications The present invention relates to an ultra-small electronic component and a method for manufacturing the same.

従来の技術 最近では電子回路装置の小形化のために、小型の電子部
品を用いて実装密度を向上させるようにしている。第2
1図は小型電子部品の一例を示すもので、図において1
は電子部品本体で、例えばダイオードペレリト、2は2
本−組のリードで、一端部を互に近接させ一直線十に配
置して、一方のリード2aにベレ・ソト1をマウントし
、ベレット1上の電極と他のリード2bとを金属細線8
にて接続している。4はベレット1を含む主要部分を樹
脂にて被覆外装した外装部を示す。
BACKGROUND OF THE INVENTION Recently, in order to downsize electronic circuit devices, smaller electronic components have been used to improve packaging density. Second
Figure 1 shows an example of a small electronic component.
is an electronic component body, for example, a diode Pellerit, 2 is a 2
This set of leads is arranged in a straight line with one end close to each other, and the beret soto 1 is mounted on one lead 2a, and the electrode on the beret 1 and the other lead 2b are connected by a thin metal wire 8.
It is connected at. Reference numeral 4 indicates an exterior part in which the main parts including the pellet 1 are coated with resin.

この電子部品は一般的には第22図に示すリードフレー
ム5を用い、ペレリト1をリード2a上にマウントする
マウント工程、ベレ、ソト1上の電極とり一ド2bを金
属細線8にて接続するワイヤポンディング工程、樹脂モ
ールド工程、リードフレーム5の不要部分を切断除去し
リード2a、2bを独立させると共に個々の電子部品に
分離する工程、リード2.a、2bを整形する工程等々
を経て、一括して製造される。
This electronic component generally uses a lead frame 5 shown in FIG. 22, and includes a mounting process in which the pellet 1 is mounted on the lead 2a, a beret, and an electrode holder 2b on the bottom 1 is connected with a thin metal wire 8. Wire bonding process, resin molding process, process of cutting and removing unnecessary parts of lead frame 5 to make leads 2a and 2b independent and separating them into individual electronic components, lead 2. A, 2b are manufactured all at once through a process of shaping and so on.

発明が解決しようとする問題点 しかしながら、この種電子部品は金属細線8のうに十分
肉厚にする必要があって小形化が制約されていた。
Problems to be Solved by the Invention However, in this type of electronic component, it is necessary to make the thin metal wire 8 sufficiently thick, which limits miniaturization.

また各工程で用いられる製造装置は各工程特有のもので
、高精度のものが必要で、寸だ複数の電子部品に対し同
時作業ができず、製造に時間を要すという問題もあった
In addition, the manufacturing equipment used in each process is unique to each process and requires high precision, making it impossible to work on multiple electronic components at the same time, resulting in a time-consuming manufacturing process.

本発明は上記問題点に鑑み提案されたもので、外囲器を
セフミックシートの積層体で構成し、この積層体に形成
した凹部に電子部品本体を収容し外部電極を形成するよ
うにし−だものである。
The present invention has been proposed in view of the above-mentioned problems, and includes an envelope made of a laminate of cefmic sheets, and a recess formed in the laminate to house an electronic component body and form external electrodes. It is something.

実施例 以下に、本発明を第1図乃至第20図から掴1明する。Example The present invention will be explained in detail below with reference to FIGS. 1 to 20.

第1図において、6は第1のセラミ、Jクシ−1−で図
示例では8枚のセラミックシー)612.6b、6Cを
積層している。7は第1のセラミ、。
In FIG. 1, reference numeral 6 denotes a first ceramic, J comb 1-, in which eight ceramic sheets 612.6b and 6C are laminated. 7 is the first cerami.

クシ−トロの最上K・76tの上面中央部より一側端に
向かって形成1〜だ第1の導電膜、8は中央部に透孔9
を有する第2のセラミックシートで図示例では同径の透
孔を有する5枚のセラミックシート8a、8b、8C1
Bd、Beを積層している。
A first conductive film 1 to 8 is formed from the center of the upper surface of the K.76t toward one side edge, and 8 is a through hole 9 in the center.
In the illustrated example, there are five ceramic sheets 8a, 8b, 8C1 having through holes of the same diameter.
Bd and Be are laminated.

10は両端に電極1 ’Oa、10bを有する電子部品
本体、図示例ではダイオードベレットで、第2のセラミ
ックシート8の透孔9により形成された凹部に一方の電
極(図示例では電極10a)を第1の導電膜7に接触す
るように収容されている。
Reference numeral 10 denotes an electronic component main body having electrodes 1'Oa and 10b at both ends, which is a diode pellet in the illustrated example, and one electrode (electrode 10a in the illustrated example) is inserted into the recess formed by the through hole 9 of the second ceramic sheet 8. It is accommodated so as to be in contact with the first conductive film 7.

8′は第2のセフミックシートで、符号8で示す第2の
セラミ1.クシートの透孔9より小径の透孔9’を有し
、第2のセラミ・、クシート8上に積層されている。1
1は透孔9′で形成された凹部内に注入され電子部品本
体10の電極10bと電電的に接続した導電部材、12
は一端が導電部材11、即ち電極10bに電電的に接続
され第1の導電膜7と反対方向に延びる第2の導電膜、
13は第2のセラミックシート8′の透孔9′を閉塞す
る第3の十゛の両端部の積層面間に形成した第3の導電
膜、15iz、15bは第3の導電膜14a114bに
よりセラミックシート積層体の外面に形成した外部電極
を示す。
8' is a second cefmic sheet, which is a second ceramic sheet 1. It has a through hole 9' having a smaller diameter than the through hole 9 of the ceramic sheet, and is laminated on the second ceramic sheet 8. 1
1 is a conductive member injected into the recess formed by the through hole 9' and electrically connected to the electrode 10b of the electronic component body 10;
is a second conductive film whose one end is electrically connected to the conductive member 11, that is, the electrode 10b, and which extends in the opposite direction to the first conductive film 7;
13 is a third conductive film formed between the laminated surfaces at both ends of the third sheet 8' to close the through hole 9' of the second ceramic sheet 8'; External electrodes formed on the outer surface of the sheet laminate are shown.

第2図乃至第14図は第1図電子部品の製造方法を示す
。先ず第2図に示すように外部電極形成用の第3の導電
膜14(14a、14b)を基板16+に形成し仮焼成
する。導電膜14の形成(ば例えばスクリーン印刷法を
用いることができる。
2 to 14 show a method of manufacturing the electronic component shown in FIG. 1. First, as shown in FIG. 2, the third conductive film 14 (14a, 14b) for forming external electrodes is formed on the substrate 16+ and pre-baked. Formation of the conductive film 14 (for example, a screen printing method can be used).

そして第2図に示すように基板16士の第3の導電膜1
4士に第1のセラミリクシ−)6(Zの層を形成し仮焼
成する。この層6aはスクリーン印刷法により形成して
もよいし、所定厚さのセラミ、リフグリーンシートを用
いてもよい。そして第2図及び第3図に示す要領で導電
膜14の形成とセラミックシート6の形成を繰返し第4
図に示す積層体を得る。導電膜の厚さはセラミックシー
トの厚さに比して十分薄いが、図示例では導電膜の厚さ
を強調して示している。
Then, as shown in FIG. 2, the third conductive film 1 on the substrate 16 is
A first ceramic layer 6 (Z) layer is formed on the 4 layers and pre-fired. This layer 6a may be formed by a screen printing method, or a ceramic or ref green sheet of a predetermined thickness may be used. Then, the formation of the conductive film 14 and the formation of the ceramic sheet 6 are repeated in the manner shown in FIGS.
The laminate shown in the figure is obtained. Although the thickness of the conductive film is sufficiently thin compared to the thickness of the ceramic sheet, the illustrated example emphasizes the thickness of the conductive film.

そI〜て第5図に示すように第1の導電膜7を最上層の
シート6C上に形成して仮焼成する。そして透孔9を有
する第2のセラミックシート8aを積層しく第6図参照
)仮焼成する。この第2のセラミ”Jクシ−1・8に対
し導電膜14(14a、14b)の形成作業とセブミミ
クシート債層作業を繰返し、第7図に示すように透孔9
で形成された複数の有底凹部を有するセラミックシート
積層体を得る。
Then, as shown in FIG. 5, a first conductive film 7 is formed on the uppermost sheet 6C and pre-baked. Then, a second ceramic sheet 8a having through holes 9 is laminated and pre-fired (see FIG. 6). The process of forming the conductive film 14 (14a, 14b) and the bonding process of the Cebu Mimic sheet were repeated for the second ceramic "J-1 and 8", and the through holes 9 were formed as shown in FIG.
A ceramic sheet laminate having a plurality of bottomed recesses is obtained.

とのセラミックシート積層体の凹部に第9図に示すよう
に電子部品本体(ダイオードベレット)10を供給する
。凹部はベレツト10が入り易(贋ようにベレット10
よりやや径大に形成されているため、凹部内のペレ、 
)位置及び向きはまちまちとなる。
As shown in FIG. 9, an electronic component body (diode pellet) 10 is supplied into the recessed portion of the ceramic sheet laminate. Beret 10 can easily fit into the recessed part (like the counterfeit, Beret 10
Because it is formed with a slightly larger diameter, the pellet inside the recess,
) The position and orientation will vary.

またペレ、ソ) 10の供給は凹部の配列パターンと同
じパターンの透孔を穿設し、下面にシャ・フタ・を有す
るベレ、ソト配列治具(図示せず)を用い複数のベレッ
トを予めベレツト配列治具に配列させ、このベレットを
複数個一括して供給することができる。
In addition, for supplying Pellet (S) 10, holes with the same pattern as the arrangement pattern of the concave portions are drilled, and a plurality of pellets are prepared in advance using a Pellet and Soto arrangement jig (not shown) having a shaft and a lid on the bottom surface. A plurality of pellets can be supplied at once by arranging them on a pellet arranging jig.

この後、第10図に示すように、第2のセラミックシー
ト8の透孔9より小径の透孔9′を有するセラミックシ
ート8′を積層し、電子部品本体10の電m1obが露
呈する凹部を形成する。この透孔9′の径は図示例のよ
うにベレツト10が凹部内でどのよう々位置にあっても
ベレツト10の上面−l〇 − 周辺部を覆う大きさに形成される。
After that, as shown in FIG. 10, a ceramic sheet 8' having a through hole 9' with a diameter smaller than that of the through hole 9 of the second ceramic sheet 8 is laminated to form a recess where the electric current m1ob of the electronic component body 10 is exposed. Form. As shown in the illustrated example, the diameter of the through hole 9' is formed to be large enough to cover the upper surface -10- of the beret 10 no matter where the beret 10 is located within the recess.

なお、図示例では第2のセラミ1.クシート8′の透孔
9内に食み出した皿部分9a′が平坦になっているが実
際には皿部分9a′は凹部内に垂れ下る状態となり、ベ
レ/ l−10の上面に密着乃至近接する。
In the illustrated example, the second ceramic 1. The plate portion 9a' protruding into the through hole 9 of the seat 8' is flat, but in reality, the plate portion 9a' hangs down into the recess and comes into close contact with the top surface of the beret/l-10. be in close proximity.

従って第2のセラミックシート8の一枚当りの厚さや積
層数はベレ、y ) 10の厚みにより決められ、セラ
ミックシート8の積層厚σがペレ、ソト1゜の厚さとほ
ぼ等しくなるように設定することにより、シートの孔9
′近傍での皿部分の変形を小さくできる。
Therefore, the thickness of each second ceramic sheet 8 and the number of laminated layers are determined by the thickness of the second ceramic sheet 8, and the laminated thickness σ of the ceramic sheet 8 is set to be approximately equal to the thickness of the second ceramic sheet 8, which is 1°. By doing so, the holes 9 in the sheet
The deformation of the plate portion near ′ can be reduced.

次いで、第11図に示すように透孔9′にロウ材(導電
部材)11′を供給する。この供給もベレ・ソトlOと
同様にして配列治具を用い複数個同時にできる。そして
赤外線加熱装置等の加熱手段によりロウ材11′を溶融
する。
Next, as shown in FIG. 11, a brazing material (conductive member) 11' is supplied to the through hole 9'. This supply can also be carried out at the same time using an arrangement jig in the same manner as the Bere-Soto IO. Then, the brazing material 11' is melted by heating means such as an infrared heating device.

この後、第12図に示すように、導電部材11に接続さ
れ第1の導電膜7と反対方向に延びる第2の導電膜を形
成する。
Thereafter, as shown in FIG. 12, a second conductive film connected to the conductive member 11 and extending in the opposite direction to the first conductive film 7 is formed.

そしてこの第2のセブミノクシート8′上に第3のセラ
ミ1.クシ−)18を積層し、積層体の上面に外部電極
形成用の導電膜を形成して複数の電子部品本体を収容し
た積層体17を得る。(第13図参照)々お、同図には
外面に露出する導電膜を図示省略している。
Then, on this second Sebuminoku sheet 8', a third ceramic 1. A conductive film for forming external electrodes is formed on the upper surface of the laminate to obtain a laminate 17 containing a plurality of electronic component bodies. (See FIG. 13) Furthermore, the conductive film exposed on the outer surface is not shown in the same figure.

そしてこの積層体を第3の導電膜を2分割する位置(第
13図一点鎖線で示す位置)から切断し、個々の電子部
品構成体17′(第14図参照)を得、これを焼結する
Then, this laminate is cut from the position where the third conductive film is divided into two (the position shown by the dashed line in Fig. 13) to obtain individual electronic component structures 17' (see Fig. 14), which are sintered. do.

そして外面に露呈E〜だ導電1fH4a、14/)に半
田による外部電極を形成、第1図に示す電子部品を得る
Then, external electrodes are formed by soldering on the conductive parts E~1fH4a, 14/) exposed on the outer surface to obtain the electronic component shown in FIG.

而の一端から各層毎に交互に他端側に延び遊端部ば第2
0図に示すようにコンデンサCを並列接続した電子部品
(ダイオード)Diが得られる。
The second end extends alternately from one end to the other end for each layer.
As shown in Figure 0, an electronic component (diode) Di is obtained in which a capacitor C is connected in parallel.

尚、本発明は上記実施例にのみ限定されるものではなく
、例えば電子部品本体10はダイオードだけでなく両面
に電極を有するものであれば何にでも適用できる。
It should be noted that the present invention is not limited to the above-mentioned embodiments; for example, the electronic component main body 10 can be applied not only to a diode but also to anything that has electrodes on both sides.

壕だ、電子部品本体lOとしてバンプ電極10bを形成
したものだけでなく、平坦な電極を有するものでもよい
In addition to forming the bump electrode 10b as the electronic component main body 10, it is also possible to use a flat electrode.

−また導電部材11は半田だけで々く、導電性樹脂を用
いることができ、ディヌベンサヲ用いて供給したり、ス
クリーン印刷法により供給することもできる。
- In addition, the conductive member 11 can be made of not only solder, but also a conductive resin, and can also be supplied by using a metal wire or by a screen printing method.

−また導電部材11を供給する前に第2の導電膜12を
形成しておくこともできるし、第2の導電い。
-Also, the second conductive film 12 can be formed before supplying the conductive member 11, or the second conductive film 12 can be formed before supplying the conductive member 11.

さらには、セラミック層はセラミックシート順次積層す
るだけではなく、第1・第2・第3のセラミンクシート
(中間セラミック層及び一対のセラミック層)をそれぞ
れ予め板状に形成1−でおき、これを電子部品本体の耐
熱温度より低い温度で接合可能なフリットを用いて一体
化するようにしてもよい。
Furthermore, the ceramic layer is not only formed by sequentially laminating ceramic sheets, but also by forming first, second, and third ceramic sheets (an intermediate ceramic layer and a pair of ceramic layers) into a plate shape in advance. They may be integrated using a frit that can be joined at a temperature lower than the heat resistance temperature of the electronic component body.

効果 本発明によれば、部品本体の電極が直接的に外装部外面
に導出され、また外部電極も外装部外面に直接的に形成
されるため小型の電子部品が実現できる。
Effects According to the present invention, since the electrodes of the component body are directly led out to the outer surface of the exterior part, and the external electrodes are also formed directly on the outer surface of the exterior part, it is possible to realize a small electronic component.

1だ製造装置としてスクリーン印刷装置や加熱装置が必
要であるが、同じ様な操作を複数回繰返す単純な作業で
あり、治具に対して目合せすれば数百乃至数万個の電子
部品に対して一括して位置合せができるため製造が容易
で、製品のばらつきも抑えることができる。
Screen printing equipment and heating equipment are required as manufacturing equipment, but it is a simple process that involves repeating the same operation multiple times, and by aligning the jig, hundreds to tens of thousands of electronic components can be produced. However, since alignment can be performed all at once, manufacturing is easy and product variations can be suppressed.

才だ、コンデンサを並列I妾続1−だ小型の電子部品が
実現できる。
By connecting capacitors in parallel, small electronic components can be realized.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明による電子部品の一例を示す側断面図、
第2図乃至第14図は第1口重1子部品の製造方法を説
明するだめの図面で、第2図乃至第3図及び第10図乃
至第12図は部分側断面図、第9図は部分平面図、第1
3図は部分11111而図、第14図は斜視図を示す。 −1だ第15図は本発明の他の実施例を示す側断面図、
第16図乃至第19図は第15図電子部品の導電膜のパ
ターンを示す断面図、第20図は第15図電子部品の等
何回路、第21図は電子部品の従来例を示す側断面図、
第22図は第21図電子部品の製造に用いられるリード
フレームの一部斜視図を示す。 6・・・・・・・・・・・・・・・・・・第1のセラミ
ックシート、7・・・・・・・・・・・・・・・・・・
・・・第1の導電膜、8・・・・・・・・・・・・・・
・ ・第2のセラミックシート、9・・・・・・・・・
・・・・・・・・透孔、lO・・・・・・・・・・・・
・・・電子部品本体、10a、10b・・・・・・電極
、 12・・・・・・・・・・・・・・第2の導電膜、13
・聞・第2のセ@           献 N               K>昧      
  賊 手続補正書(方式) (特許庁審査官       殿) 1、事件の表示 昭和59年特 許 願第231656号2、発明の名称 電子部品及びその製造方法 3、捕市をする者 事件の関係 特許出願人 〒520滋賀県大津市晴嵐2丁目9番1号関西日本電気
株式会社 4、補正命令の日付 昭和60年 2月26日 5、補正の対象 出願時提出の明細書並びに図面 7、理由 (+)第5頁下から第4行の「第21図」を「第20図
」に訂正する。 (2)第6頁第5行の「第22図」を「第21図」に訂
正する。 (3)第7頁第10行の「第20図」を「第19図」に
訂正する。 (4)第3頁第4行の「セラミックシート」の後に「の
一部を構成する厚み調整用セラミックシート」を挿入す
る。 (5)第3頁下から第2行の「第14図」を「第13図
」に訂正する。 (6)第9頁第4行の「第2図」を「第3図」に訂正す
る。 (7)第9頁下から第2行の「セラミミク」を「セラミ
ック」に訂正する。 (8)第10頁第3行の「第9図」を「第3図」に訂正
する。 (9)第10頁下から第6行の「第10図」を「第9図
」に訂正する。 (10)第11頁下から第3行の「第11図」を「第1
0図」に訂正する。 (II)第11頁下から第3行の「第12図」を「第1
1図」に訂正する。 (+2)第11頁下から第1行の「導電膜」の後に「1
2」を挿入する。 (13)第12頁第4行乃至第5行の「第13図」を「
第12図」に訂正する。 (+4)第12頁第3行の「第13図」を「第12図」
に訂正する。 (15)第12頁第3行の「・・・切断し、」の後に「
第13図に示すように」を挿入する。 (16)第12頁下から第7行の「第15図」を「第1
4図」に訂正する。 (17)第12頁下から第6行乃至第5行の「第16図
乃至第19図」を「第15図乃至第18図」に訂正する
。 (18)第13頁第1行の「第20図」を「第19図」
に訂正する。 (19)第15頁第2行乃至第12行の「第2図〜を示
す。」を「第2図乃至第13図は第1図電子部品の製造
方法を説明するための図面で、第2図乃至第7図及び第
9図乃至第11図は部分側断面図、第3図は部分平面図
、第12図は部分側面図、第13図は斜視図を示す。ま
た第14図は本発明の他の実施例を示す側断面図、第1
5図乃至第18図は第14図電子部品の導電パターンを
示す断面図、第19図は第14図電子部品の等価回路、
第20図は電子部品の従来例を示す側断面図、第21図
は第20図電子部品の製造に用いられるIJ−ドフレー
ムの一部斜視図を示す。」に訂正する。 (20)図面中第5図を別添のとおりに訂正する。 (2I)図面中第3図乃至第22図を別添図面朱記のと
おりに訂正する。 〜壷     科      − 法        眼         ()(載 −952へ− a4i    口1 派        法
FIG. 1 is a side sectional view showing an example of an electronic component according to the present invention;
Figures 2 to 14 are preliminary drawings for explaining the manufacturing method of the first mouth part, and Figures 2 to 3 and Figures 10 to 12 are partial side sectional views, and Figure 9. is a partial plan view, the first
3 shows a partial view of the portion 11111, and FIG. 14 shows a perspective view. -1 Figure 15 is a side sectional view showing another embodiment of the present invention;
16 to 19 are cross-sectional views showing the pattern of the conductive film of the electronic component shown in FIG. 15, FIG. 20 is a cross-sectional view showing the circuit of the electronic component shown in FIG. figure,
FIG. 22 shows a partial perspective view of a lead frame used for manufacturing the electronic component shown in FIG. 21. 6・・・・・・・・・・・・・・・・・・First ceramic sheet, 7・・・・・・・・・・・・・・・・・・
...First conductive film, 8...
・ ・Second ceramic sheet, 9・・・・・・・・・
......Through hole, lO...
. . . Electronic component body, 10a, 10b . . . Electrode, 12 . . . Second conductive film, 13
・Listen・Second Section @ Present N K>Madashi
Amendment to the procedure for plagiarism (formality) (To the Japan Patent Office Examiner) 1. Indication of the case Patent Application No. 231656 of 1982 2. Name of the invention Electronic parts and method for manufacturing the same 3. Related to the arrestee case Patent Applicant: 2-9-1 Seiran, Otsu City, Shiga Prefecture 520 Kansai NEC Corporation 4 Date of amendment order February 26, 1985 5 Specification and drawings submitted at the time of filing subject to amendment 7 Reasons ( +) Correct "Figure 21" in the fourth line from the bottom of page 5 to "Figure 20." (2) Correct "Figure 22" on page 6, line 5 to "Figure 21." (3) Correct "Figure 20" on page 7, line 10 to "Figure 19." (4) Insert "ceramic sheet for thickness adjustment forming a part of" after "ceramic sheet" on page 3, line 4. (5) Correct "Figure 14" in the second line from the bottom of page 3 to "Figure 13." (6) Correct “Figure 2” on page 9, line 4 to “Figure 3.” (7) Correct "ceramimic" in the second line from the bottom of page 9 to "ceramic". (8) Correct "Figure 9" in line 3 of page 10 to "Figure 3." (9) Correct "Figure 10" in the 6th line from the bottom of page 10 to "Figure 9." (10) Change “Figure 11” in the third line from the bottom of page 11 to “1
Corrected to ``Figure 0''. (II) Change “Figure 12” in the third line from the bottom of page 11 to “1
Corrected to ``Figure 1''. (+2) “1” after “conductive film” in the first line from the bottom of page 11
Insert "2". (13) Change “Figure 13” from line 4 to line 5 on page 12 to “
Figure 12 has been corrected. (+4) Change “Figure 13” on page 12, line 3 to “Figure 12”
Correct. (15) On page 12, line 3, after “…cut,” “
Insert "as shown in FIG. (16) Change “Figure 15” in line 7 from the bottom of page 12 to “1
Corrected to ``Figure 4''. (17) "Figures 16 to 19" in lines 6 to 5 from the bottom of page 12 are corrected to "Figures 15 to 18." (18) Change “Figure 20” in the first line of page 13 to “Figure 19”
Correct. (19) In lines 2 to 12 of page 15, "Figure 2 shows..." was changed to "Figure 2 to 13 are drawings for explaining the method of manufacturing the electronic component shown in Figure 1. 2 to 7 and 9 to 11 are partial side sectional views, FIG. 3 is a partial plan view, FIG. 12 is a partial side view, and FIG. 13 is a perspective view. Side sectional view showing another embodiment of the present invention, first
5 to 18 are cross-sectional views showing conductive patterns of the electronic component shown in FIG. 14, FIG. 19 is an equivalent circuit of the electronic component shown in FIG. 14,
FIG. 20 is a side sectional view showing a conventional example of an electronic component, and FIG. 21 is a partial perspective view of an IJ-hard frame used for manufacturing the electronic component shown in FIG. ” is corrected. (20) Figure 5 of the drawings will be corrected as attached. (2I) Figures 3 to 22 in the drawings are corrected as indicated in red on the attached drawings. ~Urban Ka-Ho Eye () (to 952)-a4i Mouth 1 School Ho

Claims (11)

【特許請求の範囲】[Claims] (1)中央部に透孔を有する中間セラミック層の透孔内
に、両端に電極を有する電子部品本体を収容し、中央部
より互に反対方向の端部に導電膜を形成した一対のセラ
ミック層にて中間セラミック層の開口端を閉塞すると共
に電子部品本体の電極と導電膜とを電気的に接続し、各
導電膜に電気的に接続された外部電極を形成したことを
特徴とする電子部品。
(1) A pair of ceramics in which an electronic component body having electrodes at both ends is accommodated in the hole of an intermediate ceramic layer having a hole in the center, and a conductive film is formed at the ends in opposite directions from the center. An electronic device characterized in that the layer closes the open end of the intermediate ceramic layer and electrically connects the electrode of the electronic component body to the conductive film, forming an external electrode electrically connected to each conductive film. parts.
(2)前記セラミック層はセラミックシートの積層体に
より構成したことを特徴とする特許請求の範囲第1項記
載の電子部品。
(2) The electronic component according to claim 1, wherein the ceramic layer is constituted by a laminate of ceramic sheets.
(3)前記セラミックシートの積層体の端部積層間に外
部電極形成用の導電膜を形成し外部電極と接続するよう
にしたことを特徴とする特許請求の範囲第2項記載の電
子部品。
(3) The electronic component according to claim 2, characterized in that a conductive film for forming an external electrode is formed between the end laminations of the ceramic sheet laminate and connected to the external electrode.
(4)前記外部電極形成用の導電膜はセラミックシート
の積層面の一端部近傍から各層毎に交互に他端部側に延
び遊端部乃至中間部がセラミックシートを介して対向し
コンデンサを形成させるようにしたことを特徴とする特
許請求の範囲第3項記載の電子部品。
(4) The conductive film for forming the external electrode extends alternately from near one end of the laminated surface of the ceramic sheet to the other end for each layer, and the free ends or intermediate portions face each other with the ceramic sheet interposed therebetween to form a capacitor. The electronic component according to claim 3, characterized in that the electronic component is configured to cause
(5)前記各セラミック層間をフリットにて接続したこ
とを特徴とする特許請求の範囲第1項記載の電子部品。
(5) The electronic component according to claim 1, wherein the ceramic layers are connected by a frit.
(6)次の各工程(ア)〜(ケ)を含むことを特徴とす
る電子部品の製造方法。 (ア)基板上に方形乃至矩形状の第1のセラミックシー
トを1層以上積層する工程、 (イ)第1のセラミックシートの上面に第1の導電膜を
形成する工程、 (ウ)第1のセラミックシート上に、複数の透孔を整列
状態で形成した第2のセラミックシートを複数層積層す
る工程、 (エ)第2のセラミックシートの透孔で形成された凹部
内に電子部品本体を供給する工程、 (オ)第2のセラミックシートの最上層に第2の導電膜
を形成すると共に第2の導電膜を電子部品の電極と電気
的に接続する工程、 (カ)第2のセラミックシート上に、第3のセラミック
シートを1層以上積層する工程、 (キ)第1乃至第3のセラミックシート積層体の透孔間
を切断して小セラミック積層体に分割する工程、 (ク)小セラミック積層体を焼結する工程、 (ケ)小セラミック積層体に外部電極を形成する工程。
(6) A method for manufacturing an electronic component, characterized by including the following steps (a) to (k). (A) Step of laminating one or more square or rectangular first ceramic sheets on a substrate, (B) Step of forming a first conductive film on the upper surface of the first ceramic sheet, (C) First laminating a plurality of layers of a second ceramic sheet in which a plurality of through holes are formed on the ceramic sheet; (d) placing an electronic component body in a recess formed by the through holes in the second ceramic sheet; (e) a step of forming a second conductive film on the top layer of the second ceramic sheet and electrically connecting the second conductive film to an electrode of an electronic component; (f) a second ceramic sheet; a step of laminating one or more layers of a third ceramic sheet on the sheet; (g) a step of dividing the first to third ceramic sheet laminates into small ceramic laminates by cutting between the holes; A process of sintering the small ceramic laminate; (e) A process of forming external electrodes on the small ceramic laminate.
(7)上記セラミックシートはスクリーン印刷法により
形成することを特徴とする特許請求の範囲第6項記載の
電子部品の製造方法。
(7) The method of manufacturing an electronic component according to claim 6, wherein the ceramic sheet is formed by a screen printing method.
(8)上記セラミックシートは予めシート状に形成され
たシートを用いることを特徴とする特許請求の範囲第6
項記載の電子部品の製造方法。
(8) Claim 6, characterized in that the ceramic sheet is a sheet formed in advance into a sheet shape.
2. Method for manufacturing electronic components described in Section 1.
(9)上記電子部品本体の電極と導電膜の接続は導電性
接着剤により行うことを特徴とする特許請求の範囲第6
項記載の電子部品の製造方法。
(9) Claim 6, characterized in that the electrode of the electronic component body and the conductive film are connected by a conductive adhesive.
2. Method for manufacturing electronic components described in Section 1.
(10)次の各工程(ア)〜(キ)を含むことを特徴と
する電子部品の製造方法。 (ア)第1のセラミック板上の所定位置に所望パターン
の第1の導電膜を複数形成する工程、 (イ)第1のセラミック板の第1の導電膜の一端部に対
応する位置に透孔を穿設した第2のセラミック板を第1
のセラミック板に積層する工程、(ウ)第1・第2のセ
ラミック板によって形成された凹部に両端に電極を有す
る電子部品本体を収容し、第1のセラミック板の第1の
導電膜と電子部品本体の一方の電極を電気的に接続させ
る工程、 (エ)第2のセラミック板の透孔と対向する位置から第
1の導電膜と反対方向に延びる所望パターンの第2の導
電膜を複数形成した第3のセラミック板にて第2のセラ
ミック板の開口端を閉塞すると共に、電子部品本体の他
の電極と第2の導電膜とを電気的に接続させる工程、 (オ)各セラミック板の接合面を気密的に接続する工程
、 (カ)各セラミック板の積層体の透孔間を切断して小セ
ラミック積層体に分割する工程、 (キ)小セラミック積層体に外部電極を形成する工程。
(10) A method for manufacturing an electronic component, characterized by including the following steps (a) to (g). (a) forming a plurality of first conductive films in a desired pattern at predetermined positions on the first ceramic plate; (b) forming a transparent film at a position corresponding to one end of the first conductive film on the first ceramic plate; A second ceramic plate with holes is inserted into the first ceramic plate.
(c) housing an electronic component main body having electrodes at both ends in the recess formed by the first and second ceramic plates, and stacking the electronic component on the first conductive film of the first ceramic plate and the electronic component body; A step of electrically connecting one electrode of the component body; (d) forming a plurality of second conductive films in a desired pattern extending in a direction opposite to the first conductive film from a position facing the through hole of the second ceramic plate; a step of closing the open end of the second ceramic plate with the formed third ceramic plate and electrically connecting the second conductive film to another electrode of the electronic component body; (e) each ceramic plate; (f) Step of cutting between the through holes of each ceramic plate laminate to divide it into small ceramic laminates; (g) Forming external electrodes on the small ceramic laminates. Process.
(11)上記各セラミック板の接合面の気密接続にはフ
リットを用いることを特徴とする特許請求の範囲第10
項記載の電子部品の製造方法。
(11) Claim 10, characterized in that a frit is used for airtight connection of the joining surfaces of each of the ceramic plates.
2. Method for manufacturing electronic components described in Section 1.
JP23165684A 1984-10-31 1984-10-31 Electronic parts and manufacture thereof Pending JPS61108153A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23165684A JPS61108153A (en) 1984-10-31 1984-10-31 Electronic parts and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23165684A JPS61108153A (en) 1984-10-31 1984-10-31 Electronic parts and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS61108153A true JPS61108153A (en) 1986-05-26

Family

ID=16926910

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23165684A Pending JPS61108153A (en) 1984-10-31 1984-10-31 Electronic parts and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS61108153A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110204521A1 (en) * 2010-02-25 2011-08-25 Inpaq Technology Co., Ltd. Chip-scale semiconductor device package and method of manufacturing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110204521A1 (en) * 2010-02-25 2011-08-25 Inpaq Technology Co., Ltd. Chip-scale semiconductor device package and method of manufacturing the same
JP2011176263A (en) * 2010-02-25 2011-09-08 Inpaq Technology Co Ltd Chip-scale semiconductor device package and method of manufacturing the same
TWI406379B (en) * 2010-02-25 2013-08-21 Inpaq Technology Co Ltd Chip scale semiconductor device package and manufacturing method thereof

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