JPS61107229U - - Google Patents

Info

Publication number
JPS61107229U
JPS61107229U JP19254984U JP19254984U JPS61107229U JP S61107229 U JPS61107229 U JP S61107229U JP 19254984 U JP19254984 U JP 19254984U JP 19254984 U JP19254984 U JP 19254984U JP S61107229 U JPS61107229 U JP S61107229U
Authority
JP
Japan
Prior art keywords
frequency
subtracting
adding twice
amplifier circuit
output level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19254984U
Other languages
English (en)
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP19254984U priority Critical patent/JPS61107229U/ja
Publication of JPS61107229U publication Critical patent/JPS61107229U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)
  • Superheterodyne Receivers (AREA)
JP19254984U 1984-12-18 1984-12-18 Pending JPS61107229U (enExample)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19254984U JPS61107229U (enExample) 1984-12-18 1984-12-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19254984U JPS61107229U (enExample) 1984-12-18 1984-12-18

Publications (1)

Publication Number Publication Date
JPS61107229U true JPS61107229U (enExample) 1986-07-08

Family

ID=30749959

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19254984U Pending JPS61107229U (enExample) 1984-12-18 1984-12-18

Country Status (1)

Country Link
JP (1) JPS61107229U (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7509106B2 (en) 2004-04-06 2009-03-24 Sony Corporation Test signal generation circuit, and reception circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7509106B2 (en) 2004-04-06 2009-03-24 Sony Corporation Test signal generation circuit, and reception circuit

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