JPS61105154A - Zero continuous suppression transmission system - Google Patents

Abstract

PURPOSE:To prevent timing information from being lost due to zero continuity without using complicated circuits by sending the check bit after inverting with an encoding circuit on the transmitting side and by decoding it after inverting on the receiving side. CONSTITUTION:On the transmitting side, switches 7 and 8 of an encoding circuit are placed in the illustrated state and 4-bit information bit is inputted from an input terminal 1 and sent from an output terminal 9, and also inputted to a dividing circuit from an exclusive OR circuit 6. After said bit is outputted from the output terminal 9, the switches 7 and 8 are reversed. At that time, the remainder of the division result held in FFs2-4 is inputted from the exclusive OR circuit 6 to an inverter 21 and the inverted check bit is sent from the terminal 9. In the decoding circuit, the switch 22 is tilted upward and of the received data blocks the first information bit is inputted and then the switch 22 is tilted downward to invert and inputted the subsequent check bit.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a continuous zero suppression transmission system that suppresses continuous zeros in a transmission code by inverting and transmitting a check code for error detection and correction.

PRIOR ART Conventionally, there have been various transmission methods in which an error correction code is sent out by adding a check code for error detection and correction to information data, and the receiving side detects errors from the received signal and corrects the error bits. It is used. Error correction codes are broadly classified into block codes and convolutional codes.

As shown in the third factor, the block code consists of k bits of information bits and n- bits of check bits (total n bits).
It consists of Let the number of information bits of bits represented by a row vector of elements be 4, and let the code word of n bits represented by a row vector of n elements be .

C=dlG・・・・・・・・・・・・・・・・・・
It can be expressed as (1). However, G is a code generation matrix, and is a matrix of rows and n columns expressed by the following equation.

G= CI[k PI ・・・・・・・・・・・・
(2) Here, lrk is the next unit matrix, and P is the row (n
-k) columns, as is clear from equations (1) and (2), the left-hand elements of the code word C are the same as the information bits dl, and the remaining right-hand elements are the same as the information bits dl. There are (n-k) elements.

This is a check bit uniquely determined by P. However, in a block code in which addition is performed by modulo-2 addition, the check bits are defined only by the information bits within one block. Furthermore, from equation (1), if all the elements of the information bit (dl) are "0", all the check bits will also be "0", and therefore all the elements of the code word C will not be "0" either. it is obvious.

In the convolutional code, check bits are generated from information bits spanning 1 m blocks, and the constraint length thereof is nm, where n is the length of 1 block. The encoding of a convolutional code with a constraint length of 1 is mk bits of information bits, a1=
”@-1a11&-□・・・・・・1 on d11d16
This is done by multiplying by a generation matrix G expressed by equation (3).

However, O is the next total zero, and station is the next unit matrix,
Pi is a matrix with (nk) rows and columns for generating check bits for the information bits of i block before.

Therefore, if all the elements of the mk-bit information bits are "O", all the elements of the 1m block code word will be 'O'. In other words, all the transmitted codes are MO'', and long consecutive zero codes are transmitted.For details of the above-mentioned encoding and decoding, see, for example, References 1w and E.

etal, ”PRIII:IPLES OF
DATA COMNUNI GATIO ".

McGraw-Hill Inc., 1988. Please refer to etc.

As an example of an encoding circuit that generates a block code, an encoding circuit for a cyclic Hamming (7, 4) code is shown in Figure 144, and a decoding circuit for the cyclic Hamming (7, 4) code is shown in Figure 5.
The code is a single-error correctable cyclic code with a code length of nx7 bits, an information bit length of 4 bits, and a check bit length of 3 bits, and has a generating polynomial G(x)wx''+x+1.

In the 4th v4, a division circuit is formed by tree flops 2 to 4 and exclusive OR circuits 5 and 6.

The 4-bit input information input from the input terminal 1 is output from the output terminal 9 through the changeover switch 7, and
The signal is input from the exclusive OR circuit 6 to the division circuit. 4
x'-8 (=X3) times the bit input information as G (x)
The remainder obtained by dividing by It is sent from output terminal 9 as . The check bits corresponding to various patterns of information hits are shown in Table 1.

Table 1 Accordingly, when all the information bits are "0", all the check bits are also "0", and the transmitted code becomes continuous.

In the decoding circuit shown in the rftJs diagram, 7-bit received data input manually from the input terminal 11 is stored in the 8-stage shift register 14, and is also input to the syndrome generation circuit 12, where the syndrome is determined. If there is an error in the received signal, the error bit position is detected by the error bit position detection circuit 13 using the syndrome output from the syndrome generation circuit 12, and the error bit output from the 8-stage shift register +4 is exclusively detected. OR circuit 15
By inverting the signal, error correction is performed and output from the output terminal 1B. It is possible to correct a 1-bit bit error by the above decoding circuit. In addition,
Regarding the configuration and operation of the syndrome generation circuit and the error bit position detection circuit, see 1, for example, Inose et al.

``Computer Course 3 Data Communication J Sanpo, 11373.'' The detailed explanation is omitted here.

As mentioned above, in the conventional error detection and correction method, when all the information bits are "0", all the check bits are also "0", so there is a drawback that the number of consecutive zeros is long.

In bipolar codes and the like that are widely used in digital transmission, if the number of consecutive zeros becomes long, it becomes impossible to extract timing from the received pulse sequence.

As a countermeasure against the zero-M series, it is possible to use a method in which the transmission code sequence is scrambled and descrambled on the receiving side, but this increases the circuit scale. Also, for example, C
There is also a method that uses a continuous zero suppression code such as an MI code, but a continuous zero suppression code.

It requires a wider transmission band than bipolar codes, and the circuits for code conversion and inverse conversion are complex.

OBJECTS OF THE INVENTION It is an object of the present invention to solve the above-mentioned conventional drawbacks and to convert jtl! of a transmission code sequence by inverting the check bits. 1m
An object of the present invention is to provide a continuous zero suppression transmission system that suppresses the error rate and improves the mark rate.

Composition of the Invention The zero consecutive suppression transmission system of the present invention includes an encoding circuit on the transmitting side that generates a check code for error detection and correction for the information code and outputs it in addition to the information code; In a transmission system equipped with a decoding circuit that performs error detection and error bit correction from a signal, the transmitting side is equipped with an inverter that inverts the output of the encoding circuit, and the check code added to the information code is inverted and sent. However, the receiving side is provided with an inverter for inverting the check code, and the check code in the received signal is inverted and inputted to the decoding circuit.

Embodiments of the Invention Next, one embodiment of the present invention will be described in detail with reference to one drawing.

FIG. 1 is a block diagram showing an encoding circuit on the transmitting side in an embodiment in which the present invention is applied to a cyclic Hamming (7,4) code, and FIG. 2 shows an example of the configuration of a decoding circuit on the receiving side. , 1st
The encoding circuit shown in the figure is constructed by inserting an inverter 21 between the exclusive OR circuit 6 and the switching contact of the changeover switch 7 of the conventional encoding circuit shown in FIG. The receiving side decoding circuit shown in FIG. 2 has a changeover switch 22 inserted between the conventional decoding circuit shown in FIG. No. 48 inputted from the input terminal 11 is inverted by the inverter 23 and inputted to the other terminal.

In the encoding circuit shown in FIG. 1, the switch 7 is turned down as shown in the figure, and with the switch 8 closed, four bits of information are input from the input terminal l, and from the output terminal 9 through the changeover switch 7. At the same time, it is also input from the exclusive OR circuit 6 to the division circuit. After the 4 information bits are output from the output terminal 9, turn the switch 8 to M.
When the selector switch 7 is turned upward, the remainder of the division result held in the flip-flops 2 to 4 is input from the exclusive OR circuit 6 to the inverter 21.

The test bits inverted by the inverter 21 are sent out from the output terminal 9 through the changeover switch 7.Table 2 shows the correspondence between the information bits of various patterns and the test bits.
Table 2 In this embodiment, when the contents of the information bits are all "0", the contents of the check bits are all "1", so zero I!
T! This has the effect of suppressing continuations and improving the mark rate. The check bits for other patterns of information bits are the inversion of the conventional check bits in Table 1. Therefore, when all the information bits are "1", all the check bits are "0", so the same effect can be obtained even in the case of negative logic.

In the decoding circuit shown in FIG. 2, first, the changeover switch 22 is turned upward to input the first 4 information bits of the 7-bit received data block input from the input terminal 11, and then the changeover switch 22 is turned upward. 22 to the lower side and the remaining three test bits are inverted and input. Therefore, since the received signal input to the syndrome generation circuit 12 and the eight-stage shift register 14 has the check bits inverted and is the same as the conventional received data, the syndrome generation circuit 12 can generate the syndrome in the same way as in the conventional case. The error bit position detection circuit 13 detects the position of the error bit based on the above syndrome, and can perform error correction in the same manner as in the prior art.

This embodiment has the advantage that even when using a code such as a hepolar code that is likely to cause loss of timing information, 'IIF continuity can be prevented without scrambling and timing can be extracted stably.

Effects of the Invention As described above, in the present invention, the encoding circuit on the transmitting side inverts the check bit before sending it out, and the receiving side inverts the check bit in the received signal before decoding. Therefore, it is possible to prevent timing information from being lost due to consecutive zeros without using a complicated circuit such as a scrambler.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a transmitting side encoding circuit according to an embodiment of the present invention, FIG. 2 is a block diagram showing a receiving side decoding circuit according to the above embodiment, and FIG. 3 is an example of a data block of a cyclic code. 4 is a block diagram showing an example of a conventional cyclic Hamming code encoding circuit, and FIG. 5 is a block diagram showing an example of a conventional decoding circuit. In the figure, ■=input terminal, 2 to 4: flip-flop, 5, 6, 15: exclusive OR circuit, 7°22: changeover switch, 8: switch, 9: output terminal, 11: input terminal,
12: Syndrome generation circuit, 13: Error bit position detection circuit, 14: 8-stage shift register, 18: Output terminal,
21, 23: Inverter.

Claims (1)

[Claims] The transmitting side is equipped with an encoding circuit that generates a check code for error detection and correction of the information code and outputs it as an additional output to the information code, and the receiving side is equipped with a decoding circuit that performs error detection and error bit correction from the received signal. In the transmission method, the transmitting side is provided with an inverter for inverting the output of the encoding circuit, and the check code added to the information code is inverted and transmitted, and the receiving side is configured to invert the check code. 1. A continuous zero suppression transmission system comprising: an inverter for inverting a check code in a received signal and inputting the inverted signal to the decoding circuit.