JPS61105152A - Information transfer circuit - Google Patents

Abstract

PURPOSE:To prevent extension of transfer circuit and signal line when divided data are transferred, by providing a means to supply buffer register idle information on the transmitting side and a means to display a receiving circuit busy and transferring the data only when the data are received immediately after the above display or when there is a reading signal. CONSTITUTION:When a transmitting circuit 2 is started, an AND circuit 9 operates and data on a signal line 3 is set to a buffer register BR10. Simultaneously a set signal 4 ignites an FF16 and informs a processor 1 that the BR10 is not idle. Then the processor 1 stops the subsequent use of the transmitting circuit 2. Also, with signal 14 delayed by t1, it transfers the data of the BR10 to an SR12 and informs a synchronizing signal line 20 of the data transfer. After t2, it resets the FF16. In the receiving circuit 22, the synchronizing signal ignites an FF30, displays that the receiving circuit is busy, and the automatic data transfer from SR23 is deterred. When an FF30 is ignited, the signal is impressed to a delay circuit 29, differentiated into a signal for delay time by an AND circuit and the data are transferred to BR43.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information transfer circuit, and particularly to a circuit that transmits and receives serial data between a plurality of control devices. This invention relates to an information transfer circuit that divides wide bit-width data into two or more times and sends and receives the data.

[Conventional technology]

Due to distributed processing and the like, different processing is often performed by a plurality of control devices. In such a case, when the processor of the first control device accesses its own memory and there is no required information therein, it transfers the address data to access the memory in the second control device. However, a method has been proposed for reading out the above information from memory (see Japanese Patent Application No. 118165/1989, ``Memory Access Control Method''). In such a case, the address data to be transferred is transmitted and received in serial form. . In addition, if the bit width of the memory in each control device is wider than the bit width of the transfer data line, the memory address data is divided into multiple pieces,
6. When data is divided into multiple blocks and serially transferred, information indicating that the data to be transferred is divided into blocks on the transmitting side.

If information identifying the block number is included, the data can be restored to the original data on the receiving side, but this increases the number of bits to be transferred and also includes information for assembling blocks into data. That amount of processing hardware is required.

2 For example, when transmitting information using serial data between processors, the transmitting side uses a signal line for serial data,
A simple method is adopted in which a synchronization signal line indicating that data has been output is sent to a clock signal line and a signal line for serial data, and the data is parallelized using these three signal lines on the reception line. However, as the bit width of data transferred between processors increases, and furthermore, when attempting to integrate these information transfer circuits into integrated circuits, it becomes necessary to divide the data into a plurality of blocks due to the limited number of terminals. In this case, it is possible to deal with this by arranging the information transfer circuits in parallel with the number of divided blocks, but this has the disadvantage that the amount of hardware and the number of input/output terminals of the processor increase. Also, only one set of information transfer circuit is provided.

This can be solved by serially dividing the block several times, but it becomes necessary to identify the beginning of the data, that is, from where to where in multiple blocks is one piece of data. The signal line at
The disadvantage is that the number of books increases.

[Purpose of the invention]

SUMMARY OF THE INVENTION In order to improve such drawbacks, an object of the present invention is to transfer data divided into multiple blocks between multiple control devices without arranging transfer circuits in parallel for the number of blocks.
Another object of the present invention is to provide an information transfer circuit that can reduce the amount of hardware without adding additional signal lines.

[Structure of the invention]

In order to achieve the above object, the information transfer circuit of the present invention is an information transfer circuit that divides data having a width of multiple bits into two or more times and transmits and receives the data serially, comprising: a control means for supplying buffer register empty information; a transmitting circuit including a first buffer register that stores data from the outside according to the free space information; and a first shift register that serially converts the data from the first buffer register and outputs the data; means for indicating that the receiving circuit is in use in synchronization with a clock, a second shift register for receiving transfer data, and whether the data received by the second shift register is immediately after the receiving circuit in use indication; ,
or only when there is a buffer register read signal,
The present invention is characterized in that it includes a receiving circuit including means for transferring data in the second shift register to a second buffer register.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 1 and 2 are block diagrams of a transmitting circuit and a receiving circuit, respectively, showing an embodiment of the present invention.

In FIG. 1, numeral 1 denotes a processor in a control device on the transmitting side, which controls a transmitting circuit and a receiving circuit.

2 is a transmission circuit, 3 is a signal line that supplies transmission data from the processor 1 to the transmission circuit, 4 is a set signal line that sets data to the buffer register in the transmission circuit 2, and 5 is a signal line in the buffer register in the transmission circuit 2. A signal line for sending data to the shift register and indicating that it is empty; 7 is a resonant circuit for generating a clock for serial data sent from the transmitting circuit; 6 and 8 are its input/output signal lines; 9 is an AND circuit for setting data into the buffer register,
10 is a buffer register for temporarily storing data sent from the processor and transmitting the data to the shift register after checking for free space in the shift register; 11 is an AND circuit for setting data to the shift register; 12 is a data 13 is a delay circuit that delays the set signal received from the processor, 14.15 is the output signal line of the delay circuit, which is delayed by t1 time from the set signal to 14. A signal is generated on the signal line 15 with a delay of tz (tt<tz) time. 16 is a flip-prop that remembers that the rose register is in use (lid closed);

17 generates a clock for serial data transfer.

The distribution circuit 18 is activated by the signal line 14 through which data is set to the shift register, and the signal line A synchronization signal is sent to 20. 19 is a signal line that supplies the serial data shifted out from the shift register to the receiving circuit, 20 is a signal line through which a synchronization signal flows, 21 is a signal line through which a clock signal always flows, and 19 to 21 are the receiving circuit 2.
2 is connected. In the receiving circuit 22, 23 is a shift register that receives serial data, shifts it, and converts it into parallel data, and 24 is a shift register 2 that receives serial data, shifts it, and converts it into parallel data.
a clock generation circuit that generates a clock for shifting 3;
25 is an AND circuit for setting the data received by the shift register to the buffer register 43; 26.27
28 is a delay circuit for delaying the signal on the signal line 39; 29 is a delay circuit for differentiating the signal on the flip-flop 29; 30 is a transmission circuit. A flip-flop circuit 31 is set by the synchronization signal 20 sent from the circuit 2 to indicate that the receiving circuit is in use, and 31 suppresses the buffer register readout signal 39 that is first generated when the flip-flop 30 in use of the receiving circuit is fired. In other words, when data is divided into a plurality of blocks and transmitted, the first block is transferred from the shift register 23 to the buffer register 43.
It is a flip-flop to ensure the transfer to 3.
2 is a flip-flop in which the data sent from the transmitting circuit 2 is stored in the shift register 23, and stores a command to the processor 40 to read the buffer register; This is a flip-flop that operates according to a clock signal, and data is set when the clock changes in the direction of the arrow. 36 is an OR circuit; 37 is a flip-flop 33 that receives the clock sent from the processor;
A clock supply circuit that supplies the clock to ~35, 3
8 is a clock signal line; 39 is a buffer register read signal line for instructing the transfer of data in the shift register 23 to the buffer register 43; 40 is a signal line for notifying the processor 42 that data has been set in the shift register 23; 41 is a signal line for notifying the processor 42 that data has been set in the shift register 23; This is a signal line that sends the contents of the buffer register to the processor 42.

When the processor 1 transfers data to the processor 42, the signal line 5 becomes logic II 01', confirms that the buffer register IO is empty, outputs the data to be sent to the processor 3, and transfers the data to the signal line 4. The transmitter circuit 2 is activated by sending a buffer register set signal to the buffer register set signal. As a result, the AND circuit 9 operates, and the data on the signal line 3 is set into the buffer register 10. At the same time, the set signal 4 is supplied to the flip-flop 16, igniting the flip-flop 16 and notifying the processor l via the signal line 5 that the buffer register is not empty. As a result, processor l stops using the next transmitting circuit 2. Further, the set signal 4 is supplied to the delay circuit 13, and when time t1 has elapsed, it is output to the signal line 14 to operate the AND circuit 11.
When the data in the buffer register 10 is transferred to the shift register 12 and the shift register 12 is activated, the counter circuit I8 is activated at the same time, and a signal #I9 is sent to the synchronization signal line 20 to indicate that serial data has been sent.

When 12 hours have elapsed, it is output to the signal line 15, resets the flip-flop 16, and indicates to the processor l that the buffer register 10 is empty.

This allows the processor l to send the next data to the transmitting circuit 2. The clock oscillation circuit 17 constantly outputs a clock for serial data transfer, and this signal is supplied to the receiving circuit 22 through the clock signal line 21 and also to the counter circuit 18 . shift register 1
It also supplies to 2. When a signal is applied to the output signal line 14 of the delay circuit 13, the shift register 12 starts a shift operation according to the clock signal 17, and the shifted out serial data is sent to the signal line 19. The counter circuit also has a bit width of 17 in the shift register 12.
, and sends a message to that effect to the synchronization signal line 20 during counting.

With this configuration, on the transmitting side, the processor 1 can output the data to be sent to the signal line 3 when the signal line 5 indicates that the buffer register is empty.

The receiving circuit 22 includes a clock signal line 21 and a synchronization signal line 20.
The clock generation circuit 24 generates a clock to be supplied to the reception shift register 23 based on Therefore, the serial data signal on signal line 19 is shifted to a shift register. The signal is shifted and inputted by the star 24 and converted into parallel data.

The flip-flop 30 is fired by the synchronization signal 20 to indicate that the receiving circuit is in use, and the flip-flop 30 is not reset until the clock supplied from the processor changes from rising to falling to rising. From the shift register 23 to the buffer 7, which will be described later.
Automatic data transfer to register 43 is inhibited. That is, when data is divided into a plurality of blocks and sent from the processor 1, the transfer of the first block of data from the shift register 23 to the buffer register 43 is automatically performed by the differential signal of the flip-flop 30. , notifying processor 42 that the data has been received;
Thereafter, data is not transferred from the shift register 23 to the buffer register 43 unless the processor 42 sends a buffer read signal.

When the blip prop 30 is ignited, the signal is applied to the 11 delay circuit 29, and the AND circuit 27 differentiates it into a signal corresponding to the delay time. This signal is applied to the AND circuit 25 through the OR circuit 36, transfers the data in the shift register 23 to the buffer register 43, and at the same time resets the flip-flop 31. The flip-flop 32 is set synchronously through the synchronization signal line 20, and the processor 42 is notified through the signal line 40 that data has been set in the shift register 23. This signal causes processor 4
2 activates the signal line 39 and instructs transfer from the shift register 23 to the buffer register 43.

However, since the flip-flop 31 is not lit during the first block, the AND circuits 26 and 25 do not operate.
The data set by the signal 27 is sent to the processor 42 through the signal line 41.

The signal line 39 resets the flip-flop, and the delay circuit 28 delays the signal, causing the flip-flop 31 to fire. By igniting flip-flop 31,
While the flip-flop 30 is firing, data transfer from the shift register 23 to the buffer 7 register 43 is controlled by the signal line 39.

When the data of the next block is transferred from the processor 1, the synchronizing signal line 20 causes the flip-flop 32 to fire at the same time as the data on the signal line 19 is taken into the shift register as described above.

Processor 42 is notified via signal line 40 that data has been received in the shift register. The processor 42 thereby sends out a read signal via the signal line 39,
While resetting the flip-flop 32, the AND circuit 26. The OR circuit 36 and the AND circuit 25 are operated, and the data in the shift register 23 is transferred to the buffer register 43.
Transfer to.

In the above, the transmitting circuit 2 and the receiving circuit 22 were described as separate circuits, but since both circuits have many common parts, they are provided as a transmitting circuit and can be used externally for transmitting and receiving. There's no need to explain.

Because of this configuration, when a time interval is set according to the clock 38 from the processor, and one data is divided into multiple blocks from the transmitting side and transmitted within one time interval, the data in the first block is AND circuit 27
This makes it possible to automatically transfer data from the shift register 23 to the buffer register 43, and there is no need to constantly monitor that data has been set in the shift register 23 on the receiving side. Especially when the number of block divisions is 2.
In this case, there is an advantage that the processor 42 does not need to pay attention to the timing of the second block data read command.

Note that when reading memory between processors, the information transfer circuit may be required to operate at high speed, and in such a case, for example, the logic circuit needs to be an ECL. If one of the processors is configured using TTL, a level conversion circuit is required between the processor and the information transfer circuit, and if the information transfer circuits are installed in parallel as many times as the number of block divisions.

Although the number of level conversion circuits will increase, according to this embodiment, only one set of level conversion circuits may be provided.

〔Effect of the invention〕

As explained above, according to the present invention, there is no need to add signal lines between processors, and information transfer circuits can be divided into blocks in parallel! ! 2. Data divided into a plurality of blocks between the transmitting and receiving circuits can be read out as a single piece of data without the need to do so and without increasing the amount of hardware in the processor.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a transmitting circuit showing one embodiment of the present invention, and FIG. 2 is a block diagram of a receiving circuit showing one embodiment of the present invention. 1.42: Processor, 10.43: Buffer register, 12.23: Shift register, 17°24: Clock generation distribution circuit, 18: Count circuit, 13, 28, 29
: Delay circuit, 37: Clock supply circuit, 16, 30, 3
1, 32, 33, 34° 35: Flip-prop. Figure WJ1] Figure 2

Claims (1)

[Claims] (1) In an information transfer circuit that divides multi-bit width data into two or more times and serially transmits and receives the data, there is a control means for supplying buffer register free information, and data from the outside is stored according to the free space information. Displays whether a transmitter circuit including a first buffer register and a first shift register that serially converts data from the first buffer register and outputs the data, and a receiver circuit in use in synchronization with an externally supplied clock. a second shift register for receiving transfer data; and a second shift register for receiving transfer data; 1. An information transfer circuit comprising: a receiving circuit including means for transferring data in a second shift register to a second buffer register.