JPS61104387A - Magnetic bubble memory control device - Google Patents

Abstract

PURPOSE:To shorten the time when a CPU is possessed exclusively by a magnetic bubble memory control device by making a host CPU monitor a data end flag bit generated at the time when a data transfer is ended. CONSTITUTION:A flag bit of a status register 8 of a controller 3 becomes effective, when write and read-out of a magnetic bubble memory device 7 can be executed, and a data is transferred between a host CPU2 and the device 7. In this register 8, a data end flag bit which is generated as soon as the data transfer is ended is also stored, and this bit is monitored by the CPU2. Accordingly, the time when the host CPU is possessed exclusively by the magnetic bubble memory control device is shortened to the necessary minimum time.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a magnetic bubble memory control device, and more particularly, to a magnetic bubble memory control device that releases a CPU from a magnetic bubble memory device immediately upon completion of data transfer. Regarding equipment.

[Conventional technology]

The conventional magnetic bubble memory control method will be explained with reference to the time chart of FIG. In FIG. 5, time 1. Before the magnetic bubble memory controller was READY.
) state, and the busy (BUSY) signal of bit O of the status register STR is "0". Time t
When the command is set in , the busy signal becomes “1”
Switch to time 1. The magnetic bubble device is accessed between and t2. Data transfer between the host CPU and the magnetic bubble memory device then takes place between times t2 and t. When the data transfer ends at time t, post-processing for a so-called seek operation is performed at time t, which moves the bubble to the next position to be accessed in response to the command set at time t1.

When the post-processing is completed at time t4, which is performed between 0 and t4, the command end signal of bit 7 of the status register STR switches to 11'', and the processing of the command set at time 1 ends.

[Problems to be solved by the invention] According to the above-mentioned conventional technology, even though the data transfer has ended at time t, the host CPU confirms that the command end signal has switched to “1”. Since no other processing can be performed until this is done, there is a problem that the CPU (host) is occupied exclusively by the magnetic bubble memory control device for a long time.

[Means for solving problems]

In order to solve the above problems, the present invention provides a host CPU, a magnetic bubble memory device, a write enable signal generated when writing to the magnetic bubble memory device is possible, and a magnetic bubble memory. a status register that stores flag bits including at least a read enable signal generated when reading from the device is possible; and a controller that controls data transfer between the host CPU and the magnetic bubble memory device based on the flag bits. The magnetic bubble memory control device further includes a data end flag bit generated in response to the end of data transfer.

The data end flag bit is stored in an area that stores the status register's read valid signal when writing data to the magnetic bubble memory device, and stores the status register's write valid signal when reading from the magnetic bubble memory device ends. It is preferable to store it in

Further, the data end flag bit can be generated in response to a count end signal of a counter that counts the number of successive read/write bits output from the host CPU in synchronization with the read/write timing of each bit. preferable.

[For production]

As soon as the host CPU detects the data end flag bit, it is released from controlling the magnetic bubble memory device and can move on to executing other processes, so the time that the host CPU is exclusively occupied by the magnetic bubble memory control device is shortened. .

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram schematically showing the overall configuration of a magnetic bubble memory control device according to the present invention. In the figure, the magnetic bubble memory control device 1 is connected to a host CP, as is well known.
It includes U2, a controller 3, a coil driver 4, a function driver 5, a sense amplifier 6, and a magnetic bubble memory device 7. The controller 3 has a status register 8 for storing flag bits indicating the state of control over the magnetic bubble memory device 7.
It is equipped with The present invention relates to improvements in the contents stored in the status register 8. That is, the status register 8 stores, for example, 8 flag bits from bit 0 to bit 7, and in the embodiment of the present invention, the contents of bits 5 and 6, which are shaded in the figure, are different from the conventional ones. Make it different.

FIG. 2 shows a status register (
It is a figure showing the contents of STR)8. In the figure, the upper row shows the state when reading from the magnetic bubble memory device 7 (R), and the lower row shows the state when writing to the magnetic bubble memory device 7 (W). When reading (R)
In this case, the read enable signal RDA is set in bit 5, and the first data end flag bit TDRA*, which is generated in response to the end of the transfer of read data 4, is stored in bit 6 according to the embodiment of the present invention. be done. Conventionally, this bit 6 has stored a write enable signal TDRA ("0" during reading) which is unnecessary during reading (R).

Furthermore, at the time of writing (W) shown in the lower part of FIG. 2, bit 5 contains the second data end flag bit RDA*, which is generated in response to the end of the transfer of write data, according to the embodiment of the present invention. The write enable signal TDRA is set at bit 6. Conventionally, an unnecessary read valid signal RDA (“O” at the time of writing) was stored in bit 5 at the time of writing (W>).

The flag bits of bits θ to 4 and bit 7 are the same as the conventional ones. Briefly, bit 0 is busy indicating whether the magnetic bubble memory device is in operation or not.
Y) signal, bit 1 is the error (E RROR) signal that indicates whether an error has occurred, bit 2 is the write protect (WPRT) signal that indicates write protection, and bit 3 is whether or not a magnetic bubble memory device is installed. Bit 4 is a special command end (SCE) signal that indicates whether a special command such as a boot loop read/write is finished, and bit 7 is a command end (CME) signal. It's a signal.

FIG. 3 is an embodiment of a circuit for generating the first and second data end flag bits TDRA* and RDA* shown in FIG. 2. In the figure, a counter 9 is set with the number N of read bits or write bits given from the host CPυ2 (FIG. 1). The counter 9 receives a clock signal CL from the host CPU 2 that is synchronized with the read timing of each bit of read data from the magnetic bubble memory device 7 or the write timing of each bit of write data to the magnetic bubble memory device 7, and receives this clock signal CL. In response to this, the set number N of successive output/write bits is counted, and after the counting is completed, a count end signal CR is output.

During continuous output, the read/write signal R/- is "0" and the read valid signal RDA is "1".

Therefore, "1" of RDA passes through OR gate 10 and "1" is obtained at output terminal 11. This is stored in bit 5 of the status register (STR) 8 shown in FIG. 2 as a valid signal RDA(1') for reading at the time of successive reading. At the end of the read data transfer, the read/write signal is dirty.
0" to "L", and a count end signal CR is obtained at the output of the counter 9. At this time, if the no error signal is "1", that is, there is no error, the count end signal CR is switched from the AND gate 12 and the OR gate 13. a first data end flag bit TDR at output 14 through
Obtained as A*. This first data end flag bit TDRA* is stored in bit 6 of status register (STR) 8.

On the other hand, during writing, the read/write signal is “L”.
The write valid signal TDRA is "l'. Therefore, @l" of TDRA passes through the OR gate 13 and 11" is obtained at the output terminal 14. This is the write valid signal TDRA (1") during writing. Status register (ST
R)8 is stored in bit 6. At the end of the transfer of write data, the read/write signal ■ switches from "L" to "θ", and the count end signal C is sent to the output of the counter 9.
R is obtained. The read/write signal “0” is converted to “L” by the inverter 15 and the AND gate 16
is input. At this time, if the no-error signal is "l",
The count end signal CR passes through the AND gate 16 and the OR gate io and is obtained at the output terminal 11 as a second data end flag bit RDA*. This second data end flag bit RDA* is set to the status register (STR).
)8 bit 5.

In conclusion, the signal obtained at the output terminal 11 is always stored in bit 5 of the status register (STR) 8, and the signal obtained at the output terminal 11 is always stored in bit 5 of the status register (STR) 8.
The signal obtained in 4 is always stored in the status register (STR).
It should be stored in bit 6 of 8.

FIG. 4 is a time chart for explaining the operation of the magnetic bubble memory control device of FIG. 1 according to an embodiment of the present invention. In FIG. 4, the process up to time t3 is the same as the conventional example shown in FIG. When the data transfer ends at time t3, the counter 9 (FIG. 3) outputs the carrier signal CR as described above.
When the host CPU 2 detects this, it is released from the magnetic bubble memory control device 1. Ru. Therefore, only the time Δt between time t and t4,
The time during which CPtJ is exclusively used by the magnetic bubble memory device 1 is shortened.

The present invention is not limited to the embodiments described above, and various modifications are possible. For example, the data end flag bit may be stored in a location other than the read valid signal or write valid signal.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, by having the host CPU monitor the data end flag bit that occurs simultaneously with the end of data transfer, in the magnetic bubble memory control device, the host CPU Since the time dedicated to the memory control device can be shortened, the versatility of the host CPU is improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram schematically showing the overall configuration of a magnetic bubble memory control device according to the present invention, FIG. 2 is a diagram showing the contents of a status register according to an embodiment of the present invention, and FIG. FIG. 4 is a circuit diagram of the data end flag bit generation circuit shown in FIG. 2 according to an embodiment of the present invention; FIG. 4 is a time chart for explaining the operation of the magnetic bubble memory control device of FIG. 1 according to an embodiment of the present invention; FIG. 5 is a time chart for explaining the conventional magnetic bubble memory control method. 1... Magnetic bubble memory control device, 2... Host CPU. 3... Controller 7... Magnetic bubble memory device, 8... Status register, 9... Counter, RDA... Successive output valid signal, TDRA... Write valid signal, TDRA*... No. 1 data end flag bit, R
DA*...Second data end flag bit.

Claims (1)

[Claims] 1. A host CPU, a magnetic bubble memory device, a write enable signal generated when writing to the magnetic bubble memory device is possible, and a case when reading from the magnetic bubble memory device is possible. a status register storing a flag bit including at least a read enable signal generated in the magnetic bubble memory device; and a controller controlling data transfer between the host CPU and the magnetic bubble memory device based on the flag bit. A magnetic bubble memory control device characterized in that the flag bits further include a data end flag bit generated in response to the end of the data transfer. 2. The data end flag bit is stored in the area of the status register that stores the read valid signal when writing data to the magnetic bubble memory device, and the data end flag bit is stored in the area where the read valid signal is stored in the status register when data is finished being read from the magnetic bubble memory device. 2. The magnetic bubble memory control device according to claim 1, wherein the write enable signal is stored in the storage area. 3. A patent in which the data end flag bit is generated in response to a count end signal of a counter that counts the number of read/write bits output from the host CPU in synchronization with the read/write timing of each bit. A magnetic bubble memory control device according to claim 1 or 2.