JPS61103131A - Light emission control circuit of strobe device - Google Patents

Abstract

PURPOSE:To stop flash light emission extremely speedily by connecting a capacitor for stopping light emission in the discharge loop of a flash discharge tube in series and performing flash light emission while said capacitor is charged. CONSTITUTION:When a synchro contact X0 is made, the base potential of a transistor (TR) Q1 which is held at a level H by a resistance R14 falls to a level L, so the TR Q1 turns on. Consequently, the base potential of a TR Q2 goes up to a level H, so the TR Q2 turns on and TRs Q3 and Q4 turn on. Therefore, the collector of the TR Q3 is held at the level H and its H-level signal is applied as a charge control signal A2 to the gate of the 2nd thyristor Q20, which turns on. When the 2nd thyristor Q20 turns on, the remaining charge in the capacitor C4 for stopping light emission is discharged instantaneously through the path of the capacitor C4 for stopping light emission, anode and cathode of the 2nd thyristor Q20, and a line l20 and the thyristor Q20 decreases in current below a hold current and turns off.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention provides a light emission control circuit in a strobe device, and more specifically, the time from when a flash discharge tube stops emitting light to when it starts emitting light again can be extremely reduced. The present invention relates to a light emission control circuit suitable for a strobe device that performs light emission in conjunction with a motor drive device, dynamic flat light emission, etc.

(Prior art) In general, series control type strobe devices are, for example,
This strobe device is described in Japanese Patent No. 30905, and as shown in FIG.
Charging resistor 'FL of commutating capacitor Cc and rotating current capacitor Cc. 4. Rc2. A commutating thyristor 5CRc and the like are connected as shown in the figure.

Then, by turning on the main thyristor SCRM, the flash discharge tube XTJ starts emitting light, and when the amount of light emitted at this time reaches the value necessary to obtain proper exposure, the commutating thyristor 5CRc is turned on, and the resistor R61 , commutating capacitor Cc, and resistor R62, the main thyristor 5CFt, u is reverse biased by the commutating capacitor Cc charged through the path of the commutating capacitor Cc and the resistor R62.
M is turned on to stop the flash discharge WXL from emitting light.

When using such series-controlled strobes to perform multi-strobe photography in which the strobe fires several times during one fully open shutter operation of the camera, the motor controls the shooting of several frames per second. When performing motor drive linked strobe photography that is linked to a drive device,
Or when performing dynamic flat flash photography that repeatedly emits small pulse-like flashes at extremely short intervals to achieve substantially uniform exposure while slit exposure is being performed using a 7-ocal plane shutter. To start the next flash after a short period of time, as in The current capacitor Cc needs to be charged.

However, the charging time constant to the commutating capacitor Cc can be made small due to the presence of the resistors R, R, and the commutating thyristor 5 due to the commutating capacitor Cc is
Since the commutation operation cannot be made faster due to the time constant of @flow to CRc, there is a problem that the time from the start of flash light emission to the start of the next flash light emission cannot be reduced. Furthermore, if the commutating thyristor 5CRc is turned on when the commutating capacitor Cc is not sufficiently charged, there is also a problem that a commutation error occurs.

(Objective) An object of the present invention is to provide a light emission control circuit for a strobe device, which can stop flashlight emission very quickly and can start flashlight emission again very quickly after the flashlight emission has stopped. be.

(Summary) The light emission control circuit in the strobe device according to the BAIC of the present invention connects a light emission stopping capacitor in series during the discharge loop of the flash discharge tube, and performs flash light emission while the light is bent to the capacitor. This is what I did.

(Example) First light emission control circuit in a strobe light emitting device of the present invention
An embodiment will be explained using FIG. 1 and FIG. 2.

The first tooth shows the light emission control circuit of this embodiment, and the second tooth shows its time chart.

The light emission control circuit includes a main circuit 100 as shown in 1aK.
and a control circuit 200, and one end of a step-up power supply circuit DCC, which forms part of the main circuit 100 and converts the voltage of a power supply battery etc. into high voltage, is a negative voltage supply line (hereinafter abbreviated as line-eo). The other end is connected to a positive voltage supply line (hereinafter referred to as line J) via a rectifying diode D.

(abbreviated as ). Main capacitor CI + resistor R3 and neon lamp N are connected between both ins 13o and 4.
A well-known charge completion indicating circuit consisting of a series circuit of E is connected, and resistors R, 2, R, 3, R4, R5,) Riga capacitor C2, capacitor C3, trigger Sirisk Qr
, a trigger transformer T, etc., are connected to the well-known trigger circuit. A light emission trigger signal A1 sent from the control circuit 200 is supplied to the resistor R5.

Furthermore, a diode D2 is connected between the above lines go and 4.
and a parallel circuit of coil L1, and the number of flashes 'Ft tube XI,
A first thyristor Q, which is a first switching element.

A series circuit of the capacitor C4 and the capacitor C4 for stopping one light emission is connected.

The trigger electrode of the tube XL with the number of flashes M is connected to the trigger output terminal of the trigger transformer T, and a discharge loop of the capacitor C4, which is a second switching element, is connected to both ends of the capacitor C4 for stopping light emission. The forming second cyrisk Q20 is connected. A bias setting resistor R6 is connected between the gate and cathode of the first thyristor QJI). At the gate of
A parallel circuit of a capacitor C5 and a resistor R7 and a resistor R8 are connected in sequence, and a control circuit 200 is connected to the other end of the resistor R8.
A light emission start signal A3 that is also sent out is supplied.

A bias setting resistor R2 is connected between the gate and cathode of the second thyristor Q2o.
A parallel circuit of a capacitor C6 and a resistor R16, and a resistor all are sequentially connected to the gate of the resistor R11, and the discharge control signal A2 sent from the control circuit 200 is connected to the other end of the resistor R11.
is being supplied.

Next, the configuration of the control circuit 200 will be explained. Line shadow 0. A series circuit consisting of a resistor R12, a diode D3 for preventing backflow, and a resistor R13 is connected between the type 8 and a voltage dividing point of a voltage dividing circuit formed by the series circuit.

That is, the connection point between the cathode of the diode D and the resistor R13 is connected to a low voltage power supply line K (hereinafter abbreviated as line 22). There is a line between the same line 2□ and the above line - go! A capacitor C7, which serves as a power source for the second circuit, is connected. Both lines 2. ! 0 between resistor R14 and resistor R1
5 and a tuning contact Xo are connected in series. This tuning contact Xo is provided on the camera! 'Ah, 1
, 2□5Met; □Fi 2.1 construction has been completed.

The connection point of the resistor R14#R4s is connected to the base of the PNP transistor Q1, the emitter of the transistor Q is connected to the line p2, and the collector is connected to the resistor R1.
The line lokcg is connected through 6 and %NP
It is connected to the base of an N-type transistor Q2, whose emitter is connected to line 2°, and whose collector is connected to line 22 through resistors a and R at about j. The connection point of the resistors R171R18 is connected to the respective bases of PNP type transistors Q, Q4. The same transistor Q5. Each emitter of Q4 is a line! ,It is connected to the. The discharge control signal A2 is transmitted from the collector of the transistor Q3 to the main circuit 10.
011+. The collector of the transistor Q4 is connected to the line -eoK through a parallel circuit of a resistor R19, a resistor 20, and an integrating capacitor C8.
It is connected. The connection point between the resistor R19 and the integrating capacitor C8, that is, the integrating output terminal is connected to an NPN transistor Q.
Connected to 1 base of 5. The work of the same transistor Q5 2 Mituta is on the line! . and the collector is connected to line 11. through resistor RH' R22 in turn. It is connected to the. The connection point between the resistors R and R22 is connected to the base of a PNP type transistor Q6. The emitter of the transistor Q6 is connected to the line p2, and the collector receives the light emission trigger signal A and the light emission start signal A3.
is sent to the main circuit 100 side.

The operation of the light emission control circuit in this embodiment configured as described above will be explained using the time chart shown in FIG. 2.

When the tuning contact Xo is turned on at the same time as the shutter of the camera is fully opened, the base potential of the transistor Q1, which is set to the H level by the resistor R14, becomes the L level, so that the transistor Q1 is turned on. Along with this, the base potential of transistor Q2 becomes H level, so transistor Q2 is turned on, and transistors Q, . The level signal is applied as the charging control signal A2 to the gate of the second thyristor Q20, turning on the second thyristor Q20.

When the second thyristor Q20 is turned on, the light r=z charge remaining in the light emission stopping capacitor C4 is instantly discharged along the path from the light emission stopping capacitor C4 to the anode/cando of the second thyristor Q20 to line No. 0. At the same time, the thyristor Q20 becomes lower than the holding current and turns off. At the same time as the charging control signal A2 rises to the H level, in other words, the transistor Q4 turns on at the same time as the transistor Q3 turns on, so that the line type voltage starts to be integrated into the capacitor C8 by the resistor '19. . After that, the integrated voltage of capacitor C8 is applied to transistor Q5.
Base-emitter potential threshold (for example, 0.6
When the voltage exceeds V), the transistor Q5 turns on. The delay time τ due to the proportionally divided voltage until the threshold value is exceeded is provided in order to discharge the charge in the capacitor C4. When the transistor Q5 turns on, the transistor Q60 goes to L level ItCfxte, and the transistor Q6 turns on. When transistor Q6 is turned on, the collector of transistor Q6 rises to H level. This H level signal is applied as the light emission trigger signal A1 to the gate of the trigger thyristor QT, and the thyristor QT is turned on. When the same trigger thyristor QT turns on, line 1f → resistor R2 → trigger capacitor C
2 → primary coil of trigger transformer T → line 4o, the charge of trigger capacitor C2 that has already been charged is discharged, so that the discharge current at this time is transferred to the primary coil of trigger transformer T, KfAI, and the transformer A high voltage develops in the secondary coil of T, and flash discharge tube XL is triggered.

At the same time, the light emission start signal A3 rises to H level, thereby turning on the first thyristor Q+o. 1st
When thyristor Q, o of is turned on, line 4. → Coil LI-4 - Flash discharge tube XL → First thyristor Q +
o's anode/cando → Capacitor C4 for stopping light emission →
A current flows through the path of the line 1o, and the flash discharge tube XL starts emitting flash light. Light is emitted by the discharge current flowing through the flash discharge tube XL at this time; 1 Stop capacitor C4
When the charging voltage of the capacitor C4 increases and the discharge current becomes equal to or less than the holding current of the first thyristor Q r o, the thyristor Q +o is turned off and the flash light emission stops.

Similarly, tuning contact X is shown below. The above operation can be repeated as the switch turns on.

Next, the second embodiment of the light emission control circuit according to the present invention will be described in the third embodiment.
This will be explained based on FIG. In this embodiment, the light emission control circuit according to the present invention is applied to a dynamic type flat light emission strobe device.

Main circuit 101 shown in Fig. 3 and control circuit 20 shown in Fig. 4
It consists of 1.

Note that the main circuit 101 is the main circuit 1 in FIG.
00 is constructed in exactly the same way except for the additional circuit portion, so the same components are given the same reference numerals and their explanations will be omitted. The same applies to each embodiment below.

As shown in FIG. 3, a main circuit 101 is obtained by adding an additional circuit to the main circuit 100 shown in FIG. 1 above.

That is, there is a resistor FL51# across the main capacitor C8.
A voltage dividing circuit formed by R52 is connected, and a monitor voltage signal M is sent to the control circuit 201 side, which will be described later, from the connection point of resistors R51#R52 of the circuit, in other words, from the voltage dividing point. Further, the output terminal of the OR gate OR3 is connected to the other end of the resistor R8, which is connected to the gate of the first Cyrisk Qto via the resistor R2, and the input terminal of the OR gate OR is connected to the control circuit described below. A light emission start signal A3 and a light emission restart signal A4 sent from the 201 side are supplied.

Control f! in this embodiment! As shown in FIG. 4, one circuit 201 is connected to a tuning contact 1 for flat light emission provided on the camera. This tuning contact 1 is formed by a switch that is closed once just before the front curtain of the focal plane shutter is exposed, and is closed again when the front curtain has completed exposing the film screen. One end of this tuning contact 1 is grounded, and the other end is connected to one end of a resistor 2 and an NPN type transistor 30 pace KJ! It is continued. The other end of the resistor 2 is connected to a positive voltage power supply 1B, and the collector of the transistor 3 is connected to the positive voltage power supply 1B via a resistor 4. In addition, the collector of the transistor 3 is triggered when the λ power level increases from the L level to the H level, and outputs a one shot pulse of the H level.
It is connected to the trigger input terminal of the pulse generating circuit (abbreviated as pulse generating circuit) 5. 18! The output terminal of the circuit 5 is connected to the set input terminal of the R8 type 7 lip-flop circuit (hereinafter abbreviated as FF circuit) B, and the 1 light emission trigger signal A and the light emission start signal A3 are sent to the main circuit 1011jll. It's like a trap. The output terminals of the four B"F circuit sections are connected to the input terminals of one of the AND gates 7 and 8, and are also connected to the trigger input terminal of the pulse generation circuit 9. The output terminal of the pulse generation circuit 9 is connected to one input terminal of the OR gate 10, and the output terminal of the OR gate 10 is)
' F [51 Connected to the set input terminal of path 11. The output terminal of the same 11i5Jj'311 is AND gate 12
is connected to one input end of the

On the other hand, the monitor voltage signal M from the main circuit 101 side is supplied to the input terminal of the arithmetic circuit 130 (5), and the output terminal of the circuit 13 is connected to the above-mentioned AND/GO signal via the V-F comparator 14 (7). .12. This arithmetic circuit 13 is a main capacitor C
, is divided by the resistors ``31'' and ``52'', the voltage is squared, and the output voltage is converted into a reciprocal number.As a result, the output voltage is inversely proportional to the square of the voltage of the main capacitor C8. It is formed so that it can be obtained.

The output terminal of an oscillation circuit 15 is connected to the other input terminal of the AND gate 8, and the oscillation circuit 15 is connected to one end of each of a resistor 15a and a capacitor 15b that determine its own oscillation frequency. A positive voltage power supply element B is supplied to the other end of each of the capacitors 15b.

The respective output terminals of the AND gates 7.8.12 are connected to the count input terminals of the counter circuits 16, 17.18. The counter circuit 16 is used to control the light emission interval from the start of a small flash to the start of the next small flash in dynamic flat flash, and the circuit 16 controls the shutter speed and aperture value.

It serves as a light emission interval setting circuit into which preset data corresponding to a time within the deionization time of the flash discharge tube XL, which is set according to film sensitivity and the like, is input. Also,
The above counter times! I5'17 is a total light time setting circuit into which preset data x2 is input, which is set to a count number corresponding to the time from the start to the end of film exposure, which is determined according to the shutter speed, etc. . Furthermore, the counter circuit 18 is for controlling the discharge of the capacitor C4, and the preset data 3:
The discharge timing setting circuit receives preset data x3 corresponding to a count number smaller than the count number corresponding to .

The respective output terminals of the counter circuits 16, 17, and 18 are connected to the trigger input terminals of the pulse generating circuits 19, 20, and 21, and the output terminals of the pulse generating circuits 19 are connected to the other input terminal of the OR gate 10. At the same time, a light emission restart signal A4 is sent to the main circuit 101 side. The output terminal of the pulse generating circuit 20 is an FF circuit 220.
The output terminal of the circuit 22 is connected to one input terminal of an AND gate 23. The output terminal of the pulse generating circuit 21 is connected to the other input terminal of the AND gate 23 and the reset terminal of the FF @ path 11, and the discharge control signal A2 is sent to the main circuit 101 side. .

Further, the reset signal R sent from the output terminal of the AND gate 23 is transmitted to the FF circuit 6.22, the counter circuit 16.1
7.18 to be supplied to their respective reset terminals.

This is 5! %! The operation performed in this example is described in the fifth section.
This will be explained using the time chart shown in the figure.

Now, when the shirt release is performed, the first 4Y run starts, the tuning contact 1 closes, and as a result, the base of the transistor 3 goes to the L level, so the transistor 3 turns off. When the transistor 5 turns off, the pulse generating circuit 5
The signal at the trigger input end of is at H level! On the upstream side, the same circuit 5 is triggered and outputs an H-level funsit pulse. This output is applied as a light emission start signal A to the gate of the trigger thyristor QT, turning on the same thyristor QT. When the thyristor QT is turned on, the flash discharge tube XL is triggered in the same manner as described above. At the same time, the H level output of the pulse generating circuit 5 is sent to the first thyristor Q as a light emission start signal A3 via an OR gate OR. Since the gate current is applied, the same thyristor Q1° is turned on. 1st
When the thyristor Q+o is turned on, the tube XL starts emitting light with the same number of flashes as described above. At the same time, since the FF circuit 6 is set by the H level output of the pulse generating circuit 5, AND gates 7 and 8 are both opened. Furthermore, F.F.
Since the pulse generating circuit 9 is triggered by the H level output of the circuit 6, an H level one shot pulse is generated at the output of the circuit 9. This output pulse passes through the OR gate 10 and sets the FF circuit 11, and the output of the four FF circuit 11 becomes H level, opening the antgel gate 12. Therefore, counting of the output pulses of the oscillation circuit 15 is started by the counter circuit 17Vc in which the total light time is set.

Further, the voltage of the main capacitor C2 at this time is supplied to the arithmetic circuit 13 as a monitor voltage signal M divided by the resistors R and RK. The circuit 13 converts the voltage into a voltage inversely proportional to the square of the energy of the main capacitor C0. This converted voltage is converted by the V-F converter 14 into a pulse signal P having a frequency proportional to the input voltage. This pulse signal P is inputted via the AND gate 7 to the counter circuit 16 for setting the light emission interval, and is also inputted via the AND gate 12 to the counter circuit 18 for setting the discharge timing.

Then, charging of the light emission stopping capacitor C4 by the discharge current of the flash discharge tube XL is completed, and the first thyristor Q
When the current flowing through ro becomes less than the holding current, the same thyristor Q
ro is turned off and light emission stops.

Thereafter, when the number of pulses of the pulse signal P reaches the count number corresponding to the preset data J5K, the output of the counter circuit 18 rises to the H level. Then, the pulse generation circuit 21 is triggered and a one-shot pulse of H level is generated, and this pulse is transmitted to the discharge side 3, ) control signal 6
is applied to the second thyristor Q20, turning on the same thyristor Q20.Then, the electric charge of the light emission stopping capacitor C4, which is charged by the current flowing through the flash discharge tube XLK, is transferred by the second thyristor Q20. It is discharged during the abdomen, and you can see the start of the next small light emission.

At the same time, the FF' circuit 11 is reset by the H level shot pulse of the pulse generating circuit 21, so the output of the circuit 11 is inverted to the L level, and accordingly, the AND gate 12 is closed. The pulse signal P is no longer input to the counter circuit 18.

Thereafter, when the pulse count number of the pulse signal P by the counter circuit 16 for setting the light emitting interval reaches the count number corresponding to the preset data x1, the output of the circuit 18 rises to the H level, and the circuit 16 is reset. At the same time, the pulse generating circuit 19 is triggered. Then, 4′ circuit 1
At 9, an H level shot pulse is generated, and this pulse is sent to the first thyristor Q+ via OR, as a light emission restart signal A4.

is applied to the gate of the same thyristor Q,. Turn on. When the first thyristor Q+o is turned on, the flash discharge tube XL starts emitting light in the same manner as described above.

At the same time, the output of the H level one-shot pulse of the pulse generation circuit 19 sets the FF circuit 11 via the OR gate 10, so the output of the same circuit 32 is inverted to H level, and accordingly, the AND gate 12 is opened again, the pulse signal P is input to the counter circuit 18, and counting starts in the same manner as described above.

Thereafter, in the same way, the flash discharge tube XLK repeatedly emits small light by sequentially and repeatedly generating H-level pulses in the discharge control signal A2 and the light emission restart signal A4. The repetition interval of such small light emission, ie, the light emission interval, becomes longer when the voltage of the main capacitor C1 is high, and becomes shorter when the voltage of the main capacitor C1 is low. Therefore, as the voltage of the main capacitor CI decreases, the amount of light from each small light emission gradually decreases, so the light emission interval is gradually shortened so that the actual light emission level remains constant.

After that, when the number of pulses input to the counter circuit 17 for setting the total light time reaches the count number corresponding to the preset data &2 IC, the output of the circuit 18 goes to H level KW.
climb. Then, the pulse generation circuit 21 is triggered by this output, the FF' circuit 22 is set, and the AND gate 23 is opened. Then, when the H level pulse of the discharge control signal A3 passes through the AND gate 23, each part of the circuit is reset by the reset signal R generated at the output of the AND gate 23, and a series of 7 dynamic type R lights is completed.

It goes without saying that the light emission interval of the above-mentioned small light emission needs to be set within the deionization time of the flash discharge tube XL.

In the second embodiment, the light emission per flash is uniquely determined by the capacitance of the capacitor C4 for stopping light emission and the voltage of the main capacitor CI5, so the respective capacitances are determined as shown in FIG. Switch to select multiple different light emission stop capacitors C511C521C53"5
It may be replaced with a capacitance cutting circuit 50 that is selectively connected at 0. By doing this, the amount of light per one small light emission can be selectively adjusted according to the capacitance of each of the plurality of capacitors C511C52e and C5g. can be obtained. That is, when each company is large, K emits a large amount of light, and when it is small, it emits a small amount of light.

Further, as shown in FIG. 7, a plurality of circuits 51, 52, and 53 similar to those shown in FIG. capacitor C5 for stopping light emission.

C521C53 are connected and these circuits 51. ...
may be selectively switched using changeover switches 551a l 5s1b.

Next, a third embodiment of the light emission control circuit according to the present invention will be described with reference to FIG. In this embodiment, the light emission control circuit according to the present invention is applied to a dynamic type flat light emission strobe device, and an additional circuit is provided to the main circuit 101 shown in FIG. 3 above to form the main circuit 102 as shown in FIG. This is an example in which the same control circuit as the control circuit 201 shown in FIG. 4 is used as the control circuit connected to the main circuit 102.

In the main circuit 102 shown in FIG. .

A series circuit consisting of a resistor 8, a resistor 1, and a resistor R42 is connected between the terminals 9 and 1, and the resistor R4.

The connection point of R42, in other words, the voltage dividing point is the low voltage line (
The line 22 (abbreviated as line 22) is attached below the feet. Line with □ on the same line! . A capacitor C41 is connected between them, and a line AoK is connected through resistors FL, R, and the collector/emitter of an NPN transistor Q4+ in this order. And the same transistor Q41
The base of the line is connected to the line through the resistor 45. When connected, the light emission start signal A2 from the control circuit 201 (see Fig. 4) is supplied through the Rat resistor 46. . Also, the connection point of resistor 1 (43°RJ44 is PN
It is connected to the base of a P-type transistor Q420, and the emitter of the same transistor Q42 is connected to the line! 32. Furthermore, the line C2 is connected to a resistor R4, l't48.
It is connected to the line 2o through the collector and emitter of an NPN transistor Q45 in sequence. The transistor Q450 is connected to line p through a resistor R49. K is connected to the OR gate 01' (
・Both input terminals of the above-mentioned side control circuit 201 (fourth
Light emission start signal A3° and light emission restart signal A4 from (see figure)
are sent respectively. The emitter of the transistor Q44 is connected to line 2□, and the collector is connected to the gate of the first thyristor Q+o through a parallel circuit of resistor R51, resistor R52 and capacitor C, and the anode and cathode of diode D43. There is. There is a resistor R5 between the cathode and gate of the same thyristor Q +o.
3 is connected to the gate, and the cathode of a diode D42 for forming a discharge loop of the light emission stopping capacitor C4 is connected to the gate, and the anode of the diode D42 is connected to the cathode of the first thyristor Q+o. has been done. Further, the first thyristor Q+.

cathode and line! . There is a capacitor C for stopping light emission in between.
4 is connected. Also, the first thyristor Q.

The anode of the second thyristor Q20 is connected to the gate of the line node oVC, and the cathode of the second thyristor Q20 is connected to the line node oVC.
It is connected.

The collector of the transistor Q42 is connected to a parallel circuit of a resistor R54, a resistor R and a capacitor C43, and a diode D44.
The gate of the second thyristor Q20 is connected to the gate of the second thyristor Q20 through the anode and cathode of the transistor Q20. Also, the same gate and line! . A resistor R56 is connected between the two.

In the real M fll' Ic configured in this way,
When the light emission trigger signal A and the one-shot pulse of the light emission start signal A3KH level are sent from the ilJ control circuit 201 (see the fourth cause), the trigger thyristor QT is turned on by the same signal A1, and the same process as described above occurs. Flash discharge tube XL is triggered. At the same time, the light emission start signal A3 is applied to the base of the transistor Q43 via OR, so that the transistor Q43 is turned on.

Then, the base of the transistor Q44 becomes L level, so the transistor Q44 is turned on, and accordingly, the first thyristor Q+o is turned on, and light emission is performed by the flash discharge t·XL in the same manner as described above. When the photoelectric current to the capacitor C4 for stopping light emission accompanying this light emission becomes less than the holding current of the first thyristor Q'+, the same thyristor Q,+.

is turned off.

Thereafter, when a pulse of charge control signal A2KH level is generated, the base of transistor Q41 becomes H level, and transistor Q41 is turned on. Along with this, the pace of the transistor Q4 DEG becomes H level, and the transistor Q42 is turned on. Along with this, the second thyristor Q20 is turned on.

When the thyristor Q20 is turned on, the electric charge charged in the light emission stopping capacitor C is transferred to the 7 node of the diode D42.
The cathode + the anode/cathode of the second thyristor Q20 is instantaneously discharged along the line eo. At this time, since the cathode and gate of the first thyristor QIG are reverse biased, the first thyristor Qro is surely turned off, and while the second thyristor Q20 is on, the first thyristor QIG is turned off for some reason. Even if high-level noise occurs at the gate of thyristor Q1゜, the same thyristor Q1
o won't turn on, it's set to 5. After that, the transistor Q43 is turned on again by the H level pulse generated in the light emission restart signal A4, and accordingly, the first irristor Qro is turned on again, and the light emission by the flash discharge tube XL is resumed. Similarly, small light emissions are repeated at light emission intervals depending on the voltage of the main capacitor C0.

Next, a fourth embodiment of the present invention will be described. In this embodiment, the light emission control circuit according to the present invention is applied to a strobe device having a dynamic flat light emission function and a flash light emitter IIM, and an additional circuit is provided to the main circuit 102 shown in FIG. A main circuit 103 as shown in the figure is used, and the control circuit connected to the main circuit 103 is an additional circuit added to the control circuit 201 shown in Fig. 4 above to form a control circuit 202 as shown in Fig. 10. be. Therefore, Fig. 9, 1st
Identical components other than the additional circuits of each of the above-mentioned circuits in FIG.

In the main circuit 103 shown in FIG. 9, line 22° shadow.

In between, there is a circuit 3I/fi (each symbol is a), which is configured similarly to the switching circuit formed by the transistor Q41 p Q42 y resistor R43° RR, R.

(subscripts b and c) are connected in the same way.

Furthermore, the connection point between the flash discharge tube XL and the first thyristor Qro, and the line! . The main thyristor Q61 for flash emission is connected between the lines! Between 1 and 10 is a resistor R and a commutating capacitor C6.

A series circuit of resistor R62 is connected. The connection point between the commutating capacitor C and the resistor R62 is connected to the anode of the main thyristor Q, and the connecting point between the resistor R61 and the commutating capacitor C6 and the line 2o reverse biases the main thyristor Q41. A commutating thyristor Q62 is connected for this purpose. A flash light emission start signal A7 sent from the control circuit 202 is supplied to the base of the transistor Q through a resistor R463.
The collector of the diode D61 is connected to the main thyristor Q61 through a parallel circuit consisting of the anode/cathode 2a of the diode D61, the resistor R, the resistor R64, and the capacitor C62.

Also, a resistor R46b is connected to the base of the transistor Q41b.
A flash light emission stop signal A5 sent from the control circuit 202 is supplied through the transistor Q.
The collector of 42b is connected to the gate of a commutating thyristor Q62 through a parallel circuit consisting of the anode/cathode of a diode D62, a resistor R66, a resistor "67" and a capacitor C63 in this order.

Furthermore, the base of the transistor Q41c is connected to the resistor R46.
A control circuit 20 is connected to the output terminal of the OR gate OR2 through C, and a control circuit 20 is connected to the input terminal of the OR gate OR2.
A light emission trigger signal A and a flash light emission trigger signal A6 sent from the light source 2 are supplied. Further, the collector of the transistor Q45G is connected to the resistor R5 via the anode and cathode of the diode D65. A bias setting resistor R is installed between the gate and cathode of the main thyristor Q and the commutating thyristor Q6□.
, R are connected.

In the control circuit 202 shown in FIG. 10, the output terminal of the pulse generating circuit 5 is connected to the first input terminal of the three-man-powered AND gate 61, the first input terminal of the three-human-powered AND gate 62, and one of the AND gates 63. Connected to the input end. The second input terminal of the AND gate 62 is connected to the output terminal of an inverter 64, and the input terminal of the inverter 64 is connected to the other input terminal of the AND gate 63. The output terminal of the AND gate 62 is connected to the set input terminal of the F'F circuit 650, and the output terminal of the same circuit 65 is connected to the other input terminal of the AND gate 63. The output terminal of the AND gate 63 is connected to the set input terminal of the FF circuit 66, and
A flash light emission trigger signal A6 and a flash light emission start signal A7 are sent to the main circuit 103 side. The output end of the FF circuit 66 is connected to the base of an NPN transistor 690 via an inverter 67 and a resistor 68 in this order. There is a resistance of 70.71 between the positive voltage electric atom B and the ground terminal.
A voltage dividing circuit formed by is connected.

The connection point of the resistors 70 and 71, in other words, the voltage dividing point, is connected to the inverting input terminal of the operating circuit 20 forming the voltage comparison circuit. The positive voltage electric atom B is connected to the collector of a phototransistor 76 provided in the camera body or the strobe device body for receiving reflected light from a subject, and the emitter of the phototransistor 73 is connected to a resistor 74 and an integrating capacitor. It is grounded through 75 in sequence. The connection point between the resistor 74 and the integrating capacitor 75 is connected to the collector of the operational amplifier 72. The output terminal of the operational amplifier 72 is connected to the trigger input terminal VC of the pulse generation circuit 76, and the output terminal of the circuit 76 is connected to the above F.
It is connected to the reset terminals of each of the F circuits 65 and 66.

Further, a changeover switch 77 for switching between the "dynamic flat light emission mode" and the "flash light emission mode" is provided, and the common end 77c of this switch 77 is connected to the third input terminal of the AND gate 62, and It is connected to the second input terminal of the AND gate 61 via an inverter 79. Furthermore, the first terminal 77 of the switch 77
a is connected to the positive voltage electric atom B via a resistor 78, and the second
The terminal 77b of is grounded. An inverter 80 is connected between the output terminal of the FF circuit 6 and the third input terminal of the AND gate 61.

The operation of this embodiment configured in this way will be explained. In the case of "dynamic flat light emission mode", the common end 77c of the changeover switch 77 is connected to the terminal 77b.
- Since the switch is made to the negative side, the AND gate 62 is closed, and since the output of the FF circuit 65 is at L level, the AND gate 63 is closed.

Therefore, the flash light emission trigger signal A6. Flash light emission start signal A2
．． Both flash light emission stop signals A5 are maintained at L level.

At this time, the output terminal of the inverter 79 connected to the second input terminal of the AND gate 61 is connected to the second input terminal of the AND gate 61.
Since the 0 input terminal is grounded via switch 77, H
The output terminal of the inverter 80 connected to the third input terminal of the AND gate 61 is at the H level since the output terminal of the FF circuit 6 connected to the input terminal of the inverter 800 is at the L level. level. Therefore, AND gate 61 is in an open state.

Therefore, when the tuning contact 1 is closed in the same manner as described above, the output terminal of the pulse generation circuit 5 is set to the H level one signal 1.
This pulse passes through the AND gate 61 and sets the FF circuit 6.

Then, the output of the circuit B is inverted to the H level, and the light emission trigger signal A and the light emission start signal A3 rise to the H level in the same manner as described above. At the same time, AND gate 61 is closed via inverter 80.

Then, the H level signal of the light emission trigger signal A is applied to the base of the transistor Q41c via OR2 and the resistor R46C in sequence, so the transistor Q4 is applied to the base of the transistor Q41c.
1° turns on, and along with this, transistor Q45 turns on.
c is turned on. Then, the potential of the line node (H level)
is the 7-node cant of diode D65, resistor kR5+
The voltage is applied to the gate of the trigger thyristor QT through the parallel circuit of the resistor R4 and the capacitor C3.
t is turned on. When the trigger thyristor QT is turned on, the flash dazzling 'IXL is triggered in the same manner as described above. At the same time, the first light emission start signal A3 at H level is activated as described above.
Thyristor Qi.

□ is turned on and the flash discharge tube XL starts emitting light. - Thereafter, the discharge control signal A2 rises to the H level as described above, and then the light emission restart signal A4 rises to the H level, so that small light emission is repeatedly performed in the same manner as in the third embodiment.

On the other hand, in the case of the "flash emission mode", the common terminal 77c of the switch 77 is switched to the terminal 77a side, so the second input terminal of the AND gate 61 is brought to L level via the inverter 79, and the AND gate 61 is closed. Therefore, the signal A1. A2. A3. Both A4 are maintained at L level.

Therefore, when the shirt release is performed now, the front curtain of the shutter starts running, and the tuning contact 1 is closed accordingly. Along with this, the base of the transistor 4 is grounded, so the transistor 4 is turned off, and the input signal of the pulse generating circuit 5 becomes H level, so that an H level pulse is generated at the output terminal of the circuit 5. When the AND gate 63 is opened, this pulse is applied to the first input terminal of the AND gate 62 to which the KH level signal is applied to the second and third input terminals, so it passes through the AND gate 62 and is sent to the FF circuit 65.
is set, the AND gate 62 is closed, and the AND gate 63 is opened. Thereafter, as the leading curtain of the shutter completes running in front of the film screen (the shutter is fully open), the tuning contact 1 is closed again, so that the pulse generating circuit 5
is triggered again.

The H level output of the pulse generating circuit 5 generated by this trigger passes through the AND gate 63 which is connected to the output of the FF path 65, and the flash light emission trigger signal A
6 and the H level pulse of the flash light emission start signal A7. Then, the flash discharge tube XL is triggered by turning on the trigger thyristor QT by the H level pulse of the flash light emission trigger signal A6. At the same time, the transistor Q41a is activated by the H level pulse of the flash light emission start signal A7.
is turned on, and accordingly, transistor Q42a is turned on. When transistor Q42a is turned on, line no. The voltage at the emitter of transistor Q42a
It is applied to the gate of the main thyristor Q61 through the collector, the anode/cathode of the diode D61, the parallel circuit of the resistor R63, the resistor R64, and the capacitor C62, turning on the thyristor Q<11. When main thyristor Q61 turns on, the line! 1 → Coil L, →
Flash discharge tube XL → Main thyristor Q6. Anode of
Cathode → Rhinestone. Since the Ml flow flows through the path, the flash discharge tube XL starts emitting light.

At the same time, the signal A6. Since the FF circuit 66 is set by the H level pulse of A, the transistor 69 is accordingly turned off. Then, the capacitor 75 starts integrating the reflected light from the photographic object, which is received by the phototransistor 73. Then, the integrated output voltage at this time, that is, the capacitor 75 and the resistor 74
The voltage at the connection point of the resistor 70.7 is applied by the operational amplifier 72
It is compared with a reference voltage according to 1.

After that, when the amount of light received by the phototransistor 73 reaches a value for obtaining proper exposure, the output of the operational amplifier 72 becomes H level and the pulse generation circuit 76 is triggered.
A one-shot pulse of H level is generated at the output terminal IK. This H level pulse turns on the transistor Q41b via the resistor R46b as a flash light emission stop signal A5. When the transistor Q41b is turned on, the transistor Q42b is turned on, and the potential of line 12 is sequentially passed through the parallel circuit path of the anode/cathode of the emitter/collector diode D of the transistor Q42b → the resistor R66 → the resistor "67" and the capacitor C63. The voltage is applied to the gate of the commutating thyristor Qd2.Then, the commutating thyristor Q62 is turned on, and the already charged commutating thyristor Q62 is turned on, and the already charged commutating thyristor Since the main thyristor Q61 is reverse biased by the discharged charge of the current capacitor C6, the thyristor Q61 is turned off and a flash discharge Wx occurs.
The light emission of L stops, and a series of flashlight emission operations is completed.

Next, a fifth embodiment of the present invention will be described. This embodiment is designed to support multi-flash photography and dynamic flat flash photography for monochrome 2-eve continuous @ photography.
The main circuit 104 shown in FIG. 11 is the main circuit 104 shown in FIG.
The control circuit 203 shown in FIG.
The control circuit 20 shown in FIG.
Reference numeral 4 is a dynamic flat light emitting device for controlling the main circuit 104 in response to motor-driven rapid photography.

In the main circuit 104 shown in FIG. 11, a circuit similar to the capacitance switching circuit 50 shown in FIG. 6 is connected between the cathode of the first thyristor QiO and the line 2o. Further, the cathode of the diode D71 is connected to the gate of the first thyristor Q1o, and the cathode of the diode D71 is connected to the gate of the first thyristor Q1o.
The anode of the thyristor Q+o is connected to the cathode of the same thyristor Q+o. The anode of the thyristor Q71 is connected to the line B, and the same cand of the iristor Q710 is connected to the connection point between the anode of the trigger thyristor QT and the trigger capacitor C2. A bias setting resistor Fc87 is connected between the gate and cathode of the thyristor Q71.
1 is connected to the gate, and the first trigger control signal B sent from the control circuit 203 side is connected to the resistor R and the resistor R7.
2 and a capacitor C21 in a parallel circuit.

The anode of the trigger thyristor QT is a diode D.
750 cathode is connected, the same thyristor QT,
The anode of the diode D75 is connected to the cathode of the diode D75. □, Io)'D, 3 (7) Cuff-)'&t, resistance "74. NPN type transistor Q
72 collector-emitters in sequence. K
It is connected. The pace of transistor Q72 is connected to the right side of the line via resistor R75, and resistor R76.
is sent from the control circuit 203 side via! :5 trigger control signal B3 is supplied. Also,
A control circuit 203 is provided at the gate of the first thyristor Q+o.
The light emission start signal B4 sent from the side is connected to the resistor R8゜resistor R
7 and a capacitor C5 in sequence. Further, a discharge control signal B5 sent from the control circuit 203 is applied to the gate of the second thyristor Q20 through resistors R1, . . . . and a capacitor C6 in sequence.

In the control circuit 203 shown in FIG.
The output terminal of the inverter 81 is connected to the input terminal of the inverter 81, and the sixth trigger control signal B3 is sent from the output terminal of the inverter 81 to the main circuit 104 side. Further, the output terminal of the FF circuit 6 is connected to one input terminal of an AND gate 82 and also to the trigger input terminal of a pulse generation circuit 86.

An oscillation circuit 8 is connected to the other input terminal of the AND gate 82.
The output terminal of 4 is connected to one input terminal of the AND gate 85. The oscillation circuit 84 is connected to one end of a resistor 84a and one end of a capacitor 84b for determining the oscillation frequency, and the other end of each of the resistor 84a and capacitor 84b is supplied with a positive voltage power source B. connected to the terminal. The output terminal of the AND gate 82 is connected to the count input terminal of the counter circuit 860. This counter circuit 86 is for setting the light emission interval of multiple light emission, and the light emission interval setting data y1 is inputted to the circuit 86. The output terminal of the counter circuit 86 is connected to a trigger input terminal of a pulse generation circuit 87, and the output terminal of the circuit 87 is connected to one input terminal of an OR gate 88. A light emission start signal B4 is sent from the output end of the OR gate 88 to the main circuit 104 side.

The output terminal of the AND gate 85 is connected to the count input terminal of the counter circuit 89. This counter circuit 89
is for determining the discharge timing of the light emission stop capacitor C511C521C53, and the discharge timing setting data y2, which is set to correspond to a time shorter than the light emission interval time corresponding to the light emission interval data 3'+Vc, is input. There is. The output terminal of this counter circuit 89 is connected to the trigger input terminal of a pulse/generating circuit 90.
The output terminal of 0 is connected to one input terminal of the AND gate 91, and the FF circuit 92 is reset iVCM[. Then, from the output end of the pulse generation circuit 90 to the main circuit 1
A discharge control signal B5 is sent to the 04 side.

The output terminal of the pulse generating circuit 85 is connected to one input terminal of an OR gate 93 and the other input terminal of an OR gate 88 . The output terminal of the OR gate 93 is connected to the set input terminal of the F'F circuit 920 and also to the count input terminal of the counter circuit 94.

This counter circuit 94 is for setting the number of times of light emission per frame in multi-flash photography, and the number of light emission setting data y5 is input to this circuit. The output terminal of the counter circuit 94 is connected to the set input terminal of the FF circuit 950, and the output terminal of the FF circuit 95 is connected to the other input terminal of the AND gate 91. The output terminal of the AND gate 91 is connected to the FF circuits 6, 95 . Counter circuit 86°8
9. Each reset end of 94 and JK type FF described later
K is connected to the reset terminal of circuit 96.

The output terminal of the OR gate 93 is connected to the clock input terminal CK of the JK type FF circuit 96. The input terminal of the circuit 960 is connected to the Q output terminal and to the trigger input terminal of the pulse generation circuit 97, and the first trigger control signal B1 is sent from the output terminal of the circuit 97 to the main circuit 104 side. It has become so.

The J input terminal of the JK type FF circuit 96 is connected to the Q output' terminal and also to the trigger input terminal of the pulse generating circuit 9. A trap is configured such that the second trigger control signal B2 is sent from the output end of the circuit 98 to the main circuit 104 side.

In the control circuit 204 VC shown in FIG.
A discharge control signal B5 is sent to the main circuit 104 side from the output terminal of the pulse generating circuit 302.
The output terminal of is connected to the clock input terminal of the JK type F'F circuit 96.

The output terminal of the pulse generating circuit 5 is the F l” circuit 303.
is connected to the set input terminal of 1 and the main circuit 104
A light emission start signal B4 is sent to the side.

The output terminal of the FF circuit 303 is set to 5 so that the sixth trigger control signal B3 is sent to the main circuit 104 side via the inverter 304. The output terminal of the FF circuit 303 is connected to one input terminal of an AND gate 305, the output terminal of the oscillation circuit 84 is connected to the other input terminal of the AND gate 305, and the output terminal of the AND gate 305 is connected to one input terminal of the AND gate 305. It is connected to the count input of circuit 306. This counter circuit 306 is used to prevent the light emission trigger operation from malfunctioning during flash photography in conjunction with the motor drive, and is input with setting data y4 corresponding to a predetermined time period, which will be described later.

The output terminal of the counter circuit 306 is connected to the pulse generation circuit 30.
The reset signal R connected to the trigger input terminal of the circuit 307 and sent from the output terminal of the circuit 307 is transmitted to the JK type FF circuit 96.
connected to the reset end of the In addition, the pulse generation circuit 5
The output terminal of is connected to the reset terminal of the counter circuit 306.

In this embodiment configured as described above, when performing multi-flash photography, the main circuit 104 shown in FIG. 11 described above and the control circuit 203 shown in FIG. 12 described above are combined.In the initial state, As shown in FIG.
．． B2. B4. B5 are both at the KL level, and the third trigger control signal B3 is at the H level.

The H level signal of the third trigger control signal B3 is applied to the transistor Q720 through the resistor R76, so the transistor Q72 is turned on and the residual charge in the commutating capacitor C2 is discharged.

Now, when the tuning contact 1 is closed with the shirt release, the output of the FF circuit 6 is inverted to the H level in the same manner as described above, and accordingly, the third trigger control signal B3 is lowered to the L level KW. Transistor Q72 is turned off. At the same time, the pulse generating circuit 83 is triggered, and an H level one-shot pulse is generated at the output terminal of the circuit 83. This pulse passes through the OR gate 93 and enters the counter circuit 94.
When K is input, the F'F circuit 92 is set.

Then, since the output of the FF circuit 92 is inverted to the H level VC, the AND gate 85 is opened and the output pulse of the oscillation circuit 84 is input to the counter circuit 89, which starts counting.

At the same time, the AND gate 82 is opened by the H level output of the F circuit 6, and the output pulse of the oscillation circuit 84 is input to the counter circuit 86 to start counting.

The output pulse of the pulse generating circuit 83 is output from the OR gate 93.
is supplied to the clock input terminal of the JK type FF circuit, inverts the 96° Q output of the circuit to H level, and generates a one-shot pulse of KH level at the output end of pulse generation circuit 97. The pulse is the first trigger control signal B, which is connected to resistor R73, resistor R7□ and capacitor C2.
, is applied to the gate of thyristor Q71 through the parallel circuits of , and turns on thyristor Q71. When the same thyristor Q7N turns on, line 41 → anode/cathode of thyristor Q71 - trigger capacitor C2 →
Since the charging current to the trigger capacitor C2 flows through the path of the primary coil of the trigger transformer T → 2 in - 1) o, high voltage is generated in the secondary coil of the trigger transformer T, and the flash discharge tube XL is triggered. . In addition, thyristor Q7
1 is turned off upon completion of charging the trigger capacitor C2.

At the same time, the H level pulse of the pulse generating circuit 83 is transmitted to the H level light emission start signal B via the OR gate 88.
4, a first thyristor Q, through a parallel circuit of a resistor R8, a resistor R7, and a capacitor C5 in sequence. is applied to the gate of the same thyristor Q,. turns on. First thyristor Q,. When turned on, the flash discharge tube XL starts emitting light in the same manner as described above, and the light emission stop capacitor C51#
The amount of light emitted depends on the capacitance of either C521C53. ' j (1) t (
') 21' Q+. b'Nn'i! i: R.J.
J T k tx v 11iil t Irista Q I
o is turned off.

After that, when a count-up output is generated from the counter circuit 89, the pulse generation circuit 90 is triggered by the output, and the H level output pulse of the circuit 90 is applied as a discharge control signal B5 to the resistor R,1, the resistor R3, and the capacitor C6. Since the voltage is applied to the second thyristor Q20 through the parallel circuit, the same thyristor Q20 is turned on. When the second thyristor Q2° is turned on, the capacitor C511 for stopping light emission
C52# C5! The charge charged in either of the transistors S is instantly discharged via the diode D71 in the same manner as described above.

At the same time, the FF circuit 92 is reset by the H level output pulse of the pulse generating circuit 90, and the FF circuit 92 is reset.
Since the output of 2 is inverted to L level, AND gate 85
is closed.

After that, when the counter circuit 86 counts up, a pulse of the output KH level is generated from the same circuit 86, and this pulse triggers the pulse generation circuit 87, and ILf1
The H-level one-shot pulse of the circuit 87 is sent to the first thyristor Q as the light emission start signal B4 through the OR gate 8, as described above. Turn on again.

At the same time, the H-level output pulse of the pulse generating circuit 87 sets the FF circuit 92 again via the OR gate 95, thereby opening the AND gate 85. Then, counting by the counter circuit 89 is restarted. At the same time, the H level pulse of the pulse generating circuit 87 is inputted to the clock input terminal of the JK type F'F circuit 96 via the OR gate 93, so that the Q output terminal is inverted to the H level. Correspondingly, the pulse generating circuit 98 is triggered, and a one-digit pulse of the KH level is generated. This pulse turns on the trigger thyristor QT as a second trigger control signal B2 through a parallel circuit of resistor R5, resistor R4, and capacitor C3 in sequence. Then, the trigger capacitor C2 charged via the thyristor Q71 is discharged, and the discharge current at this time flows to the primary coil of the trigger transformer T, so high voltage is generated in the secondary coil of the trigger transformer T and the flash discharge tube XL is triggered. At the same time, the counter circuit 94 is incremented by one force by the output pulse of the pulse generating main circuit 83.

The small light emission performed in this manner is controlled by the counter circuit 91.
Therefore, the process is repeated until a predetermined number of times of light emission is reached, and when the counter circuit 94 detects that the number of times of light emission has been reached, the output of the circuit 94 becomes H level. Then, the FF circuit 95 is set and the AND gate 91 becomes -
1. When the discharge control signal B5 rises to H level, each part of the circuit is reset by the reset signal R sent from the output terminal of the AND gate 91, and accordingly, the third trigger control signal B3 is inverted to H level and the series of operations of the multi-emission strobe greeting is completed.

On the other hand, when performing strobe scanning in conjunction with a motor drive device, the main circuit 104 shown in FIG. 11 and the control circuit 204 shown in the thirteenth factor are combined.

In the initial state Fa, the signal B4. B2.
Both B4 and B5 are at L level and the third trigger signal B3 is at H level.
level. Therefore, as before, the transistor Q
, 2 are turned on, and the charge remaining in the trigger capacitor C2 is discharged.

Now, when the tuning contact, point 1, is closed with the first shirt release in conjunction with the motor drive, a one-shot pulse of H level is sent from the pulse generation circuit 5 as the main light emission start signal B4 in the same manner as described above. The signal is sent to the circuit 104 side and turns on the first thyristor Q1°. At the same time, the %FF circuit 303 is set, so the third trigger control signal B3 goes down to L level, and accordingly, the transistor Q72 turns off. At this time, a pulse at the level of the first trigger control signal BtlCH is generated in the same manner as described above, so that the same signal B turns on the thyristor Q71 as described above. Therefore, the flash discharge tube XL is triggered and starts emitting light in the same manner as described above. Thereafter, as charging of any of the light emission stopping capacitors C54, C52, and C53 is completed, the thyristor Q+o of M1 is turned off and light emission is stopped.

Thereafter, when the second shirt release is performed, the Q output terminal of the JK type FF circuit 96 is inverted to the H level as an H level one-shot pulse is generated in the pulse generating circuit 5 in the same manner as described above. Then, an H level pulse is generated as the second light emission stop signal B2, and the trigger thyristor QT is turned on to trigger the flash discharge tube XL in the same manner as described above, and flash light emission is performed in the same manner.

The counter circuit 306 is reset and starts counting every time the tuning contact 1 is closed, and when the count number at this time reaches a count number corresponding to the setting data y4, it triggers the pulse generation circuit 607 and resets the counter circuit 306. Forcibly generates the signal R and sets the third trigger control signal B3 to H.
A trap is created to raise the level and discharge the residual charge in the capacitor C2. This is because if the time from one shirt release to the next shirt release is long, the charge in the trigger capacitor C2 gradually discharges its charge due to self-discharge, and the trigger thyristor QT This is to prevent the voltage from being sufficient to trigger the flash discharge tube XL even when the flash discharge tube XL is turned on, thereby causing a firing error. Good.

In each of the above embodiments, a second thyristor Q20 for instantaneously discharging the charge charged in the capacitor C4 for stopping light emission is connected to 5 as shown in FIG. 15 (AJ or FIG. 15(B)). However, as shown in FIG. 15(C) or FIG. 15(D), the capacitor C for stopping light emission is
The impedance element Z is connected in series during the discharge loop of No. 4.

You can also connect. With this configuration, the current when discharging the charge in the capacitor C4 for stopping light emission is limited, so the second thyristor Q20 can be protected, and in particular, the capacitor C4 for stopping light emission can be protected.
It is effective when the capacity of 4 is large, in other words, when there are many light units per small light emission.

Furthermore, instead of the second thyristor Q20 in each of the above embodiments, a switching transistor Q'20 may be connected as shown in FIG. 16(C) or FIG. 16(Bl). As shown in Figure M16 (D), the impedance element Zo is connected to a switching transistor Q'20 for discharging the capacitor C4 in a circuit inserted in the discharge loop of the capacitor C4 for stopping light emission.
You may also connect it.

Further, in each of the above embodiments, the flash discharge tube XL is connected to the line No. 0 via the first thyristor Qto and the light emission stopping capacitor C4 in sequence, but it may be configured as shown in FIG. . In other words, flash release i1? XL is connected to the line 13o K via the anode/cathode of the diode D, o, the light emission stopping capacitor C4, and the anode/cathode of the first thyristor Q1o in this order, and the cathode of the diode [)too is connected to the line 13o. D
A first thyristor Q, by configuring it through the anode-cathode of I, .

When turned on, line 4 → coil L, → flash discharge tube XL → anode/cathode of diode D100 →
Light emission stop capacitor C4 → first thyristor Q ro
A flash discharge current flows in the anode/cathode line of &i) of eo. And the above capacitor C for stopping light emission
When the second thyristor Q20 is turned on to discharge the charge stored in the second thyristor Q20, the path from the anode/cathode of the diode DIOI → line 21 → the anode/cathode of the second thyristor Q20 → the light emission stopping capacitor C4 Therefore, the charge in the capacitor C4 is instantly discharged. Naturally, in this example as well, the above first
Figure 5 (C).

16(D) and the modified examples shown in FIGS. 16(A) to 16(D), of course.

(Effects of the Invention) As described above, according to the present invention, light emission by a flash discharge tube is performed via a light emission stopping capacitor connected in series in the discharge loop of the flash discharge tube, and the light emission is stopped along with this light emission. Since the light emission stops when the capacitor is charged, there is no need to provide a light emission stop control circuit using a commutating capacitor as in conventional circuits, which ensures reliable circuit operation and simplifies the circuit. can be achieved.

Also, start the next emission after stopping the emission;
This is particularly effective for dynamic flat light emitting strobes, as the distance between the two can be made extremely small.

[Brief explanation of the drawing]

FIG. 1 is an electric circuit diagram of a light emission control circuit in a strobe device showing a first embodiment of the present invention, FIG. 2 is a time chart for explaining the operation of the circuit shown in FIG. 1, and FIG. is an electric circuit diagram showing a main circuit of a light emission control circuit in a strobe device according to a second embodiment of the present invention; FIG. 4 is an electric circuit diagram of a control circuit connected to the main circuit shown in FIG. 3 above; 5 is a time chart for explaining the operation of the circuit shown in FIGS. 3 and 4 above, and FIGS. 6 and 7 are modified examples of the main circuit shown in FIGS. 1 and 3 above. 8 is an electric circuit diagram showing a light emission control circuit in a strobe device according to a third embodiment of the present invention, and FIG. 9 is an electric circuit diagram showing a light emission control circuit in a strobe device according to a fourth embodiment of the present invention. FIG. 10 is an electric circuit diagram showing a control circuit connected to the main circuit shown in FIG. 9 above. ! FIG. 11 is an electric circuit diagram showing the main circuit of the light emission control circuit in the sports equipment of the fifth embodiment of the present invention, and FIGS. 12 and 13 show the main circuit connected to the main circuit shown in FIG. 11 above. 14 is a time chart for explaining the operation in the fifth embodiment, and FIGS. 15(A) and 15(B) show only the main parts of each of the above embodiments. The electrical circuit diagrams shown in Fig. 15(C) and (D) are the same as Fig. 15(A) above.
, CB), electrical circuit diagrams 16-(A) to (D) are electrical circuit diagrams 16-(A) to (D) showing modified examples of the circuit shown in FIGS.
) is an electrical circuit diagram showing a modification of the circuit shown in FIG.
FIG. 18 is an electric circuit diagram showing only the main parts of a conventional series-controlled strobe. FIG. C0...Main capacitor Q1o...First thyristor (first switching element) C...Capacitor for stopping light emission Q...Second thyristor (second switching element) element) 200.201.202, 203, 204...
...Control circuit light emission interval fexri! va Ma 15th Ward - 1■ I/O Ward Procedures Amendment (Spontaneous) Indication of the case 1981 Patent Application No. 226259 Title of the invention Relationship to the case of person who corrects the light emission control circuit in a strobe device Location of the patent applicant 2-43-2 Hatagaya, Shibuya-ku, Tokyo Name (037) Olympus Optical Industry Co., Ltd.
Buried Address: 5-52614 Matsubara, Setagaya-ku, Tokyo Name: (7655) Fujikawa Nanabe;)j(
5. Details of the amendment in the "Detailed Description of the Invention" column of the specification to be amended (1) "Open" written in line 16 of page 18 of the specification. After , it is written at the end of line 15 on page 18 of the same page. JNo-% (2) At the end of the 7th line on page 19 of the same page, after the ``ru.'', ``Also, the count of the output pulses of the oscillation circuit 15 is the counter circuit 17 (to which the total light time is set)''. (3) "The same circuit 1" described in page 21, line 18 of the same.
8" is changed to "Same circuit 17." (4) "Circuit 21" written in the last line of page 21 of the same
is changed to "Circuit 20". (5) Change the r HJ mentioned in the 27th purchase to “L”
Change it to Go. (6) Delete the text after "Pulse is" written in line 11 of page 65 and before "■~■level" written in line 12 of page 65, and substitute ",". . (In the 10th line of page 38 of the same statement, “by luminescence” is changed to “by luminescence”)
It was changed to ``with luminescent photography''.

Claims (1)

[Scope of Claims] A series circuit of a flash discharge tube, a first switching element, and a light emission stopping capacitor connected in a discharge loop of a main capacitor, and a second circuit forming a discharge loop of the light emission stopping capacitor.
a switching element; a light emission start signal that turns on the first switching element; and a light emission start signal that turns on the first switching element;
a control circuit that generates a discharge control signal that turns on a switching element; and a control circuit that generates a discharge control signal that turns on a switching element; A light emission control circuit for a strobe device, characterized in that the electric charge charged in the light emission stopping capacitor is discharged by emitting light and turning on the second switching element.