JPS6110233Y2 - - Google Patents

Description

[Detailed description of the invention] This invention relates to the improvement of an electronic timer device that effectively utilizes a large-scale integrated circuit for watches that includes a time counter circuit, a memory circuit, etc., and prevents malfunctions in the event of a power outage. This is what I did.

In recent years, as the size of programs in FM broadcasts and TV broadcasts has become larger, it has become common for one program to last over an hour, ranging from 90 minutes to 120 minutes. Currently, it is impossible to record the entire program using conventional equipment whose operating time is limited to a maximum of 59 minutes.

For this reason, the inventors have already used two large-scale integrated circuits for watches and applied the timer operation signal generated from the first large-scale integrated circuit for watches to the input terminal of the flip-flop circuit for generating the timer output. At the same time, by using this signal to release the reset of the second large-scale integrated circuit, and applying a timer activation signal from the second large-scale integrated circuit for a watch after a predetermined time to the reset input terminal of the flip-flop circuit, We proposed a timer device that can set the timer operating time to a long time of one hour or more and is easy to implement.

In the device configured as described above, a differential circuit is connected to the power supply in order to ensure that the flip-flop circuit remains in the reset state when the power is turned on.
The output signal from the differentiating circuit generated by the power supply current flowing through the differentiating circuit when ON is applied to the reset input terminal of the flip-flop circuit.

Incidentally, since the large-scale integrated circuit for a watch and the flip-flop circuit in this type of device generally have different operating voltages, there is a risk that the timing of the operation of the two circuits will deviate in the event of a power outage. In other words, if a power outage occurs while the timer is operating, and the power is restored before the OFF designation for the flip-flop circuit of the integrated circuit disappears and the charge in the capacitor of the differential circuit is not completely discharged, the output of the flip-flop circuit will be This will cause a malfunction as it is left out.

Therefore, this invention uses a switching circuit driven by the output of the flip-flop circuit to short-circuit the differentiating circuit at the same time that the timer operation starts at the set time, thereby discharging the charge in the capacitor of this differentiating circuit. By configuring this, the purpose is to prevent malfunction by turning off the timer output from the flip-flop circuit whenever a power outage occurs.

Embodiments of this invention will be described below with reference to the drawings.

In Figure 1, E is an alternating current, REC is a rectifier circuit, and LSI ₁ and LSI ₂ are large-scale integrated circuits for clocks that integrate time counter circuits, memory circuits, etc. (not shown), and generate a timer activation signal at a set time. However, it has a timer function that generates a timer stop signal after counting a predetermined time (59 minutes). T.D.C.
are the display output terminals of the integrated circuits LSI ₁ and LSI ₂ above.
A display circuit for hours, minutes, and seconds is commonly connected to X ₁ and X ₂ via a display switching circuit GC, and FFC is a flip-flop circuit for generating timer output.The set input terminal SE and reset input of this flip-flop circuit FFC are The above integrated circuit LSI ₁ ,
Each timer out terminal TO ₁ and TO ₂ of LSI ₂ are electrically connected. The CLC always restricts the second integrated circuit LSI ₂ to the reset state, and
A reset release circuit that receives a timer operation signal from the second integrated circuit LSI ₁ to release the reset state of the second integrated circuit LSI ₂ , and includes, for example, a switching transistor TR, resistors R ₁ and R ₂ , and a diode D ₁ .
_D4 , etc., and the cathode sides of diodes _D1 to _D3 are respectively connected to the time set input terminals S, F, SEC (S is SLOW sending, F is FasT sending, SEC is second reset) of the integrated circuit LSI ₂ . The output terminal Q of the flip-flop circuit FFC is connected to the base pole of the switching transistor _TR1 . The output terminal Q of the flip-flop circuit FFC is electrically connected to the timer off-in terminals TI ₁ and TI ₂ of the LSI ₁ and LSI ₂ , respectively. RC is a relay circuit connected to the output side of the flip-flop circuit FFC to open and close the power supply (not shown) for a load L such as a radio, and includes a relay RX, a switching transistor TR ₂ connected in series with this relay RX, and a relay contact.
Consists of Xa. INC is a differentiator circuit connected to the power supply E side, and when the power supply E is turned on, its output locks the flip-flop circuit FFC to the reset state, and the resistor _R3 , capacitor C, and flip-flop circuit FFC are built in. It consists of a diode _D5 . SWC is a switching circuit connected to the above differential circuit INC, which includes the other relay contact Xb of the above relay Rx, a normally closed contact Sa inserted on one power line side, and a normally open contact inserted on the other power line side. The contact Sb is configured to short-circuit the differential circuit INC with the output of the flip-flop circuit FFC.

Next, the operation of the above configuration will be explained.

Now, the current time is 1:00, the time when the timer starts is 2:00, and the time when the timer ends is 5:00.
minutes. After turning on the power E, first, the first integrated circuit LSI ₁ stores the time 2:00 using an external switch, and the second integrated circuit LSI ₂ stores the time 2:00 for 3 hours (5-2 hours).
time). When the above power supply E is turned on, since the relay circuit RC is not operating, the relay contact Xb that constitutes the switching circuit SWC is on the normally closed contact Sa side, and the current from the rectifier circuit REC flows to the differentiator circuit INC. , the pulse signal generated by this differentiator circuit INC is sent to the above flip-flop circuit.
The flip-flop circuit FFC is set in a locked state by being applied to the reset input terminal RE of the FFC.

At the set time of 2:00, the first integrated circuit
A timer activation signal is generated at the timer out terminal TO ₁ of LSI ₁ , and this signal is sent to the flip-flop circuit.
The reset signal is applied to the set input terminal SE of the FFC, and in conjunction with this, the output signal from the output terminal Q of the flip-flop circuit FFC is applied to the reset release circuit CLC. At this time, the output signal is input to the timer off-in terminal TI ₁ of the first integrated circuit LSI ₁ , so that the clock pulse P ₁ of the predetermined time (59 minutes) in the integrated circuit LSI ₁ is wiped out.

On the other hand, the second integrated circuit LSI ₂ is held in the reset state by applying the voltage Lc from the reset release circuit CLC to the time set input terminals S, F, and SEC until the set time reaches 2:00. However, at the same time that the timer activation signal is generated from the first integrated circuit LSI ₁ , the transistor TR ₁ becomes conductive due to the output signal from the flip-flop circuit FFC, and the voltage Vc is applied to the time set input terminals S and F. , SEC is no longer applied, so the integrated circuit LSI ₂ is released from reset and starts a timekeeping operation.

At 5:00, a timer activation signal is generated at the timer-out terminal _TO2 of the integrated circuit _LSI2 .
This signal is applied to the reset input terminal RE of the flip-flop circuit FFC. At this time, a signal from the inverted output of the flip-flop circuit FFC is applied to the timer off-in terminal of the _second integrated circuit LSI2.
Since the timer output signal from flip-flop circuit Q is applied to _TI2 , a timing pulse _P2 of the specified time (59 minutes) in integrated circuit _LSI2 is inserted. As a result, relay circuit RC which receives the timer output signal from flip-flop circuit Q operates to open and close the power supply to load L such as a radio. In other words, since the output of flip-flop circuit FFC is controlled regardless of the timing operation of each integrated circuit _LSI1 , _LSI2 of the specified time (59 minutes), the timer operation can be performed for a long period of time, such as one hour.

By the way, if a power outage or a large fluctuation in the power supply voltage occurs after the timer operation starts at the set time of 2:00, the output of the flip-flop circuit FFC is always stopped. In other words, at the same time as the timer operation starts, the output signal from the output terminal Q of the flip-flop circuit FFC turns on the transistor _TR2 .
As a result, the contact Xb of the switching circuit SWC shifts to the normally open contact Sb side and short-circuits the differential circuit INC, and this short-circuit of the differential circuit INC causes the accumulation of the capacitor C that had been charged up to that point. The charge is discharged as the power supply current IC shown by the silver wire.
If a power outage occurs in this state, the power to relay RX is cut off, so relay contact Xb of switching circuit SWC is returned to the normally closed contact Sa side. When the above-mentioned power outage is restored, the rectified output from the power supply E side flows into the capacitor C of the differentiating circuit INC as a charging current, so the flip-flop circuit FFC is restrained in the reset state by the pulse signal from this differentiating circuit INC, and the above-mentioned flip-flop circuit FFC output is stopped.

Note that the switching circuit in the above embodiment
The SWC is composed of a contact switching means such as the relay contact Xb of the relay circuit RC, but as shown in Figure 2, a non-contact switching means is connected to the low potential side of the switching transistor TR ₂ , for example. It may be constructed of a light-emitting diode LED and a phototransistor PTR that short-circuits the differential circuit INC with light from the light-emitting diode LED. In this case, in addition to producing the same effects as in the above embodiment, there is no fear of contact failure, and even short-term power outages can be quickly responded to, and reliability is improved.

As described above, this invention has a simple configuration in which a switching circuit that short-circuits the differentiating circuit with the output of the flip-flop circuit is connected to the differentiating circuit, thereby making it possible to reliably prevent malfunctions in the event of power supply voltage fluctuations due to power outages, etc. An electronic timer device can be provided.

[Brief explanation of the drawing]

FIG. 1 is an electric circuit diagram showing an example of an electronic timer device according to the invention, and FIG. 2 is an electric circuit diagram showing a modification of the main part of the device. LSI ₁ , LSI ₂ ...Large scale integrated circuit for watches, FFC
...Flip-flop circuit, INC... Differential circuit,
RC...Relay circuit, SWC...Switching circuit, E...AC power supply.

Claims (1)

[Scope of utility model registration request] A first large-scale clock integrated circuit LSI ₁ that generates a timer operation signal at a set time and a timer operation stop signal after counting a predetermined time, and has the same function as the first clock integrated circuit LSI ₁ ; The second circuit whose reset is canceled by the timer activation signal from this integrated circuit LSI ₁
a large-scale replica integrated circuit LSI ₂ for watches, and a timer that is set by a timer activation signal from the first integrated circuit LSI ₁ and reset by a timer activation signal from the second integrated circuit LSI ₂ after a predetermined period of time has elapsed. Flip-flop circuit FFC for output generation and AC power supply E
In an electronic timer device equipped with a differential circuit INC connected to the side and configured to lock the flip-flop circuit FFC in a reset state when the power is turned on, when the flip-flop circuit FFC generates a timer output, the output side of the flip-flop circuit FFC An electronic timer device in which a switching circuit SWC that short-circuits the differential circuit INC via a relay circuit RC connected to the differential circuit INC is connected to the differential circuit INC.