JPS61101875A - Image data processing system - Google Patents

Abstract

PURPOSE:To reduce the number of access to the image memory by disabling an access to the block of no data as referring to the flag when transferring the data. CONSTITUTION:An image memory 1 is constituted respectively of 4096 bits in the (i) and (j) directions of the matrix. The memory 1 is, for instance, divided into rectangles of 16X16 bits, and a flag is attached to each block. A flag memory 2 is specified address by registers 3 and 4. When the data A part of the memory 1 starts writing from addresses 6, 10, a control circuit 6 writes a flag F0 in the correspondent address '0', '0' in the memory 2. On one hand, the control circuit 6, detecting the carry generating, writes the flag F0in the next address '0', '1'. Thus, when writing the image data in the memory 1, correspondent flags are stored in the memory 2. And by this, when transferring image data from the memory 1, the transfer can be performed without access of the flag-lacking addresses to the memory 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image data processing method, and particularly to an image data processing method that reduces the number of accesses to an image memory.

[Conventional technology]

Characters, vectors, images, etc. that are output to a printing device, display device, etc. are expanded into an image memory specified by a two-dimensional address, and the contents of this image memory are generally printed or displayed as output data. Used in processing systems. However, in order to transfer the contents of the image memory, it is necessary to access the image memory and retrieve the data. This access sequentially accesses all addresses in the image memory. On the other hand, characters etc. developed in the image memory are not developed over the entire area of the image memory. Therefore, accessing the expanded space is wasteful and reduces processing power.

[Problem that the invention seeks to solve]

In view of the above-mentioned conventional situation, the present invention provides an image data processing method that particularly reduces the number of accesses to the image memory, and more specifically, it is an object of the present invention to provide an image data processing method that reduces the number of accesses to the image memory. This is an attempt to prevent a decline in processing performance without accessing the memory space.

[Means for solving problems]

A means for solving the above problems is to divide the image memory to form blocks in an image processing system that transfers image data from an image memory that stores image data, and to A flag is set for the presence or absence of the image data, and the flag is stored in the flag storage area that is stored in units of blocks, and when the image data is transferred, the image memory without the flag is set in the flag storage area. This is an image data transfer method that transfers data without accessing it.

[Effect]

The above image data transfer method divides the image memory into blocks and when expanding the image data,
The presence or absence of data is stored in a flag storage area for each block, and when data is transferred, the flag is referenced and blocks without data are not accessed, reducing the number of accesses.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram for explaining the image data processing method of the present invention, FIG. 2 is a block diagram for explaining flags for rectangular block division, and FIG. 3 is a schematic diagram for explaining rectangular divided blocks. , FIG. 4 is a block diagram of the present invention in the case of horizontal division, and FIG. 5 is a block diagram of the present invention in the case of vertical division.

The image memory in Fig. 3 is composed of a matrix (4096 bits (4096 x 4096) in the i and D directions each).
) vias) and a flag is attached to each block, a flag storage area of (256×256) bits (referred to as rear flag memory) is required.

As shown in FIG. 1, the flag memory 2 receives addresses via a flag address control circuit 5 from a register 3 that specifies an i-direction 1 address and a register 4 that specifies a j-direction address. Note that registers 3 and 4 are composed of 12 bits, the upper 8 bits are the address of flag memory 2, and all bits (12 bits) indicate the 1+J address of image memory 1.

The address of the image memory 1 is controlled by a control circuit 6. Note that the image data to be developed in the image memory 1 is input from the register 7.

The image data in the register 7 is also input to the control circuit 6. The control circuit 6 controls the flag memory 2 according to the data length of the image data and the designated image memory division method (rectangular division, horizontal division, vertical division).

Note that horizontal and vertical division will be described later.

Details of rectangular division will be explained using FIG. 3. It is assumed that image data is written into the image memory 1, as shown by diagonal lines in the figure, consisting of a data part A consisting of 16 horizontal bits and 8 parts of data consisting of 9 vertical bits. Data A,
The first addresses of part B are all addresses (i, j, 6 .
10).

The address of flag memory 2 is register 3 as described above.
and 4 are allocated in the upper 8 bits, respectively. Therefore, a rectangular range of 16×16 image memory corresponding to the lower four bits of registers 3 and 4 is allocated to one bit of flag memory 2. The data part A exceeds the 16th bit boundary in the horizontal direction. Therefore, flags must be attached to addresses (0, 1) and (0, 2) in flag memory 2. This function is performed by full adders 61 and 62 provided in the control circuit 6 and having a block boundary determination function.

The lower 4 bits of registers 3 and 4 are input to full adders 61 and 62, respectively, as well as [bit length of data - 1 bit] to be written to image memory 1, and these are respectively fully added. Note that the control circuit controls whether to perform horizontal boundary determination or vertical boundary determination based on a direction designation signal input to the control circuit 6.

For example, if the signal D is set to a logical value of "0" when determining the boundary of the data section A in the horizontal direction, the control circuit 6 controls the register 4 and the full adder 62 when the signal D'0. The number in the register 4 shown in the figure is the start address of the data section. The lower 4 bits rloloJ and the horizontal data length 16-1, ie, rllll'' are input to the full adder 62. When the data section starts writing from address (6, 10), the control circuit 6 sends the corresponding flag memory 2
Write flag FO to address (0,0).

On the other hand, the control circuit 6 detects the occurrence of a carry by the full adder 62 and selects the next address (0) of the flag memory 2.
, 1). Note that the upper eight pits of the register 4 are updated due to the occurrence of a carry. In the case of 8 parts of data, the direction designation signal D "1' causes
In the control circuit 6, the register 3 and the full adder 61 are controlled, and the full adder 61 performs the addition of "rollo" and r1000 J, no carry occurs, and the address (0, O) of the flag memory 2 is added. FO only.

As described above, when writing image data to image memory 1, if a flag is set in each 16 x 16 bit rectangular unit of flag memory 2, when image data is transferred from image memory 1, the flag is set. When the memory is referenced, for addresses without flags, the required transfer is performed without accessing the image memory.

As another embodiment, horizontal division will be explained using FIG. 4. As in the embodiment, image memory 1 has 4096
X 4096 Binoto. If this image memory 1 is divided into I x 4096 parts in the horizontal direction, the flag memory 20 will have 4096 bits.

When writing image data to the image memory 1, if there is data in the register 7 that stores the image data, a flag may be set for each address in the register 3 at that time. Therefore, the control circuit 50 is simplified and only needs to be provided with a focus detection circuit 51 that detects the presence or absence of data.

When a bit is detected, the control circuit 50 performs an operation of setting a flag at the corresponding address.

FIG. 5 shows the case of vertical division, which differs from horizontal division in that register 4 is used instead of register 3, and the operation is the same as horizontal division.

〔Effect of the invention〕

As can be understood from the above explanation, the present invention displays the presence or absence of image memory data in the flag storage area in division units, and when transferring data from the image memory, addresses without flags do not access the image memory. data can be transferred to other locations, reducing the number of accesses and improving processing performance.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining the image data processing method of the present invention. FIG. 2 is a block diagram for explaining flags of rectangular block division. FIG. 3 is a schematic diagram for explaining rectangular divided blocks. , FIG. 4 is a block diagram of the present invention in the case of horizontal division, and FIG. 5 is a block diagram of the present invention in the case of vertical division. In the figure, 1 is image memory, 2 is flag memory,
3, 4 and 7 are registers, 5 is a flag address control circuit,
6 indicates a control circuit, respectively. Figure 1 Figure 2 Leap Figure 4 Figure 5 Mu

Claims (1)

[Claims] In an image processing system that transfers image data from an image memory that stores image data, the image memory is divided to form blocks, and a flag is set as to the presence or absence of the image data in the block. , the image is characterized in that the flag is stored in the flag storage area stored in units of blocks, and when the image data is transferred, the image data is transferred without accessing the image memory without the flag in the flag storage area. Data processing method.